OV - exec - Function build_field(global_variables&) [clone .omp

	Function: build_field(global_variables&) [clone .omp_outlined]	Module: exec	Source: build_field.cpp:100-113 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 100 - 113

--------------------------------------------------------------------------------

100: #pragma omp parallel for simd collapse(2)

101:     for (int j = (0); j < (yrange + 1); j++) {

102:       for (int i = (0); i < (xrange + 1); i++) {

103:         field.work_array1(i, j) = 0.0;

104:         field.work_array2(i, j) = 0.0;

105:         field.work_array3(i, j) = 0.0;

106:         field.work_array4(i, j) = 0.0;

107:         field.work_array5(i, j) = 0.0;

108:         field.work_array6(i, j) = 0.0;

109:         field.work_array7(i, j) = 0.0;

110:         field.xvel0(i, j) = 0.0;

111:         field.xvel1(i, j) = 0.0;

112:         field.yvel0(i, j) = 0.0;

113:         field.yvel1(i, j) = 0.0;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41fbe0 LDR	W8, [X2]

0x41fbe4 TBNZ	W8, #31, 41ff54

0x41fbe8 LDR	W9, [X3]

0x41fbec TBNZ	W9, #31, 41ff54

0x41fbf0 SUB	SP, SP, #208

0x41fbf4 STP	X29, X30, [SP, #112]

0x41fbf8 STP	X28, X27, [SP, #128]

0x41fbfc STP	X26, X25, [SP, #144]

0x41fc00 STP	X24, X23, [SP, #160]

0x41fc04 STP	X22, X21, [SP, #176]

0x41fc08 STP	X20, X19, [SP, #192]

0x41fc0c ADD	X29, SP, #112

0x41fc10 ADD	W9, W9, #1

0x41fc14 LDR	W1, [X0]

0x41fc18 ORR	X19, XZR, X4

0x41fc1c ADRP	X0,

0x41fc20 ADD	X0, X0, #360

0x41fc24 SUB	X3, X29, #28

0x41fc28 SUB	X4, X29, #8

0x41fc2c SUB	X5, X29, #16

0x41fc30 STUR	WZR, [X29, #484]

0x41fc34 STR	W1, [SP, #36]

0x41fc38 SBFM	X27, X9, #0, #31

0x41fc3c MADD	X8, X27, X8, X27

0x41fc40 SUB	X20, X8, #1

0x41fc44 MOVZ	W8, #1

0x41fc48 SUB	X6, X29, #24

0x41fc4c MOVZ	W2, #34

0x41fc50 MOVZ	W7, #1

0x41fc54 STP	X20, XZR, [X29, #1008]

0x41fc58 STUR	X8, [X29, #488]

0x41fc5c STR	X8, [SP]

0x41fc60 BL	4034d0

0x41fc64 LDP	X8, X26, [X29, #1008]

0x41fc68 CMP	X8, X20

0x41fc6c CSEL	X20, X8, X20, #11

0x41fc70 CMP	X26, X20

0x41fc74 B.GT	41ff28

0x41fc78 LDR	X22, [X19, #360]

0x41fc7c LDP	X30, X13, [X19, #376]

0x41fc80 LDP	X11, X10, [X19, #400]

0x41fc84 ADD	X28, X20, #1

0x41fc88 SUB	X8, X28, X26

0x41fc8c LDP	X12, X14, [X19, #424]

0x41fc90 LDP	X15, X16, [X19, #448]

0x41fc94 LDP	X17, X18, [X19, #472]

0x41fc98 LDR	X0, [X19, #520]

0x41fc9c LDP	X1, X2, [X19, #496]

0x41fca0 LDR	X3, [X19, #168]

0x41fca4 LDP	X4, X5, [X19, #184]

0x41fca8 LDP	X6, X7, [X19, #208]

0x41fcac LDR	X21, [X19, #256]

0x41fcb0 LDP	X23, X24, [X19, #232]

0x41fcb4 CMP	X8, #2

0x41fcb8 B.CS	41fcc4

0x41fcbc ORR	X25, XZR, X26

0x41fcc0 B	41fe6c

0x41fcc4 STP	X30, X22, [X29, #976]

0x41fcc8 STP	X27, X13, [SP, #48]

0x41fccc SUB	X9, XZR, X27,LSL #32

0x41fcd0 LDUR	X13, [X29, #464]

0x41fcd4 STP	X8, X28, [SP, #16]

0x41fcd8 AND	X8, X8, #8127

0x41fcdc ADD	X25, X26, X8

0x41fce0 UBFM	X28, X26, #32, #31

0x41fce4 STR	X8, [SP, #8]

0x41fce8 ORR	X27, XZR, X8

0x41fcec STR	X9, [SP, #40]

0x41fcf0 HINT	#0

0x41fcf4 HINT	#0

0x41fcf8 HINT	#0

0x41fcfc HINT	#0

(202) 0x41fd00 LDP	X8, X9, [SP, #40]

(202) 0x41fd04 ADD	X19, X26, #1

(202) 0x41fd08 SUBS	X27, X27, #2

(202) 0x41fd0c SDIV	X20, X26, X9

(202) 0x41fd10 ADD	X26, X26, #2

(202) 0x41fd14 MADD	X22, X8, X20, X28

(202) 0x41fd18 SDIV	X30, X19, X9

(202) 0x41fd1c LDUR	X9, [X29, #472]

(202) 0x41fd20 SBFM	X19, X20, #0, #31

(202) 0x41fd24 MADD	X20, X9, X19, XZR

(202) 0x41fd28 SBFM	X22, X22, #29, #63

(202) 0x41fd2c ADD	X20, X13, X20,LSL #3

(202) 0x41fd30 STR	XZR, [X20, X22]

(202) 0x41fd34 MADD	X20, X8, X30, X28

(202) 0x41fd38 MOVZ	X8, #1

(202) 0x41fd3c ADD	X8, X20, X8

(202) 0x41fd40 SBFM	X20, X30, #0, #31

(202) 0x41fd44 MADD	X30, X9, X20, XZR

(202) 0x41fd48 ADD	X9, X13, X30,LSL #3

(202) 0x41fd4c SBFM	X30, X8, #29, #63

(202) 0x41fd50 STR	XZR, [X9, X30]

(202) 0x41fd54 LDR	X9, [SP, #56]

(202) 0x41fd58 MADD	X8, X9, X19, XZR

(202) 0x41fd5c ADD	X8, X11, X8,LSL #3

(202) 0x41fd60 STR	XZR, [X8, X22]

(202) 0x41fd64 MADD	X8, X9, X20, XZR

(202) 0x41fd68 ADD	X8, X11, X8,LSL #3

(202) 0x41fd6c STR	XZR, [X8, X30]

(202) 0x41fd70 MADD	X8, X10, X19, XZR

(202) 0x41fd74 ADD	X8, X12, X8,LSL #3

(202) 0x41fd78 STR	XZR, [X8, X22]

(202) 0x41fd7c MADD	X8, X10, X20, XZR

(202) 0x41fd80 ADD	X8, X12, X8,LSL #3

(202) 0x41fd84 STR	XZR, [X8, X30]

(202) 0x41fd88 MADD	X8, X14, X19, XZR

(202) 0x41fd8c ADD	X8, X15, X8,LSL #3

(202) 0x41fd90 STR	XZR, [X8, X22]

(202) 0x41fd94 MADD	X8, X14, X20, XZR

(202) 0x41fd98 ADD	X8, X15, X8,LSL #3

(202) 0x41fd9c STR	XZR, [X8, X30]

(202) 0x41fda0 MADD	X8, X16, X19, XZR

(202) 0x41fda4 ADD	X8, X17, X8,LSL #3

(202) 0x41fda8 STR	XZR, [X8, X22]

(202) 0x41fdac MADD	X8, X16, X20, XZR

(202) 0x41fdb0 ADD	X8, X17, X8,LSL #3

(202) 0x41fdb4 STR	XZR, [X8, X30]

(202) 0x41fdb8 MADD	X8, X18, X19, XZR

(202) 0x41fdbc ADD	X8, X1, X8,LSL #3

(202) 0x41fdc0 STR	XZR, [X8, X22]

(202) 0x41fdc4 MADD	X8, X18, X20, XZR

(202) 0x41fdc8 ADD	X8, X1, X8,LSL #3

(202) 0x41fdcc STR	XZR, [X8, X30]

(202) 0x41fdd0 MADD	X8, X2, X19, XZR

(202) 0x41fdd4 ADD	X8, X0, X8,LSL #3

(202) 0x41fdd8 STR	XZR, [X8, X22]

(202) 0x41fddc MADD	X8, X2, X20, XZR

(202) 0x41fde0 ADD	X8, X0, X8,LSL #3

(202) 0x41fde4 STR	XZR, [X8, X30]

(202) 0x41fde8 MADD	X8, X3, X19, XZR

(202) 0x41fdec ADD	X8, X4, X8,LSL #3

(202) 0x41fdf0 STR	XZR, [X8, X22]

(202) 0x41fdf4 MADD	X8, X3, X20, XZR

(202) 0x41fdf8 ADD	X8, X4, X8,LSL #3

(202) 0x41fdfc STR	XZR, [X8, X30]

(202) 0x41fe00 MADD	X8, X5, X19, XZR

(202) 0x41fe04 ADD	X8, X6, X8,LSL #3

(202) 0x41fe08 STR	XZR, [X8, X22]

(202) 0x41fe0c MADD	X8, X5, X20, XZR

(202) 0x41fe10 ADD	X8, X6, X8,LSL #3

(202) 0x41fe14 STR	XZR, [X8, X30]

(202) 0x41fe18 MADD	X8, X7, X19, XZR

(202) 0x41fe1c ADD	X8, X23, X8,LSL #3

(202) 0x41fe20 STR	XZR, [X8, X22]

(202) 0x41fe24 MADD	X8, X7, X20, XZR

(202) 0x41fe28 ADD	X8, X23, X8,LSL #3

(202) 0x41fe2c STR	XZR, [X8, X30]

(202) 0x41fe30 MADD	X8, X24, X19, XZR

(202) 0x41fe34 ADD	X8, X21, X8,LSL #3

(202) 0x41fe38 STR	XZR, [X8, X22]

(202) 0x41fe3c MADD	X8, X24, X20, XZR

(202) 0x41fe40 ADD	X8, X21, X8,LSL #3

(202) 0x41fe44 STR	XZR, [X8, X30]

(202) 0x41fe48 MOVZ	X8, #2

(202) 0x41fe4c ADD	X28, X28, X8

(202) 0x41fe50 B.NE	41fd00

0x41fe54 LDP	X9, X8, [SP, #8]

0x41fe58 LDP	X27, X13, [SP, #48]

0x41fe5c LDP	X30, X22, [X29, #976]

0x41fe60 LDR	X28, [SP, #24]

0x41fe64 CMP	X8, X9

0x41fe68 B.EQ	41ff28

0x41fe6c SUB	X19, XZR, X27,LSL #32

0x41fe70 UBFM	X20, X25, #32, #31

0x41fe74 HINT	#0

0x41fe78 HINT	#0

0x41fe7c HINT	#0

(203) 0x41fe80 SDIV	X8, X25, X27

(203) 0x41fe84 ADD	X25, X25, #1

(203) 0x41fe88 MADD	X9, X19, X8, X20

(203) 0x41fe8c SBFM	X8, X8, #0, #31

(203) 0x41fe90 MADD	X26, X22, X8, XZR

(203) 0x41fe94 SBFM	X9, X9, #29, #63

(203) 0x41fe98 ADD	X26, X30, X26,LSL #3

(203) 0x41fe9c STR	XZR, [X26, X9]

(203) 0x41fea0 MADD	X26, X13, X8, XZR

(203) 0x41fea4 ADD	X26, X11, X26,LSL #3

(203) 0x41fea8 STR	XZR, [X26, X9]

(203) 0x41feac MADD	X26, X10, X8, XZR

(203) 0x41feb0 ADD	X26, X12, X26,LSL #3

(203) 0x41feb4 STR	XZR, [X26, X9]

(203) 0x41feb8 MADD	X26, X14, X8, XZR

(203) 0x41febc ADD	X26, X15, X26,LSL #3

(203) 0x41fec0 STR	XZR, [X26, X9]

(203) 0x41fec4 MADD	X26, X16, X8, XZR

(203) 0x41fec8 ADD	X26, X17, X26,LSL #3

(203) 0x41fecc STR	XZR, [X26, X9]

(203) 0x41fed0 MADD	X26, X18, X8, XZR

(203) 0x41fed4 ADD	X26, X1, X26,LSL #3

(203) 0x41fed8 STR	XZR, [X26, X9]

(203) 0x41fedc MADD	X26, X2, X8, XZR

(203) 0x41fee0 ADD	X26, X0, X26,LSL #3

(203) 0x41fee4 STR	XZR, [X26, X9]

(203) 0x41fee8 MADD	X26, X3, X8, XZR

(203) 0x41feec ADD	X26, X4, X26,LSL #3

(203) 0x41fef0 STR	XZR, [X26, X9]

(203) 0x41fef4 MADD	X26, X5, X8, XZR

(203) 0x41fef8 ADD	X26, X6, X26,LSL #3

(203) 0x41fefc STR	XZR, [X26, X9]

(203) 0x41ff00 MADD	X26, X7, X8, XZR

(203) 0x41ff04 MADD	X8, X24, X8, XZR

(203) 0x41ff08 ADD	X26, X23, X26,LSL #3

(203) 0x41ff0c ADD	X8, X21, X8,LSL #3

(203) 0x41ff10 STR	XZR, [X26, X9]

(203) 0x41ff14 STR	XZR, [X8, X9]

(203) 0x41ff18 MOVZ	X8, #1

(203) 0x41ff1c ADD	X20, X20, X8

(203) 0x41ff20 CMP	X28, X25

(203) 0x41ff24 B.NE	41fe80

0x41ff28 LDR	W1, [SP, #36]

0x41ff2c ADRP	X0,

0x41ff30 ADD	X0, X0, #384

0x41ff34 BL	403400

0x41ff38 LDP	X20, X19, [SP, #192]

0x41ff3c LDP	X22, X21, [SP, #176]

0x41ff40 LDP	X24, X23, [SP, #160]

0x41ff44 LDP	X26, X25, [SP, #144]

0x41ff48 LDP	X28, X27, [SP, #128]

0x41ff4c LDP	X29, X30, [SP, #112]

0x41ff50 ADD	SP, SP, #208

0x41ff54 RET

0x41ff58 HINT	#0

0x41ff5c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	build_field.cpp:100-113
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:100-113
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 67% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 12.17 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 1.00 cycles (15.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 368 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	97
loop length	388
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	6.08	6.08	6.00	6.00	5.92	5.92	0.00	0.00	0.00	0.00	15.00	15.00	15.00	8.00	8.00
cycles	4.50	4.50	6.08	6.08	6.00	6.00	5.92	5.92	0.00	0.00	0.00	0.00	15.00	15.00	15.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.00
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

25% of peak load performance is reached (24.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fbe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
TBNZ W8, #31, 41ff54 <_Z11build_fieldR16global_variables.omp_outlined+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
TBNZ W9, #31, 41ff54 <_Z11build_fieldR16global_variables.omp_outlined+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W9, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46dc1c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #360	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X27, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X8, X27, X8, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
SUB X20, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X20, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X26, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X20, X8, X20, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X26, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41ff28 <_Z11build_fieldR16global_variables.omp_outlined+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X19, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X30, X13, [X19, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X11, X10, [X19, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X28, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X8, X28, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X12, X14, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X16, [X19, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X17, X18, [X19, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X0, [X19, #520]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X1, X2, [X19, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X4, X5, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X21, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X23, X24, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 41fcc4 <_Z11build_fieldR16global_variables.omp_outlined+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 41fe6c <_Z11build_fieldR16global_variables.omp_outlined+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X30, X22, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, XZR, X27,LSL #32	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X28, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X8, X8, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X25, X26, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X28, X26, #32, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X9, X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X30, X22, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X28, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41ff28 <_Z11build_fieldR16global_variables.omp_outlined+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X19, XZR, X27,LSL #32	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X20, X25, #32, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46df2c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	build_field.cpp:100-113
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:100-113
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 1.00 cycles (15.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 368 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	97
loop length	388
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	6.08	6.08	6.00	6.00	5.92	5.92	0.00	0.00	0.00	0.00	15.00	15.00	15.00	8.00	8.00
cycles	4.50	4.50	6.08	6.08	6.00	6.00	5.92	5.92	0.00	0.00	0.00	0.00	15.00	15.00	15.00	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.00
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

25% of peak load performance is reached (24.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fbe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
TBNZ W8, #31, 41ff54 <_Z11build_fieldR16global_variables.omp_outlined+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
TBNZ W9, #31, 41ff54 <_Z11build_fieldR16global_variables.omp_outlined+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W9, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46dc1c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #360	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X27, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X8, X27, X8, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
SUB X20, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X20, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4034d0 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X26, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X20, X8, X20, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X26, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41ff28 <_Z11build_fieldR16global_variables.omp_outlined+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X19, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X30, X13, [X19, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X11, X10, [X19, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X28, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X8, X28, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X12, X14, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X16, [X19, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X17, X18, [X19, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X0, [X19, #520]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X1, X2, [X19, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X4, X5, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X21, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X23, X24, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 41fcc4 <_Z11build_fieldR16global_variables.omp_outlined+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 41fe6c <_Z11build_fieldR16global_variables.omp_outlined+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X30, X22, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, XZR, X27,LSL #32	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X28, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
AND X8, X8, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X25, X26, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X28, X26, #32, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X9, X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X30, X22, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X28, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41ff28 <_Z11build_fieldR16global_variables.omp_outlined+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X19, XZR, X27,LSL #32	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X20, X25, #32, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46df2c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403400 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼build_field(global_variables&) [clone .omp_outlined]–	0.02	0.01
○Loop 202 - build_field.cpp:101-113 - exec	0.02	0.01
○Loop 203 - build_field.cpp:101-113 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code