OV - exec - Loop 396

0x425420 FSQRT	D0, D0

0x425424 LDR	X2, [X26, #24]    [1]

0x425428 LDR	X1, [X2]    [3]

0x42542c LDR	X2, [X2, #16]    [3]

0x425430 MADD	X1, X25, X1, X19

0x425434 ORR	X19, XZR, X20

0x425438 STR	D0, [X2, X1,LSL #3]    [2]

0x42543c CMP	X22, X20

0x425440 B.NE	4253e0

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 45 - 45

--------------------------------------------------------------------------------

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.98+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.64
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	ideal_gas.cpp:45-45,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	7.00 - 16.00
CQA cycles if no scalar integer	7.00 - 16.00
CQA cycles if FP arith vectorized	4.28 - 9.78
CQA cycles if fully vectorized	3.50 - 8.00
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.42
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	1.00
P7 cycles	0.42
P8 cycles	1.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	1.50
P13 cycles	1.17
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.75
Inter-iter dependencies cycles	7 - 16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.14 - 0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00 - 4.57
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.64
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	ideal_gas.cpp:45-45,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	7.00 - 16.00
CQA cycles if no scalar integer	7.00 - 16.00
CQA cycles if FP arith vectorized	4.28 - 9.78
CQA cycles if fully vectorized	3.50 - 8.00
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.42
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	1.00
P7 cycles	0.42
P8 cycles	1.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	1.50
P13 cycles	1.17
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.75
Inter-iter dependencies cycles	7 - 16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.14 - 0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00 - 4.57
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	ideal_gas.cpp:45-45
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:45
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: square root

The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.50	0.42	0.33	0.33	1.00	0.42	1.00	0.50	0.50	0.00	1.50	1.17	1.33	0.00	0.00
cycles	0.50	0.50	0.50	0.42	0.33	0.33	1.00	0.42	1.00	0.50	0.50	0.00	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	1.75-3.75
Longest recurrence chain latency (RecMII)	7.00-16.00

Cycles summary

Front-end	1.13
Data deps.	7.00-16.00
Overall L1	7.00-16.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

1% of peak load performance is reached (1.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 425420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P12	P13	P14	Latency	Recip. throughput	Vectorization
FSQRT D0, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	7-16	1.75-3.75	scal (50.0%)
LDR X2, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X2, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MADD X1, X25, X1, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR D0, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.NE 4253e0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	ideal_gas.cpp:45-45
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:45
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: square root

The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.50	0.42	0.33	0.33	1.00	0.42	1.00	0.50	0.50	0.00	1.50	1.17	1.33	0.00	0.00
cycles	0.50	0.50	0.50	0.42	0.33	0.33	1.00	0.42	1.00	0.50	0.50	0.00	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	1.75-3.75
Longest recurrence chain latency (RecMII)	7.00-16.00

Cycles summary

Front-end	1.13
Data deps.	7.00-16.00
Overall L1	7.00-16.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

1% of peak load performance is reached (1.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 425420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P12	P13	P14	Latency	Recip. throughput	Vectorization
FSQRT D0, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	7-16	1.75-3.75	scal (50.0%)
LDR X2, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X2, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MADD X1, X25, X1, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	N/A
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR D0, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X22, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.NE 4253e0 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code