OV - exec - Loop 316

	Loop Id: 316	Module: exec	Source: context.h:69-69 [...]	Coverage: 4.04%

0x420344 LD1D	{Z26.D}, P5/Z, [X7, X0,LSL #3]    [3]

0x420348 LD1D	{Z27.D}, P6/Z, [X10, X0,LSL #3]    [5]

0x42034c SUNPKHI	Z29.D, Z21

0x420350 FCMLT	P14.D, P4/Z, Z26.D, #0

0x420354 FCMLT	P15.D, P4/Z, Z27.D, #0

0x420358 SUNPKLO	Z15.D, Z21

0x42035c UZP1	P13.S, P14.S, P15.S

0x420360 SEL	Z31.S, P13, Z6.S, Z20.S

0x420364 SUNPKLO	Z30.D, Z31

0x420368 SUNPKHI	Z31.D, Z31

0x42036c MAD	Z30.D, P4/M, Z25.D, Z15.D

0x420370 MAD	Z31.D, P4/M, Z25.D, Z29.D

0x420374 LD1D	{Z5.D}, P5/Z, [X1, Z30.D,LSL #3]    [6]

0x420378 LD1D	{Z2.D}, P6/Z, [X1, Z31.D,LSL #3]    [6]

0x42037c SEL	Z14.D, P14, Z24.D, Z23.D

0x420380 SEL	Z31.D, P14, Z23.D, Z24.D

0x420384 MOVPRFX	Z30, Z15

0x420388 MLA	Z30.D, P4/M, Z25.D, Z31.D

0x42038c MAD	Z31.D, P4/M, Z19.D, Z15.D

0x420390 LD1D	{Z28.D}, P5/Z, [X1, Z30.D,LSL #3]    [6]

0x420394 MLA	Z15.D, P4/M, Z25.D, Z14.D

0x420398 MOVPRFX	Z30, Z28

0x42039c FSUB	Z30.D, P5/M, Z30.D, Z5.D

0x4203a0 LD1D	{Z14.D}, P5/Z, [X1, Z15.D,LSL #3]    [6]

0x4203a4 MOVPRFX	Z4, Z30

0x4203a8 FABS	Z4.D, P4/M, Z30.D

0x4203ac FSUB	Z14.D, P5/M, Z14.D, Z28.D

0x4203b0 FMUL	Z30.D, P5/M, Z30.D, Z14.D

0x4203b4 LD1D	{Z13.D}, P5/Z, [X6, Z31.D,LSL #3]    [2]

0x4203b8 FCMGT	P7.D, P5/Z, Z30.D, #0

0x4203bc SEL	Z3.S, P13, Z7.S, Z20.S

0x4203c0 SUNPKLO	Z30.D, Z3

0x4203c4 MOVPRFX	Z31, Z26

0x4203c8 FABS	Z31.D, P4/M, Z26.D

0x4203cc LD1D	{Z15.D}, P7/Z, [X4, Z30.D,LSL #3]    [8]

0x4203d0 FDIV	Z31.D, P5/M, Z31.D, Z13.D

0x4203d4 MOVPRFX	Z13, Z31

0x4203d8 FADD	Z13.D, P7/M, Z13.D, #1

0x4203dc MOVPRFX	Z30, Z4

0x4203e0 FMUL	Z30.D, P7/M, Z30.D, Z13.D

0x4203e4 MOVPRFX	Z5, Z14

0x4203e8 FABS	Z5.D, P4/M, Z14.D

0x4203ec MOVPRFX	Z1, Z30

0x4203f0 FDIV	Z1.D, P7/M, Z1.D, Z15.D

0x4203f4 MOVPRFX	Z13, Z22

0x4203f8 FSUB	Z13.D, P7/M, Z13.D, Z31.D

0x4203fc SEL	Z15.D, P5, Z31.D, Z16.D

0x420400 MOVPRFX	Z30, Z5

0x420404 FMUL	Z30.D, P7/M, Z30.D, Z13.D

0x420408 LD1RD	{Z31.D}, P4/Z, [X9]    [4]

0x42040c FSUBR	Z15.D, P5/M, Z15.D, #1

0x420410 FCMLE	P14.D, P7/Z, Z14.D, #0

0x420414 FDIV	Z30.D, P7/M, Z30.D, Z31.D

0x420418 EOR	P14.B, P7/Z, P14.B, P7.B

0x42041c FADD	Z30.D, P7/M, Z30.D, Z1.D

0x420420 MOVPRFX	Z14, Z17

0x420424 FCPY	Z14.D, P14/M, #1.0000000

0x420428 MOVPRFX	Z0, Z31

0x42042c FMUL	Z0.D, P7/M, Z0.D, Z30.D

0x420430 FDIV	Z0.D, P7/M, Z0.D, Z18.D

0x420434 FMINNM	Z4.D, P4/M, Z4.D, Z0.D

0x420438 FMINNM	Z5.D, P4/M, Z5.D, Z4.D

0x42043c MOVPRFX	Z5.D, P7/Z, Z5.D

0x420440 FMUL	Z5.D, P7/M, Z5.D, Z14.D

0x420444 FMLA	Z28.D, P5/M, Z5.D, Z15.D

0x420448 SEL	Z1.D, P15, Z23.D, Z24.D

0x42044c FMUL	Z26.D, P5/M, Z26.D, Z28.D

0x420450 MOVPRFX	Z13, Z29

0x420454 MLA	Z13.D, P4/M, Z25.D, Z1.D

0x420458 SEL	Z15.D, P15, Z24.D, Z23.D

0x42045c LD1D	{Z30.D}, P6/Z, [X1, Z13.D,LSL #3]    [6]

0x420460 MAD	Z15.D, P4/M, Z25.D, Z29.D

0x420464 MOVPRFX	Z4, Z30

0x420468 FSUB	Z4.D, P6/M, Z4.D, Z2.D

0x42046c LD1D	{Z28.D}, P6/Z, [X1, Z15.D,LSL #3]    [6]

0x420470 MOVPRFX	Z5, Z4

0x420474 FABS	Z5.D, P4/M, Z4.D

0x420478 FSUB	Z28.D, P6/M, Z28.D, Z30.D

0x42047c FMUL	Z4.D, P6/M, Z4.D, Z28.D

0x420480 MAD	Z1.D, P4/M, Z19.D, Z29.D

0x420484 FCMGT	P7.D, P6/Z, Z4.D, #0

0x420488 LD1D	{Z0.D}, P6/Z, [X6, Z1.D,LSL #3]    [2]

0x42048c MOVPRFX	Z29, Z27

0x420490 FABS	Z29.D, P4/M, Z27.D

0x420494 SUNPKHI	Z3.D, Z3

0x420498 FDIV	Z29.D, P6/M, Z29.D, Z0.D

0x42049c LD1D	{Z4.D}, P7/Z, [X4, Z3.D,LSL #3]    [8]

0x4204a0 SEL	Z2.D, P6, Z29.D, Z16.D

0x4204a4 MOVPRFX	Z14, Z28

0x4204a8 FABS	Z14.D, P4/M, Z28.D

0x4204ac MOVPRFX	Z15, Z29

0x4204b0 FADD	Z15.D, P7/M, Z15.D, #1

0x4204b4 FCMLE	P15.D, P7/Z, Z28.D, #0

0x4204b8 MOVPRFX	Z28, Z5

0x4204bc FMUL	Z28.D, P7/M, Z28.D, Z15.D

0x4204c0 FDIV	Z28.D, P7/M, Z28.D, Z4.D

0x4204c4 MOVPRFX	Z4, Z22

0x4204c8 FSUB	Z4.D, P7/M, Z4.D, Z29.D

0x4204cc MOVPRFX	Z29, Z14

0x4204d0 FMUL	Z29.D, P7/M, Z29.D, Z4.D

0x4204d4 FDIV	Z29.D, P7/M, Z29.D, Z31.D

0x4204d8 FADD	Z29.D, P7/M, Z29.D, Z28.D

0x4204dc FMUL	Z31.D, P7/M, Z31.D, Z29.D

0x4204e0 FDIV	Z31.D, P7/M, Z31.D, Z18.D

0x4204e4 FSUBR	Z2.D, P6/M, Z2.D, #1

0x4204e8 EOR	P15.B, P7/Z, P15.B, P7.B

0x4204ec FMINNM	Z5.D, P4/M, Z5.D, Z31.D

0x4204f0 MOVPRFX	Z15, Z17

0x4204f4 FCPY	Z15.D, P15/M, #1.0000000

0x4204f8 MOVPRFX	Z31, Z14

0x4204fc FMINNM	Z31.D, P4/M, Z31.D, Z5.D

0x420500 MOVPRFX	Z31.D, P7/Z, Z31.D

0x420504 FMUL	Z31.D, P7/M, Z31.D, Z15.D

0x420508 FMLA	Z30.D, P6/M, Z31.D, Z2.D

0x42050c FMUL	Z27.D, P6/M, Z27.D, Z30.D

0x420510 ST1D	{Z26.D}, P5, [X3, X0,LSL #3]    [7]

0x420514 ST1D	{Z27.D}, P6, [X5, X0,LSL #3]    [1]

0x420518 ADD	X0, X0, X11

0x42051c WHILELO	P6.D, X0, X8

0x420520 INCW	Z21.S, ALL

0x420524 WHILELO	P5.D, X0, X2

0x420528 B.NE	420344

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 186 - 211

--------------------------------------------------------------------------------

186:           if (node_flux(i, j) < 0.0) {

[...]

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10 - 2.19
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	advec_mom.cpp:186-186,advec_mom.cpp:197-211,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 55.94
CQA cycles if no scalar integer	27.97 - 55.94
CQA cycles if FP arith vectorized	27.97 - 55.94
CQA cycles if fully vectorized	27.97 - 55.94
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	25.50
P9 cycles	25.50
P10 cycles	25.50
P11 cycles	25.50
P12 cycles	5.00
P13 cycles	5.00
P14 cycles	5.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	27.97 - 55.94
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.29
Nb FLOP add-sub	24.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.15 - 8.29
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	3.00
Vectorization ratio all	72.03
Vectorization ratio load	92.31
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	46.67
Vector-efficiency ratio all	95.76
Vector-efficiency ratio load	96.15
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10 - 2.19
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	advec_mom.cpp:186-186,advec_mom.cpp:197-211,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 55.94
CQA cycles if no scalar integer	27.97 - 55.94
CQA cycles if FP arith vectorized	27.97 - 55.94
CQA cycles if fully vectorized	27.97 - 55.94
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	25.50
P9 cycles	25.50
P10 cycles	25.50
P11 cycles	25.50
P12 cycles	5.00
P13 cycles	5.00
P14 cycles	5.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	27.97 - 55.94
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.29
Nb FLOP add-sub	24.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.15 - 8.29
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	3.00
Vectorization ratio all	72.03
Vectorization ratio load	92.31
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	46.67
Vector-efficiency ratio all	95.76
Vector-efficiency ratio load	96.15
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,197-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU loads are used in vector version.
46% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 200 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	2.50	2.50	25.50	25.50	25.50	25.50	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	2.50	2.50	25.50	25.50	25.50	25.50	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-55.94
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Data deps.	2.00
Overall L1	27.97-55.94

Vectorization ratios

INT

all	53%
load	92%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	28%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	72%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	46%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 55.94 cycles. At this rate:

3% of peak load performance is reached (3.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420344

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1D {Z26.D}, P5/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P6/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SUNPKHI Z29.D, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCMLT P14.D, P4/Z, Z26.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P15.D, P4/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z15.D, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
UZP1 P13.S, P14.S, P15.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
SEL Z31.S, P13, Z6.S, Z20.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z30.D, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKHI Z31.D, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MAD Z30.D, P4/M, Z25.D, Z15.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MAD Z31.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
LD1D {Z5.D}, P5/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z2.D}, P6/Z, [X1, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SEL Z14.D, P14, Z24.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z31.D, P14, Z23.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z30, Z15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MLA Z30.D, P4/M, Z25.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MAD Z31.D, P4/M, Z19.D, Z15.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
LD1D {Z28.D}, P5/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MLA Z15.D, P4/M, Z25.D, Z14.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z30.D, P5/M, Z30.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z14.D}, P5/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z4.D, P4/M, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z14.D, P5/M, Z14.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z30.D, P5/M, Z30.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LD1D {Z13.D}, P5/Z, [X6, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCMGT P7.D, P5/Z, Z30.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z3.S, P13, Z7.S, Z20.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z30.D, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z31.D, P4/M, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z15.D}, P7/Z, [X4, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV Z31.D, P5/M, Z31.D, Z13.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z13, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z13.D, P7/M, Z13.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z30, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z5, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z5.D, P4/M, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z1, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z15.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z13, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z13.D, P7/M, Z13.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z15.D, P5, Z31.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z30, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LD1RD {Z31.D}, P4/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUBR Z15.D, P5/M, Z15.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE P14.D, P7/Z, Z14.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z30.D, P7/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
EOR P14.B, P7/Z, P14.B, P7.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FADD Z30.D, P7/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z14.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMINNM Z4.D, P4/M, Z4.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z5.D, P4/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z5.D, P7/Z, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA Z28.D, P5/M, Z5.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
SEL Z1.D, P15, Z23.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z26.D, P5/M, Z26.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MLA Z13.D, P4/M, Z25.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
SEL Z15.D, P15, Z24.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z30.D}, P6/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MAD Z15.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z4.D, P6/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z5.D, P4/M, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z28.D, P6/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z4.D, P6/M, Z4.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MAD Z1.D, P4/M, Z19.D, Z29.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
FCMGT P7.D, P6/Z, Z4.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X6, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z29.D, P4/M, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKHI Z3.D, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FDIV Z29.D, P6/M, Z29.D, Z0.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SEL Z2.D, P6, Z29.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z14.D, P4/M, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z15, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z15.D, P7/M, Z15.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE P15.D, P7/Z, Z28.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z28.D, P7/M, Z28.D, Z4.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z4, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z4.D, P7/M, Z4.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z29, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z29.D, P7/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z29.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z31.D, P7/M, Z31.D, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUBR Z2.D, P6/M, Z2.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMINNM Z5.D, P4/M, Z5.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z15, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z15.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
MOVPRFX Z31, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMINNM Z31.D, P4/M, Z31.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z31.D, P7/Z, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA Z30.D, P6/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL Z27.D, P6/M, Z27.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ST1D {Z26.D}, P5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z27.D}, P6, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
WHILELO P6.D, X0, X8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
INCW Z21.S, ALL	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
WHILELO P5.D, X0, X2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
B.NE 420344 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,197-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU loads are used in vector version.
46% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 200 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	2.50	2.50	25.50	25.50	25.50	25.50	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	2.50	2.50	25.50	25.50	25.50	25.50	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-55.94
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Data deps.	2.00
Overall L1	27.97-55.94

Vectorization ratios

INT

all	53%
load	92%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	28%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	72%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	46%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 55.94 cycles. At this rate:

3% of peak load performance is reached (3.58 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420344

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1D {Z26.D}, P5/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z27.D}, P6/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SUNPKHI Z29.D, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCMLT P14.D, P4/Z, Z26.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P15.D, P4/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z15.D, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
UZP1 P13.S, P14.S, P15.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
SEL Z31.S, P13, Z6.S, Z20.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z30.D, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKHI Z31.D, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MAD Z30.D, P4/M, Z25.D, Z15.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MAD Z31.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
LD1D {Z5.D}, P5/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z2.D}, P6/Z, [X1, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SEL Z14.D, P14, Z24.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z31.D, P14, Z23.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z30, Z15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MLA Z30.D, P4/M, Z25.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MAD Z31.D, P4/M, Z19.D, Z15.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
LD1D {Z28.D}, P5/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MLA Z15.D, P4/M, Z25.D, Z14.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z30.D, P5/M, Z30.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z14.D}, P5/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z4.D, P4/M, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z14.D, P5/M, Z14.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z30.D, P5/M, Z30.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LD1D {Z13.D}, P5/Z, [X6, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCMGT P7.D, P5/Z, Z30.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z3.S, P13, Z7.S, Z20.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z30.D, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z31.D, P4/M, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z15.D}, P7/Z, [X4, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV Z31.D, P5/M, Z31.D, Z13.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z13, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z13.D, P7/M, Z13.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z30, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z5, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z5.D, P4/M, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z1, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z15.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z13, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z13.D, P7/M, Z13.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z15.D, P5, Z31.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z30, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LD1RD {Z31.D}, P4/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUBR Z15.D, P5/M, Z15.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE P14.D, P7/Z, Z14.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z30.D, P7/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
EOR P14.B, P7/Z, P14.B, P7.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FADD Z30.D, P7/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z14.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMINNM Z4.D, P4/M, Z4.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z5.D, P4/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z5.D, P7/Z, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA Z28.D, P5/M, Z5.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
SEL Z1.D, P15, Z23.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z26.D, P5/M, Z26.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MLA Z13.D, P4/M, Z25.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
SEL Z15.D, P15, Z24.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z30.D}, P6/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MAD Z15.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z4.D, P6/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z5.D, P4/M, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z28.D, P6/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z4.D, P6/M, Z4.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MAD Z1.D, P4/M, Z19.D, Z29.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	5	1	vect (100.0%)
FCMGT P7.D, P6/Z, Z4.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z0.D}, P6/Z, [X6, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z29.D, P4/M, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKHI Z3.D, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FDIV Z29.D, P6/M, Z29.D, Z0.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SEL Z2.D, P6, Z29.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z14.D, P4/M, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z15, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z15.D, P7/M, Z15.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE P15.D, P7/Z, Z28.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z28.D, P7/M, Z28.D, Z4.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z4, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z4.D, P7/M, Z4.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z29, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z29.D, P7/M, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z29.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z31.D, P7/M, Z31.D, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUBR Z2.D, P6/M, Z2.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMINNM Z5.D, P4/M, Z5.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z15, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z15.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
MOVPRFX Z31, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMINNM Z31.D, P4/M, Z31.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z31.D, P7/Z, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA Z30.D, P6/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL Z27.D, P6/M, Z27.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ST1D {Z26.D}, P5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z27.D}, P6, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
WHILELO P6.D, X0, X8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
INCW Z21.S, ALL	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
WHILELO P5.D, X0, X2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
B.NE 420344 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code