OV - exec - Loop 311

	Loop Id: 311	Module: exec	Source: context.h:69-69 [...]	Coverage: 3.88%

0x41ff90 LD1D	{Z21.D}, P4/Z, [X7, X0,LSL #3]    [3]

0x41ff94 MOVPRFX	Z19, Z25

0x41ff98 ADD	Z19.S, Z19.S, #1

0x41ff9c FCMLT	P15.D, P3/Z, Z21.D, #0

0x41ffa0 SUNPKLO	Z23.D, Z25

0x41ffa4 SUNPKLO	Z18.D, Z19

0x41ffa8 SEL	Z7.D, P15, Z18.D, Z23.D

0x41ffac SEL	Z18.D, P15, Z23.D, Z18.D

0x41ffb0 LD1D	{Z15.D}, P4/Z, [X1, Z7.D,LSL #3]    [7]

0x41ffb4 LD1D	{Z20.D}, P5/Z, [X10, X0,LSL #3]    [5]

0x41ffb8 LD1D	{Z3.D}, P4/Z, [X4, Z7.D,LSL #3]    [9]

0x41ffbc FCMLT	P14.D, P3/Z, Z20.D, #0

0x41ffc0 LD1D	{Z7.D}, P4/Z, [X1, Z18.D,LSL #3]    [7]

0x41ffc4 UZP1	P7.S, P15.S, P14.S

0x41ffc8 FSUB	Z7.D, P4/M, Z7.D, Z15.D

0x41ffcc SUNPKHI	Z22.D, Z25

0x41ffd0 SUNPKHI	Z17.D, Z19

0x41ffd4 MOVPRFX	Z16, Z25

0x41ffd8 SUB	Z16.S, Z16.S, #1

0x41ffdc SEL	Z6.D, P14, Z17.D, Z22.D

0x41ffe0 MOVPRFX	Z16.S, P7/M, Z25.S

0x41ffe4 ADD	Z16.S, P7/M, Z16.S, Z31.S

0x41ffe8 SEL	Z17.D, P14, Z22.D, Z17.D

0x41ffec SUNPKLO	Z13.D, Z16

0x41fff0 SUNPKHI	Z16.D, Z16

0x41fff4 LD1D	{Z12.D}, P4/Z, [X1, Z13.D,LSL #3]    [7]

0x41fff8 MOVPRFX	Z23, Z15

0x41fffc FSUB	Z23.D, P4/M, Z23.D, Z12.D

0x420000 MOVPRFX	Z18, Z23

0x420004 FMUL	Z18.D, P4/M, Z18.D, Z7.D

0x420008 LD1D	{Z14.D}, P5/Z, [X1, Z6.D,LSL #3]    [7]

0x42000c FCMGT	P6.D, P4/Z, Z18.D, #0

0x420010 LD1D	{Z24.D}, P5/Z, [X1, Z16.D,LSL #3]    [7]

0x420014 LD1D	{Z2.D}, P5/Z, [X4, Z6.D,LSL #3]    [9]

0x420018 MOVPRFX	Z22, Z14

0x42001c FSUB	Z22.D, P5/M, Z22.D, Z24.D

0x420020 LD1D	{Z6.D}, P5/Z, [X1, Z17.D,LSL #3]    [7]

0x420024 MOVPRFX	Z5, Z21

0x420028 FABS	Z5.D, P3/M, Z21.D

0x42002c FSUB	Z6.D, P5/M, Z6.D, Z14.D

0x420030 FDIV	Z5.D, P4/M, Z5.D, Z3.D

0x420034 MOVPRFX	Z17, Z22

0x420038 FMUL	Z17.D, P5/M, Z17.D, Z6.D

0x42003c EOR	P7.B, P3/Z, P7.B, P3.B

0x420040 MOVPRFX	Z18, Z5

0x420044 FADD	Z18.D, P6/M, Z18.D, #1

0x420048 MOVPRFX	Z16, Z27

0x42004c FSUB	Z16.D, P6/M, Z16.D, Z5.D

0x420050 MOVPRFX	Z19.S, P7/M, Z25.S

0x420054 ADD	Z19.S, P7/M, Z19.S, Z30.S

0x420058 FABS	Z23.D, P3/M, Z23.D

0x42005c FCMGT	P7.D, P5/Z, Z17.D, #0

0x420060 FCMLE	P14.D, P6/Z, Z7.D, #0

0x420064 MOVPRFX	Z3, Z7

0x420068 FABS	Z3.D, P3/M, Z7.D

0x42006c MOVPRFX	Z4, Z20

0x420070 FABS	Z4.D, P3/M, Z20.D

0x420074 MOVPRFX	Z7, Z3

0x420078 FMUL	Z7.D, P6/M, Z7.D, Z16.D

0x42007c FDIV	Z4.D, P5/M, Z4.D, Z2.D

0x420080 MOVPRFX	Z16, Z23

0x420084 FMUL	Z16.D, P6/M, Z16.D, Z18.D

0x420088 MOVPRFX	Z24, Z27

0x42008c FSUB	Z24.D, P7/M, Z24.D, Z4.D

0x420090 SUNPKLO	Z18.D, Z19

0x420094 MOVPRFX	Z17, Z4

0x420098 FADD	Z17.D, P7/M, Z17.D, #1

0x42009c LD1D	{Z1.D}, P4/Z, [X8, X0,LSL #3]    [4]

0x4200a0 LD1D	{Z0.D}, P5/Z, [X11, X0,LSL #3]    [6]

0x4200a4 FABS	Z22.D, P3/M, Z22.D

0x4200a8 FCMLE	P15.D, P7/Z, Z6.D, #0

0x4200ac MOVPRFX	Z2, Z6

0x4200b0 FABS	Z2.D, P3/M, Z6.D

0x4200b4 FDIV	Z7.D, P6/M, Z7.D, Z1.D

0x4200b8 MOVPRFX	Z6, Z2

0x4200bc FMUL	Z6.D, P7/M, Z6.D, Z24.D

0x4200c0 SUNPKHI	Z19.D, Z19

0x4200c4 MOVPRFX	Z24, Z22

0x4200c8 FMUL	Z24.D, P7/M, Z24.D, Z17.D

0x4200cc FDIV	Z6.D, P7/M, Z6.D, Z0.D

0x4200d0 LD1D	{Z17.D}, P6/Z, [X5, Z18.D,LSL #3]    [1]

0x4200d4 LD1D	{Z18.D}, P7/Z, [X5, Z19.D,LSL #3]    [1]

0x4200d8 FDIV	Z16.D, P6/M, Z16.D, Z17.D

0x4200dc FDIV	Z24.D, P7/M, Z24.D, Z18.D

0x4200e0 FADD	Z7.D, P6/M, Z7.D, Z16.D

0x4200e4 FADD	Z6.D, P7/M, Z6.D, Z24.D

0x4200e8 FMUL	Z1.D, P6/M, Z1.D, Z7.D

0x4200ec FMUL	Z0.D, P7/M, Z0.D, Z6.D

0x4200f0 SEL	Z7.D, P4, Z5.D, Z29.D

0x4200f4 EOR	P14.B, P6/Z, P14.B, P6.B

0x4200f8 FSUBR	Z7.D, P4/M, Z7.D, #1

0x4200fc SEL	Z6.D, P5, Z4.D, Z29.D

0x420100 EOR	P15.B, P7/Z, P15.B, P7.B

0x420104 FSUBR	Z6.D, P5/M, Z6.D, #1

0x420108 MOVPRFX	Z13, Z28

0x42010c FCPY	Z13.D, P14/M, #1.0000000

0x420110 FDIV	Z1.D, P6/M, Z1.D, Z26.D

0x420114 FDIV	Z0.D, P7/M, Z0.D, Z26.D

0x420118 FMINNM	Z1.D, P3/M, Z1.D, Z23.D

0x42011c FMINNM	Z0.D, P3/M, Z0.D, Z22.D

0x420120 FMINNM	Z1.D, P3/M, Z1.D, Z3.D

0x420124 FMINNM	Z0.D, P3/M, Z0.D, Z2.D

0x420128 MOVPRFX	Z1.D, P6/Z, Z1.D

0x42012c FMUL	Z1.D, P6/M, Z1.D, Z13.D

0x420130 MOVPRFX	Z12, Z28

0x420134 FCPY	Z12.D, P15/M, #1.0000000

0x420138 FMLA	Z15.D, P4/M, Z1.D, Z7.D

0x42013c MOVPRFX	Z0.D, P7/Z, Z0.D

0x420140 FMUL	Z0.D, P7/M, Z0.D, Z12.D

0x420144 FMUL	Z21.D, P4/M, Z21.D, Z15.D

0x420148 FMLA	Z14.D, P5/M, Z0.D, Z6.D

0x42014c FMUL	Z20.D, P5/M, Z20.D, Z14.D

0x420150 ST1D	{Z21.D}, P4, [X3, X0,LSL #3]    [8]

0x420154 ST1D	{Z20.D}, P5, [X6, X0,LSL #3]    [2]

0x420158 ADD	X0, X0, X13

0x42015c WHILELO	P5.D, X0, X9

0x420160 INCW	Z25.S, ALL

0x420164 WHILELO	P4.D, X0, X2

0x420168 B.NE	41ff90

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 114 - 139

--------------------------------------------------------------------------------

114:           if (node_flux(i, j) < 0.0) {

[...]

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.92+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15 - 2.31
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source	advec_mom.cpp:114-114,advec_mom.cpp:120-139,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 55.94
CQA cycles if no scalar integer	27.97 - 55.94
CQA cycles if FP arith vectorized	27.97 - 55.94
CQA cycles if fully vectorized	27.97 - 55.94
Front-end cycles	14.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	24.25
P9 cycles	24.25
P10 cycles	24.25
P11 cycles	24.25
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	27.97 - 55.94
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	119.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.29
Nb FLOP add-sub	24.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.58 - 9.15
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	3.00
Vectorization ratio all	73.04
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	48.33
Vector-efficiency ratio all	95.33
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.04

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15 - 2.31
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source	advec_mom.cpp:114-114,advec_mom.cpp:120-139,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 55.94
CQA cycles if no scalar integer	27.97 - 55.94
CQA cycles if FP arith vectorized	27.97 - 55.94
CQA cycles if fully vectorized	27.97 - 55.94
Front-end cycles	14.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	24.25
P9 cycles	24.25
P10 cycles	24.25
P11 cycles	24.25
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	27.97 - 55.94
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	119.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.29
Nb FLOP add-sub	24.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.58 - 9.15
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	3.00
Vectorization ratio all	73.04
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	48.33
Vector-efficiency ratio all	95.33
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.04

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114,120-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	119
loop length	476
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	3.00	3.00	24.25	24.25	24.25	24.25	5.33	5.33	5.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	3.00	3.00	24.25	24.25	24.25	24.25	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-55.94
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.88
Data deps.	2.00
Overall L1	27.97-55.94

Vectorization ratios

INT

all	53%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	73%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	48%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 55.94 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ff90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P4/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z19, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
ADD Z19.S, Z19.S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLT P15.D, P3/Z, Z21.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z23.D, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SEL Z7.D, P15, Z18.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z18.D, P15, Z23.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z15.D}, P4/Z, [X1, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P5/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P4/Z, [X4, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCMLT P14.D, P3/Z, Z20.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z7.D}, P4/Z, [X1, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
UZP1 P7.S, P15.S, P14.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
FSUB Z7.D, P4/M, Z7.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKHI Z22.D, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKHI Z17.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z16, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUB Z16.S, Z16.S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z6.D, P14, Z17.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z16.S, P7/M, Z25.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD Z16.S, P7/M, Z16.S, Z31.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z17.D, P14, Z22.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z13.D, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKHI Z16.D, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
LD1D {Z12.D}, P4/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z23, Z15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z23.D, P4/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z18, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z18.D, P4/M, Z18.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LD1D {Z14.D}, P5/Z, [X1, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCMGT P6.D, P4/Z, Z18.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z24.D}, P5/Z, [X1, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z2.D}, P5/Z, [X4, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z22, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z22.D, P5/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z6.D}, P5/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z5, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z5.D, P3/M, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z6.D, P5/M, Z6.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV Z5.D, P4/M, Z5.D, Z3.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z17, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z17.D, P5/M, Z17.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
EOR P7.B, P3/Z, P7.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z18.D, P6/M, Z18.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z16, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z16.D, P6/M, Z16.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z19.S, P7/M, Z25.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD Z19.S, P7/M, Z19.S, Z30.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABS Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGT P7.D, P5/Z, Z17.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLE P14.D, P6/Z, Z7.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z3, Z7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z3.D, P3/M, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z4, Z20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z4.D, P3/M, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z7, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z4.D, P5/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z16, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z16.D, P6/M, Z16.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z24, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z24.D, P7/M, Z24.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z17, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z17.D, P7/M, Z17.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z1.D}, P4/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z0.D}, P5/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FABS Z22.D, P3/M, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE P15.D, P7/Z, Z6.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z2.D, P3/M, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV Z7.D, P6/M, Z7.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z6, Z2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
SUNPKHI Z19.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z24.D, P7/M, Z24.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z6.D, P7/M, Z6.D, Z0.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X5, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X5, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV Z16.D, P6/M, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z24.D, P7/M, Z24.D, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
SEL Z7.D, P4, Z5.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P14.B, P6/Z, P14.B, P6.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FSUBR Z7.D, P4/M, Z7.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z6.D, P5, Z4.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FSUBR Z6.D, P5/M, Z6.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z13.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
FDIV Z1.D, P6/M, Z1.D, Z26.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z26.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z1.D, P6/Z, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z12, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z12.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
FMLA Z15.D, P4/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
MOVPRFX Z0.D, P7/Z, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z21.D, P4/M, Z21.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA Z14.D, P5/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL Z20.D, P5/M, Z20.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ST1D {Z21.D}, P4, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z20.D}, P5, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
WHILELO P5.D, X0, X9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
INCW Z25.S, ALL	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
WHILELO P4.D, X0, X2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
B.NE 41ff90 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114,120-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	119
loop length	476
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	3.00	3.00	24.25	24.25	24.25	24.25	5.33	5.33	5.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	3.00	3.00	24.25	24.25	24.25	24.25	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-55.94
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.88
Data deps.	2.00
Overall L1	27.97-55.94

Vectorization ratios

INT

all	53%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	73%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	48%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 55.94 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ff90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P4/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z19, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
ADD Z19.S, Z19.S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLT P15.D, P3/Z, Z21.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z23.D, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SEL Z7.D, P15, Z18.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z18.D, P15, Z23.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z15.D}, P4/Z, [X1, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z20.D}, P5/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P4/Z, [X4, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCMLT P14.D, P3/Z, Z20.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z7.D}, P4/Z, [X1, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
UZP1 P7.S, P15.S, P14.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
FSUB Z7.D, P4/M, Z7.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKHI Z22.D, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKHI Z17.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z16, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUB Z16.S, Z16.S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z6.D, P14, Z17.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z16.S, P7/M, Z25.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD Z16.S, P7/M, Z16.S, Z31.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z17.D, P14, Z22.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z13.D, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
SUNPKHI Z16.D, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
LD1D {Z12.D}, P4/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z23, Z15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z23.D, P4/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z18, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z18.D, P4/M, Z18.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LD1D {Z14.D}, P5/Z, [X1, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCMGT P6.D, P4/Z, Z18.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z24.D}, P5/Z, [X1, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z2.D}, P5/Z, [X4, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z22, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z22.D, P5/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z6.D}, P5/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVPRFX Z5, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z5.D, P3/M, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z6.D, P5/M, Z6.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV Z5.D, P4/M, Z5.D, Z3.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z17, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z17.D, P5/M, Z17.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
EOR P7.B, P3/Z, P7.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z18.D, P6/M, Z18.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z16, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z16.D, P6/M, Z16.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z19.S, P7/M, Z25.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD Z19.S, P7/M, Z19.S, Z30.S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FABS Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGT P7.D, P5/Z, Z17.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMLE P14.D, P6/Z, Z7.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z3, Z7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z3.D, P3/M, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z4, Z20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z4.D, P3/M, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z7, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z4.D, P5/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z16, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z16.D, P6/M, Z16.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z24, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FSUB Z24.D, P7/M, Z24.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z17, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD Z17.D, P7/M, Z17.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z1.D}, P4/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z0.D}, P5/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FABS Z22.D, P3/M, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMLE P15.D, P7/Z, Z6.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FABS Z2.D, P3/M, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FDIV Z7.D, P6/M, Z7.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z6, Z2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
SUNPKHI Z19.D, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FMUL Z24.D, P7/M, Z24.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV Z6.D, P7/M, Z6.D, Z0.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X5, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X5, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV Z16.D, P6/M, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z24.D, P7/M, Z24.D, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
SEL Z7.D, P4, Z5.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P14.B, P6/Z, P14.B, P6.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FSUBR Z7.D, P4/M, Z7.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SEL Z6.D, P5, Z4.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FSUBR Z6.D, P5/M, Z6.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z13.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
FDIV Z1.D, P6/M, Z1.D, Z26.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z26.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z1.D, P6/Z, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z12, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FCPY Z12.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (6.3%)
FMLA Z15.D, P4/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
MOVPRFX Z0.D, P7/Z, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z21.D, P4/M, Z21.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA Z14.D, P5/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL Z20.D, P5/M, Z20.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ST1D {Z21.D}, P4, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z20.D}, P5, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
WHILELO P5.D, X0, X9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
INCW Z25.S, ALL	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
WHILELO P4.D, X0, X2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	N/A
B.NE 41ff90 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code