OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 4.04% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

[...]

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4201f0 STP	X29, X30, [SP, #912]!

0x4201f4 ADD	X29, SP, #0

0x4201f8 STP	X23, X24, [SP, #48]

0x4201fc ORR	X23, XZR, X0

0x420200 STP	X19, X20, [SP, #16]

0x420204 STP	X25, X26, [SP, #64]

0x420208 LDP	W26, W19, [X23, #48]

0x42020c LDP	W20, W0, [X0, #40]

0x420210 ADD	W19, W19, #3

0x420214 CMP	W26, W19

0x420218 B.GE	42058c

0x42021c ADD	W20, W20, #1

0x420220 STP	X21, X22, [SP, #32]

0x420224 ADD	W22, W0, #3

0x420228 SUB	W25, W19, W26

0x42022c CMP	W20, W22

0x420230 B.GE	4205a0

0x420234 SUB	W21, W22, W20

0x420238 BL	403aa0

0x42023c MADD	W25, W25, W21, WZR

0x420240 ORR	W24, WZR, W0

0x420244 BL	403980

0x420248 ORR	W1, WZR, W0

0x42024c UDIV	W2, W25, W24

0x420250 MSUB	W0, W2, W24, W25

0x420254 CMP	W1, W0

0x420258 B.CC	4205b8

  (315) 0x42025c MADD	W1, W2, W1, W0

  (315) 0x420260 ADD	W17, W2, W1

  (315) 0x420264 CMP	W1, W17

  (315) 0x420268 B.CS	4205a0

(317) 0x42026c UDIV	W0, W1, W21

(317) 0x420270 STP	D13, D14, [SP, #80]

(317) 0x420274 CNTW	X11, ALL

(317) 0x420278 PTRUE	P4.B, ALL

(317) 0x42027c FDUP	Z16.D, #112

(317) 0x420280 LDR	X18, [X23, #32]

(317) 0x420284 FDUP	Z17.D, #240

(317) 0x420288 FDUP	Z22.D, #0

(317) 0x42028c FDUP	Z18.D, #24

(317) 0x420290 STR	D15, [SP, #96]

(317) 0x420294 LDP	X15, X16, [X23]

(317) 0x420298 LDP	X13, X14, [X23, #16]

(317) 0x42029c MSUB	W3, W0, W21, W1

(317) 0x4202a0 ADD	W9, W0, W26

(317) 0x4202a4 SBFM	X9, X9, #0, #31

(317) 0x4202a8 ADD	W4, W9, #1

(317) 0x4202ac ADD	W3, W3, W20

(317) 0x4202b0 SUB	W0, W22, W3

(317) 0x4202b4 CMP	W2, W0

(317) 0x4202b8 CSEL	X2, X2, X0, #9

(317) 0x4202bc ADD	W12, W1, W2

(317) 0x4202c0 CMP	W1, W12

(317) 0x4202c4 B.CS	420560

  (318) 0x4202c8 LDR	X7, [X16]

  (318) 0x4202cc SBFM	X1, X3, #0, #31

  (318) 0x4202d0 INDEX	Z21.S, W3, #1

  (318) 0x4202d4 ADD	W6, W9, #2

  (318) 0x4202d8 DUP	Z6.S, W6

  (318) 0x4202dc SUB	W5, W9, #1

  (318) 0x4202e0 DUP	Z20.S, W5

  (318) 0x4202e4 DUP	Z7.S, W4

  (318) 0x4202e8 ADD	X22, X9, #1

  (318) 0x4202ec DUP	Z24.D, X9

  (318) 0x4202f0 LDR	X3, [X14]

  (318) 0x4202f4 MOVZ	X0, #0

  (318) 0x4202f8 ORR	X8, XZR, X2

  (318) 0x4202fc WHILELO	P5.D, XZR, X2

  (318) 0x420300 UQDECD	X8, ALL

  (318) 0x420304 DUP	Z23.D, X22

  (318) 0x420308 WHILELO	P6.D, XZR, X8

  (318) 0x42030c LD1RD	{Z19.D}, P4/Z, [X13]

  (318) 0x420310 LD1RD	{Z25.D}, P4/Z, [X15]

  (318) 0x420314 LDR	X6, [X16, #16]

  (318) 0x420318 MADD	X7, X9, X7, X1

  (318) 0x42031c LDR	X5, [X14, #16]

  (318) 0x420320 MADD	X3, X9, X3, X1

  (318) 0x420324 LDR	X4, [X18, #8]

  (318) 0x420328 ADD	X7, X6, X7,LSL #3

  (318) 0x42032c LDR	X1, [X15, #16]

  (318) 0x420330 ADD	X3, X5, X3,LSL #3

  (318) 0x420334 ADDVL	X10, X7, #1

  (318) 0x420338 LDR	X6, [X13, #16]

  (318) 0x42033c ADD	X9, X4, X9,LSL #3

  (318) 0x420340 ADDVL	X5, X3, #1

    (316) 0x420344 LD1D	{Z26.D}, P5/Z, [X7, X0,LSL #3]

    (316) 0x420348 LD1D	{Z27.D}, P6/Z, [X10, X0,LSL #3]

    (316) 0x42034c SUNPKHI	Z29.D, Z21

    (316) 0x420350 FCMLT	P14.D, P4/Z, Z26.D, #0

    (316) 0x420354 FCMLT	P15.D, P4/Z, Z27.D, #0

    (316) 0x420358 SUNPKLO	Z15.D, Z21

    (316) 0x42035c UZP1	P13.S, P14.S, P15.S

    (316) 0x420360 SEL	Z31.S, P13, Z6.S, Z20.S

    (316) 0x420364 SUNPKLO	Z30.D, Z31

    (316) 0x420368 SUNPKHI	Z31.D, Z31

    (316) 0x42036c MAD	Z30.D, P4/M, Z25.D, Z15.D

    (316) 0x420370 MAD	Z31.D, P4/M, Z25.D, Z29.D

    (316) 0x420374 LD1D	{Z5.D}, P5/Z, [X1, Z30.D,LSL #3]

    (316) 0x420378 LD1D	{Z2.D}, P6/Z, [X1, Z31.D,LSL #3]

    (316) 0x42037c SEL	Z14.D, P14, Z24.D, Z23.D

    (316) 0x420380 SEL	Z31.D, P14, Z23.D, Z24.D

    (316) 0x420384 MOVPRFX	Z30, Z15

    (316) 0x420388 MLA	Z30.D, P4/M, Z25.D, Z31.D

    (316) 0x42038c MAD	Z31.D, P4/M, Z19.D, Z15.D

    (316) 0x420390 LD1D	{Z28.D}, P5/Z, [X1, Z30.D,LSL #3]

    (316) 0x420394 MLA	Z15.D, P4/M, Z25.D, Z14.D

    (316) 0x420398 MOVPRFX	Z30, Z28

    (316) 0x42039c FSUB	Z30.D, P5/M, Z30.D, Z5.D

    (316) 0x4203a0 LD1D	{Z14.D}, P5/Z, [X1, Z15.D,LSL #3]

    (316) 0x4203a4 MOVPRFX	Z4, Z30

    (316) 0x4203a8 FABS	Z4.D, P4/M, Z30.D

    (316) 0x4203ac FSUB	Z14.D, P5/M, Z14.D, Z28.D

    (316) 0x4203b0 FMUL	Z30.D, P5/M, Z30.D, Z14.D

    (316) 0x4203b4 LD1D	{Z13.D}, P5/Z, [X6, Z31.D,LSL #3]

    (316) 0x4203b8 FCMGT	P7.D, P5/Z, Z30.D, #0

    (316) 0x4203bc SEL	Z3.S, P13, Z7.S, Z20.S

    (316) 0x4203c0 SUNPKLO	Z30.D, Z3

    (316) 0x4203c4 MOVPRFX	Z31, Z26

    (316) 0x4203c8 FABS	Z31.D, P4/M, Z26.D

    (316) 0x4203cc LD1D	{Z15.D}, P7/Z, [X4, Z30.D,LSL #3]

    (316) 0x4203d0 FDIV	Z31.D, P5/M, Z31.D, Z13.D

    (316) 0x4203d4 MOVPRFX	Z13, Z31

    (316) 0x4203d8 FADD	Z13.D, P7/M, Z13.D, #1

    (316) 0x4203dc MOVPRFX	Z30, Z4

    (316) 0x4203e0 FMUL	Z30.D, P7/M, Z30.D, Z13.D

    (316) 0x4203e4 MOVPRFX	Z5, Z14

    (316) 0x4203e8 FABS	Z5.D, P4/M, Z14.D

    (316) 0x4203ec MOVPRFX	Z1, Z30

    (316) 0x4203f0 FDIV	Z1.D, P7/M, Z1.D, Z15.D

    (316) 0x4203f4 MOVPRFX	Z13, Z22

    (316) 0x4203f8 FSUB	Z13.D, P7/M, Z13.D, Z31.D

    (316) 0x4203fc SEL	Z15.D, P5, Z31.D, Z16.D

    (316) 0x420400 MOVPRFX	Z30, Z5

    (316) 0x420404 FMUL	Z30.D, P7/M, Z30.D, Z13.D

    (316) 0x420408 LD1RD	{Z31.D}, P4/Z, [X9]

    (316) 0x42040c FSUBR	Z15.D, P5/M, Z15.D, #1

    (316) 0x420410 FCMLE	P14.D, P7/Z, Z14.D, #0

    (316) 0x420414 FDIV	Z30.D, P7/M, Z30.D, Z31.D

    (316) 0x420418 EOR	P14.B, P7/Z, P14.B, P7.B

    (316) 0x42041c FADD	Z30.D, P7/M, Z30.D, Z1.D

    (316) 0x420420 MOVPRFX	Z14, Z17

    (316) 0x420424 FCPY	Z14.D, P14/M, #1.0000000

    (316) 0x420428 MOVPRFX	Z0, Z31

    (316) 0x42042c FMUL	Z0.D, P7/M, Z0.D, Z30.D

    (316) 0x420430 FDIV	Z0.D, P7/M, Z0.D, Z18.D

    (316) 0x420434 FMINNM	Z4.D, P4/M, Z4.D, Z0.D

    (316) 0x420438 FMINNM	Z5.D, P4/M, Z5.D, Z4.D

    (316) 0x42043c MOVPRFX	Z5.D, P7/Z, Z5.D

    (316) 0x420440 FMUL	Z5.D, P7/M, Z5.D, Z14.D

    (316) 0x420444 FMLA	Z28.D, P5/M, Z5.D, Z15.D

    (316) 0x420448 SEL	Z1.D, P15, Z23.D, Z24.D

    (316) 0x42044c FMUL	Z26.D, P5/M, Z26.D, Z28.D

    (316) 0x420450 MOVPRFX	Z13, Z29

    (316) 0x420454 MLA	Z13.D, P4/M, Z25.D, Z1.D

    (316) 0x420458 SEL	Z15.D, P15, Z24.D, Z23.D

    (316) 0x42045c LD1D	{Z30.D}, P6/Z, [X1, Z13.D,LSL #3]

    (316) 0x420460 MAD	Z15.D, P4/M, Z25.D, Z29.D

    (316) 0x420464 MOVPRFX	Z4, Z30

    (316) 0x420468 FSUB	Z4.D, P6/M, Z4.D, Z2.D

    (316) 0x42046c LD1D	{Z28.D}, P6/Z, [X1, Z15.D,LSL #3]

    (316) 0x420470 MOVPRFX	Z5, Z4

    (316) 0x420474 FABS	Z5.D, P4/M, Z4.D

    (316) 0x420478 FSUB	Z28.D, P6/M, Z28.D, Z30.D

    (316) 0x42047c FMUL	Z4.D, P6/M, Z4.D, Z28.D

    (316) 0x420480 MAD	Z1.D, P4/M, Z19.D, Z29.D

    (316) 0x420484 FCMGT	P7.D, P6/Z, Z4.D, #0

    (316) 0x420488 LD1D	{Z0.D}, P6/Z, [X6, Z1.D,LSL #3]

    (316) 0x42048c MOVPRFX	Z29, Z27

    (316) 0x420490 FABS	Z29.D, P4/M, Z27.D

    (316) 0x420494 SUNPKHI	Z3.D, Z3

    (316) 0x420498 FDIV	Z29.D, P6/M, Z29.D, Z0.D

    (316) 0x42049c LD1D	{Z4.D}, P7/Z, [X4, Z3.D,LSL #3]

    (316) 0x4204a0 SEL	Z2.D, P6, Z29.D, Z16.D

    (316) 0x4204a4 MOVPRFX	Z14, Z28

    (316) 0x4204a8 FABS	Z14.D, P4/M, Z28.D

    (316) 0x4204ac MOVPRFX	Z15, Z29

    (316) 0x4204b0 FADD	Z15.D, P7/M, Z15.D, #1

    (316) 0x4204b4 FCMLE	P15.D, P7/Z, Z28.D, #0

    (316) 0x4204b8 MOVPRFX	Z28, Z5

    (316) 0x4204bc FMUL	Z28.D, P7/M, Z28.D, Z15.D

    (316) 0x4204c0 FDIV	Z28.D, P7/M, Z28.D, Z4.D

    (316) 0x4204c4 MOVPRFX	Z4, Z22

    (316) 0x4204c8 FSUB	Z4.D, P7/M, Z4.D, Z29.D

    (316) 0x4204cc MOVPRFX	Z29, Z14

    (316) 0x4204d0 FMUL	Z29.D, P7/M, Z29.D, Z4.D

    (316) 0x4204d4 FDIV	Z29.D, P7/M, Z29.D, Z31.D

    (316) 0x4204d8 FADD	Z29.D, P7/M, Z29.D, Z28.D

    (316) 0x4204dc FMUL	Z31.D, P7/M, Z31.D, Z29.D

    (316) 0x4204e0 FDIV	Z31.D, P7/M, Z31.D, Z18.D

    (316) 0x4204e4 FSUBR	Z2.D, P6/M, Z2.D, #1

    (316) 0x4204e8 EOR	P15.B, P7/Z, P15.B, P7.B

    (316) 0x4204ec FMINNM	Z5.D, P4/M, Z5.D, Z31.D

    (316) 0x4204f0 MOVPRFX	Z15, Z17

    (316) 0x4204f4 FCPY	Z15.D, P15/M, #1.0000000

    (316) 0x4204f8 MOVPRFX	Z31, Z14

    (316) 0x4204fc FMINNM	Z31.D, P4/M, Z31.D, Z5.D

    (316) 0x420500 MOVPRFX	Z31.D, P7/Z, Z31.D

    (316) 0x420504 FMUL	Z31.D, P7/M, Z31.D, Z15.D

    (316) 0x420508 FMLA	Z30.D, P6/M, Z31.D, Z2.D

    (316) 0x42050c FMUL	Z27.D, P6/M, Z27.D, Z30.D

    (316) 0x420510 ST1D	{Z26.D}, P5, [X3, X0,LSL #3]

    (316) 0x420514 ST1D	{Z27.D}, P6, [X5, X0,LSL #3]

    (316) 0x420518 ADD	X0, X0, X11

    (316) 0x42051c WHILELO	P6.D, X0, X8

    (316) 0x420520 INCW	Z21.S, ALL

    (316) 0x420524 WHILELO	P5.D, X0, X2

    (316) 0x420528 B.NE	420344

  (318) 0x42052c ORR	X9, XZR, X22

  (318) 0x420530 CMP	W19, W22

  (318) 0x420534 B.LE	420580

  (318) 0x420538 SUB	W2, W17, W12

  (318) 0x42053c ORR	W0, WZR, W21

  (318) 0x420540 ORR	W1, WZR, W12

  (318) 0x420544 CMP	W2, W0

  (318) 0x420548 CSEL	X2, X2, X0, #9

  (318) 0x42054c ADD	W12, W1, W2

  (318) 0x420550 ORR	W3, WZR, W20

  (318) 0x420554 ADD	W4, W9, #1

  (318) 0x420558 CMP	W1, W12

  (318) 0x42055c B.CC	4202c8

  (319) 0x420560 ADD	X22, X9, #1

  (319) 0x420564 ORR	W12, WZR, W1

  (319) 0x420568 ORR	X9, XZR, X22

  (319) 0x42056c CMP	W19, W22

  (319) 0x420570 B.GT	420538

(317) 0x420574 HINT	#0

(317) 0x420578 HINT	#0

(317) 0x42057c HINT	#0

(317) 0x420580 LDR	D15, [SP, #96]

(317) 0x420584 LDP	X21, X22, [SP, #32]

(317) 0x420588 LDP	D13, D14, [SP, #80]

(317) 0x42058c LDP	X19, X20, [SP, #16]

(317) 0x420590 LDP	X23, X24, [SP, #48]

(317) 0x420594 LDP	X25, X26, [SP, #64]

(317) 0x420598 LDP	X29, X30, [SP], #112

(317) 0x42059c RET

  (315) 0x4205a0 LDP	X21, X22, [SP, #32]

  (315) 0x4205a4 LDP	X19, X20, [SP, #16]

  (315) 0x4205a8 LDP	X23, X24, [SP, #48]

  (315) 0x4205ac LDP	X25, X26, [SP, #64]

  (315) 0x4205b0 LDP	X29, X30, [SP], #112

  (315) 0x4205b4 RET

  (315) 0x4205b8 ADD	W2, W2, #1

  (315) 0x4205bc MOVZ	W0, #0

  (315) 0x4205c0 B	42025c

Coverage (%)	Name	Source Location	Module
►98.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-186,197-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.38
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4201f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X23, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42058c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W25, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4205a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W25, W25, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UDIV W2, W25, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W2, W24, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 4205b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-186,197-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.38
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4201f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W26, W19, [X23, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W26, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42058c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W22, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W25, W19, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4205a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W25, W25, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UDIV W2, W25, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W2, W24, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 4205b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.04	3.12
▼Loop 317 - advec_mom.cpp:180-211 - exec–	0.00	0.00
▼Loop 318 - advec_mom.cpp:182-211 - exec–	0.00	0.01
○Loop 316 - context.h:69-69 - exec	4.04	3.09
○Loop 319 - advec_mom.cpp:182-182 - exec	0.00	0.01
○Loop 315 - advec_mom.cpp:180-182 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code