OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 3.89% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

[...]

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41fe40 STP	X29, X30, [SP, #912]!

0x41fe44 ADD	X29, SP, #0

0x41fe48 STP	X19, X20, [SP, #16]

0x41fe4c STP	X21, X22, [SP, #32]

0x41fe50 ORR	X22, XZR, X0

0x41fe54 STP	X25, X26, [SP, #64]

0x41fe58 LDP	W25, W19, [X0, #48]

0x41fe5c LDP	W20, W0, [X0, #40]

0x41fe60 ADD	W25, W25, #1

0x41fe64 ADD	W19, W19, #3

0x41fe68 CMP	W25, W19

0x41fe6c B.GE	4201b8

0x41fe70 STP	X23, X24, [SP, #48]

0x41fe74 ADD	W23, W0, #3

0x41fe78 SUB	W26, W19, W25

0x41fe7c CMP	W20, W23

0x41fe80 B.GE	4201cc

0x41fe84 SUB	W21, W23, W20

0x41fe88 BL	403aa0

0x41fe8c MADD	W26, W26, W21, WZR

0x41fe90 ORR	W24, WZR, W0

0x41fe94 BL	403980

0x41fe98 ORR	W1, WZR, W0

0x41fe9c UDIV	W2, W26, W24

0x41fea0 MSUB	W0, W2, W24, W26

0x41fea4 CMP	W1, W0

0x41fea8 B.CC	4201e4

  (310) 0x41feac MADD	W1, W2, W1, W0

  (310) 0x41feb0 ADD	W30, W2, W1

  (310) 0x41feb4 CMP	W1, W30

  (310) 0x41feb8 B.CS	4201cc

(312) 0x41febc UDIV	W0, W1, W21

(312) 0x41fec0 STP	D12, D13, [SP, #80]

(312) 0x41fec4 CNTW	X13, ALL

(312) 0x41fec8 PTRUE	P3.B, ALL

(312) 0x41fecc DUP	Z31.S, #2

(312) 0x41fed0 STP	D14, D15, [SP, #96]

(312) 0x41fed4 DUP	Z30.B, #255

(312) 0x41fed8 FDUP	Z29.D, #112

(312) 0x41fedc FDUP	Z28.D, #240

(312) 0x41fee0 FDUP	Z27.D, #0

(312) 0x41fee4 LDP	X17, X18, [X22]

(312) 0x41fee8 FDUP	Z26.D, #24

(312) 0x41feec LDP	X15, X16, [X22, #16]

(312) 0x41fef0 LDR	X22, [X22, #32]

(312) 0x41fef4 MSUB	W3, W0, W21, W1

(312) 0x41fef8 ADD	W0, W0, W25

(312) 0x41fefc SBFM	X12, X0, #0, #31

(312) 0x41ff00 ADD	W3, W3, W20

(312) 0x41ff04 SUB	W0, W23, W3

(312) 0x41ff08 CMP	W2, W0

(312) 0x41ff0c CSEL	X2, X2, X0, #9

(312) 0x41ff10 ADD	W14, W1, W2

(312) 0x41ff14 CMP	W1, W14

(312) 0x41ff18 B.CS	42019c

(312) 0x41ff1c HINT	#0

  (313) 0x41ff20 LDR	X7, [X18]

  (313) 0x41ff24 SBFM	X8, X3, #0, #31

  (313) 0x41ff28 INDEX	Z25.S, W3, #1

  (313) 0x41ff2c MOVZ	X0, #0

  (313) 0x41ff30 WHILELO	P4.D, XZR, X2

  (313) 0x41ff34 ORR	X9, XZR, X2

  (313) 0x41ff38 UQDECD	X9, ALL

  (313) 0x41ff3c WHILELO	P5.D, XZR, X9

  (313) 0x41ff40 LDR	X3, [X16]

  (313) 0x41ff44 LDR	X1, [X17]

  (313) 0x41ff48 MADD	X7, X12, X7, X8

  (313) 0x41ff4c LDR	X4, [X15]

  (313) 0x41ff50 MADD	X3, X12, X3, X8

  (313) 0x41ff54 LDR	X5, [X22, #8]

  (313) 0x41ff58 MADD	X1, X12, X1, XZR

  (313) 0x41ff5c LDR	X10, [X16, #16]

  (313) 0x41ff60 MADD	X4, X12, X4, XZR

  (313) 0x41ff64 LDR	X11, [X18, #16]

  (313) 0x41ff68 ADD	X8, X5, X8,LSL #3

  (313) 0x41ff6c LDR	X23, [X17, #16]

  (313) 0x41ff70 ADD	X3, X10, X3,LSL #3

  (313) 0x41ff74 LDR	X6, [X15, #16]

  (313) 0x41ff78 ADD	X7, X11, X7,LSL #3

  (313) 0x41ff7c ADDVL	X11, X8, #1

  (313) 0x41ff80 ADD	X1, X23, X1,LSL #3

  (313) 0x41ff84 ADDVL	X10, X7, #1

  (313) 0x41ff88 ADD	X4, X6, X4,LSL #3

  (313) 0x41ff8c ADDVL	X6, X3, #1

    (311) 0x41ff90 LD1D	{Z21.D}, P4/Z, [X7, X0,LSL #3]

    (311) 0x41ff94 MOVPRFX	Z19, Z25

    (311) 0x41ff98 ADD	Z19.S, Z19.S, #1

    (311) 0x41ff9c FCMLT	P15.D, P3/Z, Z21.D, #0

    (311) 0x41ffa0 SUNPKLO	Z23.D, Z25

    (311) 0x41ffa4 SUNPKLO	Z18.D, Z19

    (311) 0x41ffa8 SEL	Z7.D, P15, Z18.D, Z23.D

    (311) 0x41ffac SEL	Z18.D, P15, Z23.D, Z18.D

    (311) 0x41ffb0 LD1D	{Z15.D}, P4/Z, [X1, Z7.D,LSL #3]

    (311) 0x41ffb4 LD1D	{Z20.D}, P5/Z, [X10, X0,LSL #3]

    (311) 0x41ffb8 LD1D	{Z3.D}, P4/Z, [X4, Z7.D,LSL #3]

    (311) 0x41ffbc FCMLT	P14.D, P3/Z, Z20.D, #0

    (311) 0x41ffc0 LD1D	{Z7.D}, P4/Z, [X1, Z18.D,LSL #3]

    (311) 0x41ffc4 UZP1	P7.S, P15.S, P14.S

    (311) 0x41ffc8 FSUB	Z7.D, P4/M, Z7.D, Z15.D

    (311) 0x41ffcc SUNPKHI	Z22.D, Z25

    (311) 0x41ffd0 SUNPKHI	Z17.D, Z19

    (311) 0x41ffd4 MOVPRFX	Z16, Z25

    (311) 0x41ffd8 SUB	Z16.S, Z16.S, #1

    (311) 0x41ffdc SEL	Z6.D, P14, Z17.D, Z22.D

    (311) 0x41ffe0 MOVPRFX	Z16.S, P7/M, Z25.S

    (311) 0x41ffe4 ADD	Z16.S, P7/M, Z16.S, Z31.S

    (311) 0x41ffe8 SEL	Z17.D, P14, Z22.D, Z17.D

    (311) 0x41ffec SUNPKLO	Z13.D, Z16

    (311) 0x41fff0 SUNPKHI	Z16.D, Z16

    (311) 0x41fff4 LD1D	{Z12.D}, P4/Z, [X1, Z13.D,LSL #3]

    (311) 0x41fff8 MOVPRFX	Z23, Z15

    (311) 0x41fffc FSUB	Z23.D, P4/M, Z23.D, Z12.D

    (311) 0x420000 MOVPRFX	Z18, Z23

    (311) 0x420004 FMUL	Z18.D, P4/M, Z18.D, Z7.D

    (311) 0x420008 LD1D	{Z14.D}, P5/Z, [X1, Z6.D,LSL #3]

    (311) 0x42000c FCMGT	P6.D, P4/Z, Z18.D, #0

    (311) 0x420010 LD1D	{Z24.D}, P5/Z, [X1, Z16.D,LSL #3]

    (311) 0x420014 LD1D	{Z2.D}, P5/Z, [X4, Z6.D,LSL #3]

    (311) 0x420018 MOVPRFX	Z22, Z14

    (311) 0x42001c FSUB	Z22.D, P5/M, Z22.D, Z24.D

    (311) 0x420020 LD1D	{Z6.D}, P5/Z, [X1, Z17.D,LSL #3]

    (311) 0x420024 MOVPRFX	Z5, Z21

    (311) 0x420028 FABS	Z5.D, P3/M, Z21.D

    (311) 0x42002c FSUB	Z6.D, P5/M, Z6.D, Z14.D

    (311) 0x420030 FDIV	Z5.D, P4/M, Z5.D, Z3.D

    (311) 0x420034 MOVPRFX	Z17, Z22

    (311) 0x420038 FMUL	Z17.D, P5/M, Z17.D, Z6.D

    (311) 0x42003c EOR	P7.B, P3/Z, P7.B, P3.B

    (311) 0x420040 MOVPRFX	Z18, Z5

    (311) 0x420044 FADD	Z18.D, P6/M, Z18.D, #1

    (311) 0x420048 MOVPRFX	Z16, Z27

    (311) 0x42004c FSUB	Z16.D, P6/M, Z16.D, Z5.D

    (311) 0x420050 MOVPRFX	Z19.S, P7/M, Z25.S

    (311) 0x420054 ADD	Z19.S, P7/M, Z19.S, Z30.S

    (311) 0x420058 FABS	Z23.D, P3/M, Z23.D

    (311) 0x42005c FCMGT	P7.D, P5/Z, Z17.D, #0

    (311) 0x420060 FCMLE	P14.D, P6/Z, Z7.D, #0

    (311) 0x420064 MOVPRFX	Z3, Z7

    (311) 0x420068 FABS	Z3.D, P3/M, Z7.D

    (311) 0x42006c MOVPRFX	Z4, Z20

    (311) 0x420070 FABS	Z4.D, P3/M, Z20.D

    (311) 0x420074 MOVPRFX	Z7, Z3

    (311) 0x420078 FMUL	Z7.D, P6/M, Z7.D, Z16.D

    (311) 0x42007c FDIV	Z4.D, P5/M, Z4.D, Z2.D

    (311) 0x420080 MOVPRFX	Z16, Z23

    (311) 0x420084 FMUL	Z16.D, P6/M, Z16.D, Z18.D

    (311) 0x420088 MOVPRFX	Z24, Z27

    (311) 0x42008c FSUB	Z24.D, P7/M, Z24.D, Z4.D

    (311) 0x420090 SUNPKLO	Z18.D, Z19

    (311) 0x420094 MOVPRFX	Z17, Z4

    (311) 0x420098 FADD	Z17.D, P7/M, Z17.D, #1

    (311) 0x42009c LD1D	{Z1.D}, P4/Z, [X8, X0,LSL #3]

    (311) 0x4200a0 LD1D	{Z0.D}, P5/Z, [X11, X0,LSL #3]

    (311) 0x4200a4 FABS	Z22.D, P3/M, Z22.D

    (311) 0x4200a8 FCMLE	P15.D, P7/Z, Z6.D, #0

    (311) 0x4200ac MOVPRFX	Z2, Z6

    (311) 0x4200b0 FABS	Z2.D, P3/M, Z6.D

    (311) 0x4200b4 FDIV	Z7.D, P6/M, Z7.D, Z1.D

    (311) 0x4200b8 MOVPRFX	Z6, Z2

    (311) 0x4200bc FMUL	Z6.D, P7/M, Z6.D, Z24.D

    (311) 0x4200c0 SUNPKHI	Z19.D, Z19

    (311) 0x4200c4 MOVPRFX	Z24, Z22

    (311) 0x4200c8 FMUL	Z24.D, P7/M, Z24.D, Z17.D

    (311) 0x4200cc FDIV	Z6.D, P7/M, Z6.D, Z0.D

    (311) 0x4200d0 LD1D	{Z17.D}, P6/Z, [X5, Z18.D,LSL #3]

    (311) 0x4200d4 LD1D	{Z18.D}, P7/Z, [X5, Z19.D,LSL #3]

    (311) 0x4200d8 FDIV	Z16.D, P6/M, Z16.D, Z17.D

    (311) 0x4200dc FDIV	Z24.D, P7/M, Z24.D, Z18.D

    (311) 0x4200e0 FADD	Z7.D, P6/M, Z7.D, Z16.D

    (311) 0x4200e4 FADD	Z6.D, P7/M, Z6.D, Z24.D

    (311) 0x4200e8 FMUL	Z1.D, P6/M, Z1.D, Z7.D

    (311) 0x4200ec FMUL	Z0.D, P7/M, Z0.D, Z6.D

    (311) 0x4200f0 SEL	Z7.D, P4, Z5.D, Z29.D

    (311) 0x4200f4 EOR	P14.B, P6/Z, P14.B, P6.B

    (311) 0x4200f8 FSUBR	Z7.D, P4/M, Z7.D, #1

    (311) 0x4200fc SEL	Z6.D, P5, Z4.D, Z29.D

    (311) 0x420100 EOR	P15.B, P7/Z, P15.B, P7.B

    (311) 0x420104 FSUBR	Z6.D, P5/M, Z6.D, #1

    (311) 0x420108 MOVPRFX	Z13, Z28

    (311) 0x42010c FCPY	Z13.D, P14/M, #1.0000000

    (311) 0x420110 FDIV	Z1.D, P6/M, Z1.D, Z26.D

    (311) 0x420114 FDIV	Z0.D, P7/M, Z0.D, Z26.D

    (311) 0x420118 FMINNM	Z1.D, P3/M, Z1.D, Z23.D

    (311) 0x42011c FMINNM	Z0.D, P3/M, Z0.D, Z22.D

    (311) 0x420120 FMINNM	Z1.D, P3/M, Z1.D, Z3.D

    (311) 0x420124 FMINNM	Z0.D, P3/M, Z0.D, Z2.D

    (311) 0x420128 MOVPRFX	Z1.D, P6/Z, Z1.D

    (311) 0x42012c FMUL	Z1.D, P6/M, Z1.D, Z13.D

    (311) 0x420130 MOVPRFX	Z12, Z28

    (311) 0x420134 FCPY	Z12.D, P15/M, #1.0000000

    (311) 0x420138 FMLA	Z15.D, P4/M, Z1.D, Z7.D

    (311) 0x42013c MOVPRFX	Z0.D, P7/Z, Z0.D

    (311) 0x420140 FMUL	Z0.D, P7/M, Z0.D, Z12.D

    (311) 0x420144 FMUL	Z21.D, P4/M, Z21.D, Z15.D

    (311) 0x420148 FMLA	Z14.D, P5/M, Z0.D, Z6.D

    (311) 0x42014c FMUL	Z20.D, P5/M, Z20.D, Z14.D

    (311) 0x420150 ST1D	{Z21.D}, P4, [X3, X0,LSL #3]

    (311) 0x420154 ST1D	{Z20.D}, P5, [X6, X0,LSL #3]

    (311) 0x420158 ADD	X0, X0, X13

    (311) 0x42015c WHILELO	P5.D, X0, X9

    (311) 0x420160 INCW	Z25.S, ALL

    (311) 0x420164 WHILELO	P4.D, X0, X2

    (311) 0x420168 B.NE	41ff90

  (313) 0x42016c ADD	X12, X12, #1

  (313) 0x420170 CMP	W19, W12

  (313) 0x420174 B.LE	4201ac

  (313) 0x420178 SUB	W2, W30, W14

  (313) 0x42017c ORR	W0, WZR, W21

  (313) 0x420180 ORR	W1, WZR, W14

  (313) 0x420184 CMP	W2, W0

  (313) 0x420188 CSEL	X2, X2, X0, #9

  (313) 0x42018c ADD	W14, W1, W2

  (313) 0x420190 ORR	W3, WZR, W20

  (313) 0x420194 CMP	W1, W14

  (313) 0x420198 B.CC	41ff20

  (314) 0x42019c ADD	X12, X12, #1

  (314) 0x4201a0 ORR	W14, WZR, W1

  (314) 0x4201a4 CMP	W19, W12

  (314) 0x4201a8 B.GT	420178

(312) 0x4201ac LDP	D12, D13, [SP, #80]

(312) 0x4201b0 LDP	X23, X24, [SP, #48]

(312) 0x4201b4 LDP	D14, D15, [SP, #96]

(312) 0x4201b8 LDP	X19, X20, [SP, #16]

(312) 0x4201bc LDP	X21, X22, [SP, #32]

(312) 0x4201c0 LDP	X25, X26, [SP, #64]

(312) 0x4201c4 LDP	X29, X30, [SP], #112

(312) 0x4201c8 RET

  (310) 0x4201cc LDP	X23, X24, [SP, #48]

  (310) 0x4201d0 LDP	X19, X20, [SP, #16]

  (310) 0x4201d4 LDP	X21, X22, [SP, #32]

  (310) 0x4201d8 LDP	X25, X26, [SP, #64]

  (310) 0x4201dc LDP	X29, X30, [SP], #112

  (310) 0x4201e0 RET

  (310) 0x4201e4 ADD	W2, W2, #1

  (310) 0x4201e8 MOVZ	W0, #0

  (310) 0x4201ec B	41feac

Coverage (%)	Name	Source Location	Module
►98.92+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-114,120-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.38
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fe40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4201b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4201cc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W23, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UDIV W2, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W2, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 4201e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-114,120-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50
cycles	2.50	2.50	3.08	2.92	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.50	2.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.38
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41fe40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4201b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4201cc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W23, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UDIV W2, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W2, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 4201e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.89	3.00
▼Loop 312 - advec_mom.cpp:108-139 - exec–	0.00	0.00
▼Loop 313 - advec_mom.cpp:110-139 - exec–	0.01	0.01
○Loop 311 - context.h:69-69 - exec	3.88	2.98
○Loop 314 - advec_mom.cpp:110-110 - exec	0.00	0.00
○Loop 310 - advec_mom.cpp:108-110 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code