OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 3.23% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41f6ac STP	X29, X30, [SP, #864]!

0x41f6b0 ADD	X29, SP, #0

0x41f6b4 STP	X19, X20, [SP, #16]

0x41f6b8 ORR	X20, XZR, X0

0x41f6bc STP	X23, X24, [SP, #48]

0x41f6c0 LDP	W1, W0, [X0, #40]

0x41f6c4 LDP	W23, W2, [X20, #48]

0x41f6c8 ADD	W1, W1, #1

0x41f6cc ADD	W2, W2, #4

0x41f6d0 STP	W2, W1, [SP, #144]

0x41f6d4 CMP	W23, W2

0x41f6d8 B.GE	41f9b8

0x41f6dc ADD	W19, W0, #3

0x41f6e0 STP	X21, X22, [SP, #32]

0x41f6e4 SUB	W22, W2, W23

0x41f6e8 CMP	W1, W19

0x41f6ec B.GE	41f9b4

0x41f6f0 SUB	W0, W19, W1

0x41f6f4 MADD	W22, W22, W0, WZR

0x41f6f8 STR	W0, [SP, #152]

0x41f6fc BL	403aa0

0x41f700 ORR	W21, WZR, W0

0x41f704 BL	403980

0x41f708 UDIV	W2, W22, W21

0x41f70c ORR	W3, WZR, W0

0x41f710 MSUB	W0, W2, W21, W22

0x41f714 CMP	W3, W0

0x41f718 B.CC	41f9f0

0x41f71c MADD	W3, W2, W3, W0

0x41f720 ADD	W0, W2, W3

0x41f724 STR	W0, [SP, #156]

0x41f728 CMP	W3, W0

0x41f72c B.CS	41f9b4

0x41f730 LDR	W1, [SP, #152]

0x41f734 FMOV	V30.2D, #0.2500000

0x41f738 FDUP	Z31.D, #80

0x41f73c STP	X25, X26, [SP, #64]

0x41f740 STP	X27, X28, [SP, #80]

0x41f744 UDIV	W0, W3, W1

0x41f748 LDR	X27, [X20, #32]

0x41f74c LDP	X25, X30, [X20]

0x41f750 LDP	X24, X28, [X20, #16]

0x41f754 MSUB	W1, W0, W1, W3

0x41f758 ADD	W0, W0, W23

0x41f75c SBFM	X26, X0, #0, #31

0x41f760 LDR	W0, [SP, #148]

0x41f764 ADD	W1, W1, W0

0x41f768 SUB	W0, W19, W1

  (293) 0x41f76c CMP	W2, W0

  (293) 0x41f770 CSEL	W4, W2, W0, #9

  (293) 0x41f774 ADD	W23, W3, W4

  (293) 0x41f778 CMP	W3, W23

  (293) 0x41f77c B.CS	41f990

  (296) 0x41f780 LDR	X2, [X30]

  (296) 0x41f784 SUB	W0, W26, #1

  (296) 0x41f788 SBFM	X0, X0, #0, #31

  (296) 0x41f78c LDR	X17, [X25]

  (296) 0x41f790 LDR	X16, [X27]

  (296) 0x41f794 MADD	X8, X0, X2, XZR

  (296) 0x41f798 LDR	X5, [X24]

  (296) 0x41f79c MADD	X9, X2, X26, XZR

  (296) 0x41f7a0 MADD	X21, X0, X17, XZR

  (296) 0x41f7a4 LDR	X3, [X28]

  (296) 0x41f7a8 MADD	X17, X17, X26, XZR

  (296) 0x41f7ac MADD	X20, X0, X16, XZR

  (296) 0x41f7b0 LDR	X2, [X28, #16]

  (296) 0x41f7b4 MADD	X16, X16, X26, XZR

  (296) 0x41f7b8 MADD	X10, X26, X5, XZR

  (296) 0x41f7bc LDR	X0, [X24, #16]

  (296) 0x41f7c0 MADD	X12, X26, X3, XZR

  (296) 0x41f7c4 LDR	X19, [X25, #16]

  (296) 0x41f7c8 LDR	X18, [X27, #16]

  (296) 0x41f7cc LDR	X22, [X30, #16]

  (296) 0x41f7d0 STP	X2, X9, [SP, #96]

  (296) 0x41f7d4 STP	X12, X8, [SP, #112]

  (296) 0x41f7d8 STP	X0, X10, [SP, #128]

  (296) 0x41f7dc CMP	W4, #1

  (296) 0x41f7e0 B.EQ	41f9e4

  (296) 0x41f7e4 SBFM	X1, X1, #0, #31

  (296) 0x41f7e8 UBFM	W2, W4, #1, #31

  (296) 0x41f7ec ADD	X11, X10, X1

  (296) 0x41f7f0 ADD	X7, X21, X1

  (296) 0x41f7f4 ADD	X11, X0, X11,LSL #3

  (296) 0x41f7f8 LDR	X0, [SP, #96]

  (296) 0x41f7fc ADD	X6, X20, X1

  (296) 0x41f800 ADD	X5, X17, X1

  (296) 0x41f804 ADD	X3, X16, X1

  (296) 0x41f808 ADD	X15, X19, X7,LSL #3

  (296) 0x41f80c ADD	X10, X8, X1

  (296) 0x41f810 ADD	X14, X18, X6,LSL #3

  (296) 0x41f814 ADD	X8, X12, X1

  (296) 0x41f818 ADD	X9, X9, X1

  (296) 0x41f81c ADD	X13, X19, X5,LSL #3

  (296) 0x41f820 SUB	X15, X15, #8

  (296) 0x41f824 UBFM	X2, X2, #60, #59

  (296) 0x41f828 ADD	X12, X18, X3,LSL #3

  (296) 0x41f82c SUB	X14, X14, #8

  (296) 0x41f830 ADD	X7, X19, X7,LSL #3

  (296) 0x41f834 SUB	X13, X13, #8

  (296) 0x41f838 ADD	X6, X18, X6,LSL #3

  (296) 0x41f83c SUB	X12, X12, #8

  (296) 0x41f840 ADD	X5, X19, X5,LSL #3

  (296) 0x41f844 ADD	X3, X18, X3,LSL #3

  (296) 0x41f848 ADD	X10, X22, X10,LSL #3

  (296) 0x41f84c ADD	X9, X22, X9,LSL #3

  (296) 0x41f850 ADD	X8, X0, X8,LSL #3

  (296) 0x41f854 MOVZ	X0, #0

  (296) 0x41f858 HINT	#0

  (296) 0x41f85c HINT	#0

    (295) 0x41f860 LDR	Q22, [X3, X0]

    (295) 0x41f864 LDR	Q17, [X5, X0]

    (295) 0x41f868 LDR	Q29, [X6, X0]

    (295) 0x41f86c LDR	Q23, [X7, X0]

    (295) 0x41f870 FMUL	V17.2D, V22.2D, V17.2D

    (295) 0x41f874 LDR	Q21, [X14, X0]

    (295) 0x41f878 LDR	Q20, [X15, X0]

    (295) 0x41f87c LDR	Q19, [X12, X0]

    (295) 0x41f880 FMLA	V17.2D, V29.2D, V23.2D

    (295) 0x41f884 LDR	Q18, [X13, X0]

    (295) 0x41f888 FMLA	V17.2D, V21.2D, V20.2D

    (295) 0x41f88c FMLA	V17.2D, V19.2D, V18.2D

    (295) 0x41f890 FMUL	V17.2D, V17.2D, V30.2D

    (295) 0x41f894 STR	Q17, [X11, X0]

    (295) 0x41f898 LDR	Q16, [X10, X0]

    (295) 0x41f89c LDR	Q7, [X9, X0]

    (295) 0x41f8a0 FSUB	V16.2D, V17.2D, V16.2D

    (295) 0x41f8a4 FADD	V7.2D, V16.2D, V7.2D

    (295) 0x41f8a8 STR	Q7, [X8, X0]

    (295) 0x41f8ac ADD	X0, X0, #16

    (295) 0x41f8b0 CMP	X0, X2

    (295) 0x41f8b4 B.NE	41f860

  (296) 0x41f8b8 AND	W3, W4, #1951

  (296) 0x41f8bc TBZ	W4, #0, 41f98c

  (297) 0x41f8c0 LDR	X6, [SP, #120]

  (297) 0x41f8c4 ORR	W0, WZR, W3

  (297) 0x41f8c8 ADD	X16, X16, X1

  (297) 0x41f8cc LDP	X7, X8, [SP, #104]

  (297) 0x41f8d0 ADD	X16, X16, X0

  (297) 0x41f8d4 ADD	X21, X21, X1

  (297) 0x41f8d8 ADD	X20, X20, X1

  (297) 0x41f8dc ADD	X17, X17, X1

  (297) 0x41f8e0 ADD	X21, X21, X0

  (297) 0x41f8e4 ADD	X20, X20, X0

  (297) 0x41f8e8 ADD	X17, X17, X0

  (297) 0x41f8ec SUB	W4, W4, W3

  (297) 0x41f8f0 ADD	X5, X19, X21,LSL #3

  (297) 0x41f8f4 WHILELO	P7.D, XZR, X4

  (297) 0x41f8f8 LD1D	{Z26.D}, P7/Z, [X19, X21,LSL #3]

  (297) 0x41f8fc LDR	X2, [SP, #136]

  (297) 0x41f900 ADD	X6, X6, X1

  (297) 0x41f904 ADD	X3, X18, X20,LSL #3

  (297) 0x41f908 LD1D	{Z6.D}, P7/Z, [X18, X20,LSL #3]

  (297) 0x41f90c LD1D	{Z5.D}, P7/Z, [X19, X17,LSL #3]

  (297) 0x41f910 ADD	X7, X7, X1

  (297) 0x41f914 ADD	X6, X6, X0

  (297) 0x41f918 ADD	X4, X19, X17,LSL #3

  (297) 0x41f91c LD1D	{Z4.D}, P7/Z, [X18, X16,LSL #3]

  (297) 0x41f920 FMUL	Z26.D, P7/M, Z26.D, Z6.D

  (297) 0x41f924 ADD	X7, X7, X0

  (297) 0x41f928 SUB	X5, X5, #8

  (297) 0x41f92c FMLA	Z26.D, P7/M, Z5.D, Z4.D

  (297) 0x41f930 LD1D	{Z3.D}, P7/Z, [X5, MUL VL]

  (297) 0x41f934 SUB	X3, X3, #8

  (297) 0x41f938 SUB	X4, X4, #8

  (297) 0x41f93c LD1D	{Z2.D}, P7/Z, [X3, MUL VL]

  (297) 0x41f940 LD1D	{Z27.D}, P7/Z, [X4, MUL VL]

  (297) 0x41f944 FMLA	Z26.D, P7/M, Z3.D, Z2.D

  (297) 0x41f948 ADD	X2, X2, X1

  (297) 0x41f94c ADD	X1, X8, X1

  (297) 0x41f950 ADD	X8, X18, X16,LSL #3

  (297) 0x41f954 ADD	X2, X2, X0

  (297) 0x41f958 ADD	X1, X1, X0

  (297) 0x41f95c SUB	X0, X8, #8

  (297) 0x41f960 LD1D	{Z1.D}, P7/Z, [X0, MUL VL]

  (297) 0x41f964 FMLA	Z26.D, P7/M, Z27.D, Z1.D

  (297) 0x41f968 FMUL	Z26.D, P7/M, Z26.D, Z31.D

  (297) 0x41f96c LDR	X0, [SP, #128]

  (297) 0x41f970 ST1D	{Z26.D}, P7, [X0, X2,LSL #3]

  (297) 0x41f974 LD1D	{Z0.D}, P7/Z, [X22, X6,LSL #3]

  (297) 0x41f978 LD1D	{Z28.D}, P7/Z, [X22, X7,LSL #3]

  (297) 0x41f97c FSUB	Z26.D, P7/M, Z26.D, Z0.D

  (297) 0x41f980 FADD	Z26.D, P7/M, Z26.D, Z28.D

  (297) 0x41f984 LDR	X0, [SP, #96]

  (297) 0x41f988 ST1D	{Z26.D}, P7, [X0, X1,LSL #3]

  (296) 0x41f98c ORR	W3, WZR, W23

  (293) 0x41f990 LDR	W0, [SP, #144]

  (293) 0x41f994 ADD	X26, X26, #1

  (293) 0x41f998 CMP	W0, W26

  (293) 0x41f99c B.LE	41f9c8

  (293) 0x41f9a0 LDR	W0, [SP, #156]

  (293) 0x41f9a4 LDR	W1, [SP, #148]

  (293) 0x41f9a8 SUB	W2, W0, W3

  (293) 0x41f9ac LDR	W0, [SP, #152]

  (293) 0x41f9b0 B	41f76c

0x41f9b4 LDP	X21, X22, [SP, #32]

0x41f9b8 LDP	X19, X20, [SP, #16]

0x41f9bc LDP	X23, X24, [SP, #48]

0x41f9c0 LDP	X29, X30, [SP], #160

0x41f9c4 RET

(292) 0x41f9c8 LDP	X21, X22, [SP, #32]

(292) 0x41f9cc LDP	X25, X26, [SP, #64]

(292) 0x41f9d0 LDP	X27, X28, [SP, #80]

(292) 0x41f9d4 LDP	X19, X20, [SP, #16]

(292) 0x41f9d8 LDP	X23, X24, [SP, #48]

(292) 0x41f9dc LDP	X29, X30, [SP], #160

(292) 0x41f9e0 RET

  (294) 0x41f9e4 MOVZ	W3, #0

  (294) 0x41f9e8 SBFM	X1, X1, #0, #31

  (294) 0x41f9ec B	41f8c0

0x41f9f0 ADD	W2, W2, #1

0x41f9f4 MOVZ	W0, #0

0x41f9f8 B	41f71c

0x41f9fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 56% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.00
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f6ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W1, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W23, W2, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W2, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W2, W1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f9b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W2, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f9b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W22, W22, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W2, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f9f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W2, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W2, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f9b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V30.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z31.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X27, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X28, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X26, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41f71c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 56% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.00
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f6ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W1, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W23, W2, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W2, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W2, W1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W23, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f9b8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W22, W2, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f9b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W22, W22, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W2, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f9f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W2, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W2, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f9b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V30.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z31.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X27, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X28, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X26, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41f71c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.23	2.49
▼Loop 292 - advec_mom.cpp:167-172 - exec–	0.00	0.00
○Loop 297 - advec_mom.cpp:170-172 - exec	0.00	0.00
▼Loop 296 - advec_mom.cpp:169-172 - exec–	0.00	0.01
○Loop 295 - advec_mom.cpp:170-172 - exec	3.22	2.47
○Loop 293 - advec_mom.cpp:169-172 - exec	0.00	0.01
○Loop 294 - context.h:69-69 - exec	0.00	0.00

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