OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage (incl. loops): 4.76% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41f490 STP	X29, X30, [SP, #944]!

0x41f494 ADD	X29, SP, #0

0x41f498 STP	X19, X20, [SP, #16]

0x41f49c STP	X21, X22, [SP, #32]

0x41f4a0 STP	X25, X26, [SP, #64]

0x41f4a4 LDP	W25, W19, [X0, #40]

0x41f4a8 LDP	W20, W22, [X0, #32]

0x41f4ac ADD	W25, W25, #1

0x41f4b0 ADD	W19, W19, #3

0x41f4b4 CMP	W25, W19

0x41f4b8 B.GE	41f680

0x41f4bc ADD	W20, W20, #1

0x41f4c0 ADD	W22, W22, #3

0x41f4c4 SUB	W26, W19, W25

0x41f4c8 CMP	W20, W22

0x41f4cc B.GE	41f680

0x41f4d0 SUB	W21, W22, W20

0x41f4d4 STP	X23, X24, [SP, #48]

0x41f4d8 ORR	X23, XZR, X0

0x41f4dc MADD	W26, W26, W21, WZR

0x41f4e0 BL	403aa0

0x41f4e4 ORR	W24, WZR, W0

0x41f4e8 BL	403980

0x41f4ec UDIV	W1, W26, W24

0x41f4f0 ORR	W2, WZR, W0

0x41f4f4 MSUB	W0, W1, W24, W26

0x41f4f8 CMP	W2, W0

0x41f4fc B.CC	41f6a0

0x41f500 MADD	W2, W1, W2, W0

0x41f504 ADD	W30, W1, W2

0x41f508 CMP	W2, W30

0x41f50c B.CS	41f67c

0x41f510 UDIV	W0, W2, W21

0x41f514 LDP	X17, X18, [X23]

0x41f518 LDP	X15, X16, [X23, #16]

0x41f51c MSUB	W5, W0, W21, W2

0x41f520 ADD	W0, W0, W25

0x41f524 SBFM	X10, X0, #0, #31

0x41f528 ADD	W5, W5, W20

0x41f52c SUB	W0, W22, W5

  (287) 0x41f530 CMP	W1, W0

  (287) 0x41f534 CSEL	W4, W1, W0, #9

  (287) 0x41f538 ADD	W14, W2, W4

  (287) 0x41f53c CMP	W2, W14

  (287) 0x41f540 B.CS	41f660

  (290) 0x41f544 LDR	X24, [X15]

  (290) 0x41f548 LDR	X8, [X16]

  (290) 0x41f54c LDR	X9, [X17]

  (290) 0x41f550 MADD	X24, X10, X24, XZR

  (290) 0x41f554 LDR	X11, [X18]

  (290) 0x41f558 MADD	X8, X10, X8, XZR

  (290) 0x41f55c LDR	X23, [X15, #16]

  (290) 0x41f560 MADD	X9, X10, X9, XZR

  (290) 0x41f564 LDR	X12, [X16, #16]

  (290) 0x41f568 MADD	X11, X10, X11, XZR

  (290) 0x41f56c LDR	X13, [X17, #16]

  (290) 0x41f570 LDR	X22, [X18, #16]

  (290) 0x41f574 CMP	W4, #1

  (290) 0x41f578 B.EQ	41f694

  (290) 0x41f57c SBFM	X5, X5, #0, #31

  (290) 0x41f580 UBFM	W2, W4, #1, #31

  (290) 0x41f584 ADD	X3, X8, X5

  (290) 0x41f588 ADD	X1, X9, X5

  (290) 0x41f58c UBFM	X3, X3, #61, #60

  (290) 0x41f590 ADD	X25, X24, X5

  (290) 0x41f594 ADD	X1, X13, X1,LSL #3

  (290) 0x41f598 ADD	X7, X11, X5

  (290) 0x41f59c SUB	X6, X3, #8

  (290) 0x41f5a0 ADD	X25, X23, X25,LSL #3

  (290) 0x41f5a4 ADD	X7, X22, X7,LSL #3

  (290) 0x41f5a8 MOVZ	X0, #0

  (290) 0x41f5ac ADD	X6, X12, X6

  (290) 0x41f5b0 ADD	X3, X12, X3

  (290) 0x41f5b4 UBFM	X2, X2, #60, #59

  (290) 0x41f5b8 HINT	#0

  (290) 0x41f5bc HINT	#0

    (289) 0x41f5c0 LDR	Q31, [X25, X0]

    (289) 0x41f5c4 LDR	Q1, [X1, X0]

    (289) 0x41f5c8 LDR	Q0, [X6, X0]

    (289) 0x41f5cc LDR	Q30, [X3, X0]

    (289) 0x41f5d0 LDR	Q29, [X7, X0]

    (289) 0x41f5d4 FMLA	V0.2D, V31.2D, V1.2D

    (289) 0x41f5d8 FSUB	V30.2D, V0.2D, V30.2D

    (289) 0x41f5dc FDIV	V29.2D, V30.2D, V29.2D

    (289) 0x41f5e0 STR	Q29, [X1, X0]

    (289) 0x41f5e4 ADD	X0, X0, #16

    (289) 0x41f5e8 CMP	X0, X2

    (289) 0x41f5ec B.NE	41f5c0

  (290) 0x41f5f0 AND	W1, W4, #1951

  (290) 0x41f5f4 TBZ	W4, #0, 41f65c

  (291) 0x41f5f8 ORR	W2, WZR, W1

  (291) 0x41f5fc ADD	X0, X8, X5

  (291) 0x41f600 ADD	X0, X0, X2

  (291) 0x41f604 SUB	W1, W4, W1

  (291) 0x41f608 WHILELO	P7.D, XZR, X1

  (291) 0x41f60c UBFM	X0, X0, #61, #60

  (291) 0x41f610 ADD	X9, X9, X5

  (291) 0x41f614 ADD	X24, X24, X5

  (291) 0x41f618 ADD	X11, X11, X5

  (291) 0x41f61c SUB	X3, X0, #8

  (291) 0x41f620 ADD	X9, X9, X2

  (291) 0x41f624 LD1D	{Z28.D}, P7/Z, [X13, X9,LSL #3]

  (291) 0x41f628 ADD	X1, X12, X3

  (291) 0x41f62c ADD	X24, X24, X2

  (291) 0x41f630 LD1D	{Z3.D}, P7/Z, [X1, MUL VL]

  (291) 0x41f634 LD1D	{Z4.D}, P7/Z, [X23, X24,LSL #3]

  (291) 0x41f638 FMUL	Z28.D, P7/M, Z28.D, Z4.D

  (291) 0x41f63c ADD	X11, X11, X2

  (291) 0x41f640 ADD	X12, X12, X0

  (291) 0x41f644 LD1D	{Z27.D}, P7/Z, [X22, X11,LSL #3]

  (291) 0x41f648 LD1D	{Z2.D}, P7/Z, [X12, MUL VL]

  (291) 0x41f64c FADD	Z28.D, P7/M, Z28.D, Z3.D

  (291) 0x41f650 FSUB	Z28.D, P7/M, Z28.D, Z2.D

  (291) 0x41f654 FDIV	Z28.D, P7/M, Z28.D, Z27.D

  (291) 0x41f658 ST1D	{Z28.D}, P7, [X13, X9,LSL #3]

  (290) 0x41f65c ORR	W2, WZR, W14

  (287) 0x41f660 ADD	X10, X10, #1

  (287) 0x41f664 CMP	W19, W10

  (287) 0x41f668 B.LE	41f67c

  (287) 0x41f66c SUB	W1, W30, W2

  (287) 0x41f670 ORR	W0, WZR, W21

  (287) 0x41f674 ORR	W5, WZR, W20

  (287) 0x41f678 B	41f530

(286) 0x41f67c LDP	X23, X24, [SP, #48]

(286) 0x41f680 LDP	X19, X20, [SP, #16]

(286) 0x41f684 LDP	X21, X22, [SP, #32]

(286) 0x41f688 LDP	X25, X26, [SP, #64]

(286) 0x41f68c LDP	X29, X30, [SP], #80

(286) 0x41f690 RET

  (288) 0x41f694 MOVZ	W1, #0

  (288) 0x41f698 SBFM	X5, X5, #0, #31

  (288) 0x41f69c B	41f5f8

0x41f6a0 ADD	W1, W1, #1

0x41f6a4 MOVZ	W0, #0

0x41f6a8 B	41f500

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50
cycles	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	5.38
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f490

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W22, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f680 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f680 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W1, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f6a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f67c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X17, X18, [X23]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X16, [X23, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W5, W0, W21, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X10, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W5, W5, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W22, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 41f500 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50
cycles	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	5.38
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41f490

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W22, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f680 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f680 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W1, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f6a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f67c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X17, X18, [X23]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X16, [X23, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W5, W0, W21, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X10, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W5, W5, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W22, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 41f500 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.76	3.67
▼Loop 286 - advec_mom.cpp:146-149 - exec–	0.00	0.00
▼Loop 290 - advec_mom.cpp:148-149 - exec–	0.00	0.01
○Loop 289 - advec_mom.cpp:149-149 - exec	4.76	3.65
○Loop 287 - advec_mom.cpp:148-149 - exec	0.00	0.01
○Loop 291 - advec_mom.cpp:149-149 - exec	0.00	0.00
○Loop 288 - context.h:69-69 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code