OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage (incl. loops): 3.06% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41ef40 STP	X29, X30, [SP, #864]!

0x41ef44 ADD	X29, SP, #0

0x41ef48 STP	X19, X20, [SP, #16]

0x41ef4c ORR	X20, XZR, X0

0x41ef50 STP	X21, X22, [SP, #32]

0x41ef54 LDP	W22, W1, [X0, #48]

0x41ef58 LDP	W2, W0, [X0, #40]

0x41ef5c ADD	W1, W1, #3

0x41ef60 ADD	W22, W22, #1

0x41ef64 STP	W1, W2, [SP, #144]

0x41ef68 CMP	W22, W1

0x41ef6c B.GE	41f248

0x41ef70 ADD	W19, W0, #4

0x41ef74 STP	X23, X24, [SP, #48]

0x41ef78 SUB	W23, W1, W22

0x41ef7c CMP	W2, W19

0x41ef80 B.GE	41f244

0x41ef84 SUB	W0, W19, W2

0x41ef88 MADD	W23, W23, W0, WZR

0x41ef8c STR	W0, [SP, #152]

0x41ef90 BL	403aa0

0x41ef94 ORR	W21, WZR, W0

0x41ef98 BL	403980

0x41ef9c UDIV	W3, W23, W21

0x41efa0 ORR	W2, WZR, W0

0x41efa4 MSUB	W0, W3, W21, W23

0x41efa8 CMP	W2, W0

0x41efac B.CC	41f280

0x41efb0 MADD	W2, W3, W2, W0

0x41efb4 ADD	W0, W3, W2

0x41efb8 STR	W0, [SP, #156]

0x41efbc CMP	W2, W0

0x41efc0 B.CS	41f244

0x41efc4 LDR	W1, [SP, #152]

0x41efc8 FMOV	V30.2D, #0.2500000

0x41efcc FDUP	Z31.D, #80

0x41efd0 STP	X25, X26, [SP, #64]

0x41efd4 STP	X27, X28, [SP, #80]

0x41efd8 UDIV	W0, W2, W1

0x41efdc LDR	X26, [X20, #32]

0x41efe0 LDP	X28, X30, [X20]

0x41efe4 LDP	X27, X25, [X20, #16]

0x41efe8 MSUB	W1, W0, W1, W2

0x41efec ADD	W0, W0, W22

0x41eff0 SBFM	X10, X0, #0, #31

0x41eff4 LDR	W0, [SP, #148]

0x41eff8 ADD	W1, W1, W0

0x41effc SUB	W0, W19, W1

  (275) 0x41f000 CMP	W3, W0

  (275) 0x41f004 CSEL	W5, W3, W0, #9

  (275) 0x41f008 ADD	W24, W2, W5

  (275) 0x41f00c CMP	W2, W24

  (275) 0x41f010 B.CS	41f220

  (278) 0x41f014 LDR	X0, [X25]

  (278) 0x41f018 SUB	W4, W10, #1

  (278) 0x41f01c SBFM	X4, X4, #0, #31

  (278) 0x41f020 LDR	X3, [X27]

  (278) 0x41f024 LDR	X2, [X30]

  (278) 0x41f028 MADD	X13, X10, X0, XZR

  (278) 0x41f02c LDR	X0, [X27, #16]

  (278) 0x41f030 MADD	X11, X10, X3, XZR

  (278) 0x41f034 LDR	X3, [X25, #16]

  (278) 0x41f038 MADD	X2, X10, X2, XZR

  (278) 0x41f03c LDR	X18, [X26]

  (278) 0x41f040 STR	X11, [SP, #136]

  (278) 0x41f044 LDR	X19, [X28]

  (278) 0x41f048 LDR	X20, [X26, #16]

  (278) 0x41f04c LDR	X21, [X28, #16]

  (278) 0x41f050 MADD	X22, X4, X19, XZR

  (278) 0x41f054 LDR	X23, [X30, #16]

  (278) 0x41f058 MADD	X4, X4, X18, XZR

  (278) 0x41f05c STP	X3, X13, [SP, #104]

  (278) 0x41f060 MADD	X19, X19, X10, XZR

  (278) 0x41f064 MADD	X18, X18, X10, XZR

  (278) 0x41f068 STP	X2, X0, [SP, #120]

  (278) 0x41f06c CMP	W5, #1

  (278) 0x41f070 B.EQ	41f274

  (278) 0x41f074 SBFM	X1, X1, #0, #31

  (278) 0x41f078 UBFM	W3, W5, #1, #31

  (278) 0x41f07c ADD	X12, X11, X1

  (278) 0x41f080 ADD	X9, X22, X1

  (278) 0x41f084 ADD	X12, X0, X12,LSL #3

  (278) 0x41f088 LDR	X0, [SP, #104]

  (278) 0x41f08c ADD	X8, X4, X1

  (278) 0x41f090 ADD	X7, X19, X1

  (278) 0x41f094 ADD	X6, X18, X1

  (278) 0x41f098 ADD	X2, X2, X1

  (278) 0x41f09c ADD	X16, X21, X9,LSL #3

  (278) 0x41f0a0 ADD	X15, X20, X8,LSL #3

  (278) 0x41f0a4 UBFM	X2, X2, #61, #60

  (278) 0x41f0a8 ADD	X11, X13, X1

  (278) 0x41f0ac ADD	X14, X21, X7,LSL #3

  (278) 0x41f0b0 SUB	X17, X2, #8

  (278) 0x41f0b4 ORR	X9, XZR, X16

  (278) 0x41f0b8 ADD	X13, X20, X6,LSL #3

  (278) 0x41f0bc ORR	X8, XZR, X15

  (278) 0x41f0c0 ADD	X2, X23, X2

  (278) 0x41f0c4 ADD	X7, X21, X7,LSL #3

  (278) 0x41f0c8 ADD	X17, X23, X17

  (278) 0x41f0cc SUB	X16, X16, #8

  (278) 0x41f0d0 ADD	X6, X20, X6,LSL #3

  (278) 0x41f0d4 SUB	X15, X15, #8

  (278) 0x41f0d8 SUB	X14, X14, #8

  (278) 0x41f0dc ADD	X11, X0, X11,LSL #3

  (278) 0x41f0e0 SUB	X13, X13, #8

  (278) 0x41f0e4 UBFM	X3, X3, #60, #59

  (278) 0x41f0e8 MOVZ	X0, #0

    (277) 0x41f0ec LDR	Q22, [X6, X0]

    (277) 0x41f0f0 LDR	Q17, [X7, X0]

    (277) 0x41f0f4 LDR	Q29, [X8, X0]

    (277) 0x41f0f8 LDR	Q23, [X9, X0]

    (277) 0x41f0fc FMUL	V17.2D, V22.2D, V17.2D

    (277) 0x41f100 LDR	Q21, [X15, X0]

    (277) 0x41f104 LDR	Q20, [X16, X0]

    (277) 0x41f108 LDR	Q19, [X13, X0]

    (277) 0x41f10c FMLA	V17.2D, V29.2D, V23.2D

    (277) 0x41f110 LDR	Q18, [X14, X0]

    (277) 0x41f114 FMLA	V17.2D, V21.2D, V20.2D

    (277) 0x41f118 FMLA	V17.2D, V19.2D, V18.2D

    (277) 0x41f11c FMUL	V17.2D, V17.2D, V30.2D

    (277) 0x41f120 STR	Q17, [X12, X0]

    (277) 0x41f124 LDR	Q16, [X17, X0]

    (277) 0x41f128 LDR	Q7, [X2, X0]

    (277) 0x41f12c FSUB	V16.2D, V17.2D, V16.2D

    (277) 0x41f130 FADD	V7.2D, V16.2D, V7.2D

    (277) 0x41f134 STR	Q7, [X11, X0]

    (277) 0x41f138 ADD	X0, X0, #16

    (277) 0x41f13c CMP	X0, X3

    (277) 0x41f140 B.NE	41f0ec

  (278) 0x41f144 AND	W3, W5, #1951

  (278) 0x41f148 TBZ	W5, #0, 41f21c

  (279) 0x41f14c LDP	X8, X0, [SP, #112]

  (279) 0x41f150 ADD	X22, X22, X1

  (279) 0x41f154 ADD	X4, X4, X1

  (279) 0x41f158 ADD	X19, X19, X1

  (279) 0x41f15c ADD	X18, X18, X1

  (279) 0x41f160 SUB	W5, W5, W3

  (279) 0x41f164 WHILELO	P7.D, XZR, X5

  (279) 0x41f168 LDR	X6, [SP, #136]

  (279) 0x41f16c ADD	X2, X0, X1

  (279) 0x41f170 ORR	W0, WZR, W3

  (279) 0x41f174 ADD	X2, X2, X0

  (279) 0x41f178 ADD	X4, X4, X0

  (279) 0x41f17c LD1D	{Z6.D}, P7/Z, [X20, X4,LSL #3]

  (279) 0x41f180 ADD	X22, X22, X0

  (279) 0x41f184 ADD	X19, X19, X0

  (279) 0x41f188 LD1D	{Z26.D}, P7/Z, [X21, X22,LSL #3]

  (279) 0x41f18c LD1D	{Z5.D}, P7/Z, [X21, X19,LSL #3]

  (279) 0x41f190 FMUL	Z26.D, P7/M, Z26.D, Z6.D

  (279) 0x41f194 ADD	X18, X18, X0

  (279) 0x41f198 UBFM	X2, X2, #61, #60

  (279) 0x41f19c ADD	X7, X21, X22,LSL #3

  (279) 0x41f1a0 LD1D	{Z4.D}, P7/Z, [X20, X18,LSL #3]

  (279) 0x41f1a4 FMLA	Z26.D, P7/M, Z5.D, Z4.D

  (279) 0x41f1a8 ADD	X6, X6, X1

  (279) 0x41f1ac ADD	X1, X8, X1

  (279) 0x41f1b0 ADD	X5, X21, X19,LSL #3

  (279) 0x41f1b4 ADD	X8, X20, X4,LSL #3

  (279) 0x41f1b8 ADD	X6, X6, X0

  (279) 0x41f1bc ADD	X1, X1, X0

  (279) 0x41f1c0 ADD	X3, X20, X18,LSL #3

  (279) 0x41f1c4 SUB	X0, X2, #8

  (279) 0x41f1c8 SUB	X7, X7, #8

  (279) 0x41f1cc LD1D	{Z3.D}, P7/Z, [X7, MUL VL]

  (279) 0x41f1d0 ADD	X0, X23, X0

  (279) 0x41f1d4 SUB	X8, X8, #8

  (279) 0x41f1d8 LD1D	{Z2.D}, P7/Z, [X8, MUL VL]

  (279) 0x41f1dc FMLA	Z26.D, P7/M, Z3.D, Z2.D

  (279) 0x41f1e0 ADD	X23, X23, X2

  (279) 0x41f1e4 LDR	X2, [SP, #128]

  (279) 0x41f1e8 SUB	X4, X5, #8

  (279) 0x41f1ec LD1D	{Z27.D}, P7/Z, [X4, MUL VL]

  (279) 0x41f1f0 SUB	X3, X3, #8

  (279) 0x41f1f4 LD1D	{Z1.D}, P7/Z, [X3, MUL VL]

  (279) 0x41f1f8 FMLA	Z26.D, P7/M, Z27.D, Z1.D

  (279) 0x41f1fc FMUL	Z26.D, P7/M, Z26.D, Z31.D

  (279) 0x41f200 ST1D	{Z26.D}, P7, [X2, X6,LSL #3]

  (279) 0x41f204 LD1D	{Z0.D}, P7/Z, [X0, MUL VL]

  (279) 0x41f208 LDR	X0, [SP, #104]

  (279) 0x41f20c LD1D	{Z28.D}, P7/Z, [X23, MUL VL]

  (279) 0x41f210 FSUB	Z26.D, P7/M, Z26.D, Z0.D

  (279) 0x41f214 FADD	Z26.D, P7/M, Z26.D, Z28.D

  (279) 0x41f218 ST1D	{Z26.D}, P7, [X0, X1,LSL #3]

  (278) 0x41f21c ORR	W2, WZR, W24

  (275) 0x41f220 LDR	W0, [SP, #144]

  (275) 0x41f224 ADD	X10, X10, #1

  (275) 0x41f228 CMP	W0, W10

  (275) 0x41f22c B.LE	41f258

  (275) 0x41f230 LDR	W0, [SP, #156]

  (275) 0x41f234 LDR	W1, [SP, #148]

  (275) 0x41f238 SUB	W3, W0, W2

  (275) 0x41f23c LDR	W0, [SP, #152]

  (275) 0x41f240 B	41f000

0x41f244 LDP	X23, X24, [SP, #48]

0x41f248 LDP	X19, X20, [SP, #16]

0x41f24c LDP	X21, X22, [SP, #32]

0x41f250 LDP	X29, X30, [SP], #160

0x41f254 RET

(274) 0x41f258 LDP	X23, X24, [SP, #48]

(274) 0x41f25c LDP	X25, X26, [SP, #64]

(274) 0x41f260 LDP	X27, X28, [SP, #80]

(274) 0x41f264 LDP	X19, X20, [SP, #16]

(274) 0x41f268 LDP	X21, X22, [SP, #32]

(274) 0x41f26c LDP	X29, X30, [SP], #160

(274) 0x41f270 RET

  (276) 0x41f274 MOVZ	W3, #0

  (276) 0x41f278 SBFM	X1, X1, #0, #31

  (276) 0x41f27c B	41f14c

0x41f280 ADD	W3, W3, #1

0x41f284 MOVZ	W0, #0

0x41f288 B	41efb0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.00
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41ef40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W2, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W1, W2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f248 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f244 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W3, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f280 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W3, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f244 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V30.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z31.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X26, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X28, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X25, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X10, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41efb0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 128 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.67	4.67	4.67	4.50	6.00	4.50	0.50	0.50	0.50	0.50	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.00
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41ef40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W2, W0, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W1, W2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f248 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41f244 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W3, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W3, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41f280 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W3, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41f244 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V30.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z31.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X26, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X28, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X25, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X10, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41efb0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.06	2.36
▼Loop 274 - advec_mom.cpp:95-100 - exec–	0.00	0.00
○Loop 279 - advec_mom.cpp:98-100 - exec	0.00	0.01
▼Loop 278 - advec_mom.cpp:97-100 - exec–	0.00	0.01
○Loop 277 - advec_mom.cpp:98-100 - exec	3.06	2.35
○Loop 275 - advec_mom.cpp:97-100 - exec	0.00	0.00
○Loop 276 - context.h:69-69 - exec	0.00	0.00

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Cycles summary

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ASM code