OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:65-110 [...]	Coverage (incl. loops): 3.12% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 65 - 110

--------------------------------------------------------------------------------

65: #pragma omp parallel for simd collapse(2)

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 238 - 238

--------------------------------------------------------------------------------

238:       if (__b < __a)

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41dbb0 STP	X29, X30, [SP, #912]!

0x41dbb4 ADD	X29, SP, #0

0x41dbb8 STP	X19, X20, [SP, #16]

0x41dbbc STP	X21, X22, [SP, #32]

0x41dbc0 STP	X23, X24, [SP, #48]

0x41dbc4 ORR	X23, XZR, X0

0x41dbc8 LDP	W24, W22, [X0, #64]

0x41dbcc LDP	W0, W20, [X0, #56]

0x41dbd0 ADD	W24, W24, #1

0x41dbd4 ADD	W22, W22, #2

0x41dbd8 CMP	W24, W22

0x41dbdc B.GE	41de24

0x41dbe0 ADD	W7, W0, #1

0x41dbe4 ADD	W21, W20, #4

0x41dbe8 STP	X25, X26, [SP, #64]

0x41dbec SUB	W25, W22, W24

0x41dbf0 CMP	W7, W21

0x41dbf4 B.GE	41de20

0x41dbf8 SUB	W6, W21, W7

0x41dbfc MADD	W25, W25, W6, WZR

0x41dc00 STP	W6, W7, [SP, #96]

0x41dc04 BL	403aa0

0x41dc08 ORR	W19, WZR, W0

0x41dc0c BL	403980

0x41dc10 UDIV	W5, W25, W19

0x41dc14 ORR	W2, WZR, W0

0x41dc18 LDP	W6, W7, [SP, #96]

0x41dc1c MSUB	W0, W5, W19, W25

0x41dc20 CMP	W2, W0

0x41dc24 B.CC	41ded8

  (244) 0x41dc28 MADD	W2, W5, W2, W0

  (244) 0x41dc2c ADD	W3, W5, W2

  (244) 0x41dc30 CMP	W2, W3

  (244) 0x41dc34 B.CS	41de20

  (244) 0x41dc38 UDIV	W0, W2, W6

  (244) 0x41dc3c ORR	X1, XZR, #3840

  (244) 0x41dc40 STP	X27, X28, [SP, #80]

  (244) 0x41dc44 FMOV	D28, #1.0000000

  (244) 0x41dc48 FMOV	D25, #2.0000000

  (244) 0x41dc4c MOVK	X1, #16325

  (244) 0x41dc50 FMOV	D27, #-1.0000000

  (244) 0x41dc54 MOVI	D24, #0

  (244) 0x41dc58 ADD	W20, W20, #2

  (244) 0x41dc5c LDP	X4, X28, [X23]

  (244) 0x41dc60 FMOV	D26, X1

  (244) 0x41dc64 LDP	X26, X27, [X23, #16]

  (244) 0x41dc68 MSUB	W1, W0, W6, W2

  (244) 0x41dc6c ADD	W0, W0, W24

  (244) 0x41dc70 LDP	X24, X25, [X23, #32]

  (244) 0x41dc74 SBFM	X19, X0, #0, #31

  (244) 0x41dc78 ADD	W0, W1, W7

  (244) 0x41dc7c LDR	X23, [X23, #48]

  (244) 0x41dc80 SUB	W1, W21, W0

  (244) 0x41dc84 STP	W22, W7, [SP, #96]

  (244) 0x41dc88 ORR	X7, XZR, X4

  (244) 0x41dc8c STP	W6, W3, [SP, #104]

  (244) 0x41dc90 CMP	W5, W1

  (244) 0x41dc94 CSEL	W5, W5, W1, #9

  (244) 0x41dc98 ADD	W30, W2, W5

  (244) 0x41dc9c CMP	W2, W30

  (244) 0x41dca0 B.CS	41de00

    (242) 0x41dca4 LDR	X18, [X23]

    (242) 0x41dca8 SBFM	X0, X0, #0, #31

    (242) 0x41dcac SUB	W5, W5, #1

    (242) 0x41dcb0 ADD	X8, X0, #1

    (242) 0x41dcb4 LDR	X17, [X24]

    (242) 0x41dcb8 ADD	X13, X5, X8

    (242) 0x41dcbc LDR	X16, [X27]

    (242) 0x41dcc0 MADD	X18, X19, X18, XZR

    (242) 0x41dcc4 LDR	X21, [X25]

    (242) 0x41dcc8 MADD	X17, X19, X17, XZR

    (242) 0x41dccc LDR	X10, [X26]

    (242) 0x41dcd0 MADD	X16, X19, X16, XZR

    (242) 0x41dcd4 LDR	X11, [X28]

    (242) 0x41dcd8 MADD	X21, X19, X21, XZR

    (242) 0x41dcdc LDR	X1, [X23, #16]

    (242) 0x41dce0 MADD	X10, X19, X10, XZR

    (242) 0x41dce4 LDR	X5, [X24, #16]

    (242) 0x41dce8 MADD	X11, X19, X11, XZR

    (242) 0x41dcec LDR	X2, [X27, #16]

    (242) 0x41dcf0 ADD	X18, X1, X18,LSL #3

    (242) 0x41dcf4 LDR	X14, [X7, #8]

    (242) 0x41dcf8 ADD	X17, X5, X17,LSL #3

    (242) 0x41dcfc LDR	X15, [X25, #16]

    (242) 0x41dd00 ADD	X16, X2, X16,LSL #3

    (242) 0x41dd04 LDR	X12, [X26, #16]

    (242) 0x41dd08 LDR	X9, [X28, #16]

    (242) 0x41dd0c B	41dd14

    (242) 0x41dd10 ADD	X8, X8, #1

    (242) 0x41dd14 LDR	D23, [X17, X0,LSL #3]

    (242) 0x41dd18 FCMPE	D23, #0

    (242) 0x41dd1c B.GT	41dea4

    (242) 0x41dd20 ADD	W6, W0, #1

    (242) 0x41dd24 SUB	X5, X0, #1

    (242) 0x41dd28 CMP	W20, W6

    (242) 0x41dd2c CSEL	W6, W20, W6, #13

    (242) 0x41dd30 SBFM	X6, X6, #0, #31

    (242) 0x41dd34 ORR	X1, XZR, X6

    (242) 0x41dd38 ORR	X4, XZR, X0

    (242) 0x41dd3c ADD	X3, X21, X4

    (242) 0x41dd40 LDR	D29, [X14, X6,LSL #3]

    (242) 0x41dd44 ADD	X2, X11, X4

    (242) 0x41dd48 FABS	D30, D23

    (242) 0x41dd4c UBFM	X3, X3, #61, #60

    (242) 0x41dd50 UBFM	X2, X2, #61, #60

    (242) 0x41dd54 LDR	D22, [X14, X0,LSL #3]

    (242) 0x41dd58 ADD	X22, X11, X5

    (242) 0x41dd5c ADD	X6, X11, X1

    (242) 0x41dd60 LDR	D20, [X15, X3]

    (242) 0x41dd64 LDR	D21, [X9, X2]

    (242) 0x41dd68 LDR	D31, [X9, X22,LSL #3]

    (242) 0x41dd6c FDIV	D22, D22, D29

    (242) 0x41dd70 LDR	D29, [X9, X6,LSL #3]

    (242) 0x41dd74 FDIV	D30, D30, D20

    (242) 0x41dd78 FSUB	D31, D31, S21

    (242) 0x41dd7c FSUB	D29, D21, S29

    (242) 0x41dd80 FCMPE	D31, #0

    (242) 0x41dd84 FMUL	D20, D31, D29

    (242) 0x41dd88 FCSEL	D18, D27, D28, #9

    (242) 0x41dd8c FCMPE	D20, #0

    (242) 0x41dd90 FADD	D20, D30, D28

    (242) 0x41dd94 FSUB	D19, D25, S30

    (242) 0x41dd98 FMUL	D22, D22, D20

    (242) 0x41dd9c B.GT	41de38

    (242) 0x41dda0 MOVI	D31, #0

    (242) 0x41dda4 FADD	D31, D31, D21

    (242) 0x41dda8 ADD	X4, X10, X4

    (242) 0x41ddac ADD	X5, X10, X5

    (242) 0x41ddb0 ADD	X1, X10, X1

    (242) 0x41ddb4 FMUL	D31, D31, D23

    (242) 0x41ddb8 STR	D31, [X16, X0,LSL #3]

    (242) 0x41ddbc LDR	D29, [X12, X4,LSL #3]

    (242) 0x41ddc0 LDR	D30, [X12, X5,LSL #3]

    (242) 0x41ddc4 LDR	D23, [X12, X1,LSL #3]

    (242) 0x41ddc8 FSUB	D30, D30, S29

    (242) 0x41ddcc FSUB	D23, D29, S23

    (242) 0x41ddd0 FCMPE	D30, #0

    (242) 0x41ddd4 FMUL	D21, D30, D23

    (242) 0x41ddd8 FCSEL	D18, D27, D28, #9

    (242) 0x41dddc FCMPE	D21, #0

    (242) 0x41dde0 B.GT	41de64

    (242) 0x41dde4 FADD	D29, D29, D24

    (242) 0x41dde8 FMUL	D29, D29, D31

    (242) 0x41ddec STR	D29, [X18, X0,LSL #3]

    (242) 0x41ddf0 ORR	X0, XZR, X8

    (242) 0x41ddf4 CMP	X8, X13

    (242) 0x41ddf8 B.NE	41dd10

(243) 0x41ddfc ORR	W2, WZR, W30

  (244) 0x41de00 LDR	W0, [SP, #96]

  (244) 0x41de04 ADD	X19, X19, #1

  (244) 0x41de08 CMP	W0, W19

  (244) 0x41de0c B.LE	41debc

  (244) 0x41de10 LDP	W1, W0, [SP, #104]

  (244) 0x41de14 SUB	W5, W0, W2

  (244) 0x41de18 LDR	W0, [SP, #100]

  (244) 0x41de1c B	41dc90

(243) 0x41de20 LDP	X25, X26, [SP, #64]

(243) 0x41de24 LDP	X19, X20, [SP, #16]

(243) 0x41de28 LDP	X21, X22, [SP, #32]

(243) 0x41de2c LDP	X23, X24, [SP, #48]

(243) 0x41de30 LDP	X29, X30, [SP], #112

(243) 0x41de34 RET

  (241) 0x41de38 FABS	D31, D31

  (241) 0x41de3c FABS	D29, D29

  (241) 0x41de40 FMINNM	D20, D31, D29

  (241) 0x41de44 FSUB	D30, D28, S30

  (241) 0x41de48 FMUL	D31, D31, D19

  (241) 0x41de4c FMUL	D30, D30, D18

  (241) 0x41de50 FMADD	D31, D29, D22, D31

  (241) 0x41de54 FMUL	D31, D31, D26

  (241) 0x41de58 FMINNM	D31, D31, D20

  (241) 0x41de5c FMUL	D31, D31, D30

  (241) 0x41de60 B	41dda4

    (242) 0x41de64 LDR	D20, [X15, X3]

    (242) 0x41de68 FABS	D30, D30

    (242) 0x41de6c FABS	D23, D23

    (242) 0x41de70 FMINNM	D17, D30, D23

    (242) 0x41de74 FABS	D21, D31

    (242) 0x41de78 LDR	D16, [X9, X2]

    (242) 0x41de7c FMUL	D30, D30, D19

    (242) 0x41de80 FMUL	D20, D20, D16

    (242) 0x41de84 FMADD	D30, D23, D22, D30

    (242) 0x41de88 FDIV	D23, D21, D20

    (242) 0x41de8c FMUL	D30, D30, D26

    (242) 0x41de90 FMINNM	D30, D30, D17

    (242) 0x41de94 FSUB	D23, D28, S23

    (242) 0x41de98 FMUL	D23, D23, D18

    (242) 0x41de9c FMADD	D29, D30, D23, D29

    (242) 0x41dea0 B	41dde8

    (242) 0x41dea4 SUB	X4, X0, #1

    (242) 0x41dea8 SUB	W1, W0, #2

    (242) 0x41deac ORR	X6, XZR, X4

    (242) 0x41deb0 SBFM	X1, X1, #0, #31

    (242) 0x41deb4 ORR	X5, XZR, X0

    (242) 0x41deb8 B	41dd3c

  (244) 0x41debc LDP	X25, X26, [SP, #64]

  (244) 0x41dec0 LDP	X27, X28, [SP, #80]

  (244) 0x41dec4 LDP	X19, X20, [SP, #16]

  (244) 0x41dec8 LDP	X21, X22, [SP, #32]

  (244) 0x41decc LDP	X23, X24, [SP, #48]

  (244) 0x41ded0 LDP	X29, X30, [SP], #112

  (244) 0x41ded4 RET

  (244) 0x41ded8 ADD	W5, W5, #1

  (244) 0x41dedc MOVZ	W0, #0

  (244) 0x41dee0 B	41dc28

Coverage (%)	Name	Source Location	Module
►98.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.04 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41dbb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDP W24, W22, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W20, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W24, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W24, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41de24 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W20, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W25, W22, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41de20 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W6, W21, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W25, W25, W6, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STP W6, W7, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W5, W25, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W6, W7, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB W0, W5, W19, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41ded8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00
cycles	2.50	2.50	3.25	3.08	3.17	3.17	3.17	3.17	0.00	0.00	0.00	0.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.04 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41dbb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDP W24, W22, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W20, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W24, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W24, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41de24 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W20, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W25, W22, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41de20 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W6, W21, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W25, W25, W6, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STP W6, W7, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W5, W25, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W6, W7, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB W0, W5, W19, W25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 41ded8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.12	2.41
▼Loop 243 - advec_cell.cpp:65-110 - exec–	0.00	0.00
○Loop 244 - advec_cell.cpp:65-110 - exec	0.00	0.01
▼Loop 241 - advec_cell.cpp:71-110 - exec–	0.00	0.01
○Loop 242 - advec_cell.cpp:71-110 - exec	3.12	2.39

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code