OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage (incl. loops): 4.16% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 208 - 216

--------------------------------------------------------------------------------

208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41d880 STP	X29, X30, [SP, #864]!

0x41d884 ADD	X29, SP, #0

0x41d888 STP	X19, X20, [SP, #16]

0x41d88c ORR	X20, XZR, X0

0x41d890 STP	X21, X22, [SP, #32]

0x41d894 LDP	W22, W2, [X0, #56]

0x41d898 LDP	W1, W0, [X0, #48]

0x41d89c ADD	W2, W2, #2

0x41d8a0 ADD	W22, W22, #1

0x41d8a4 ADD	W1, W1, #1

0x41d8a8 STP	W2, W1, [SP, #144]

0x41d8ac CMP	W22, W2

0x41d8b0 B.GE	41db6c

0x41d8b4 ADD	W19, W0, #2

0x41d8b8 STP	X23, X24, [SP, #48]

0x41d8bc SUB	W23, W2, W22

0x41d8c0 CMP	W1, W19

0x41d8c4 B.GE	41db68

0x41d8c8 SUB	W0, W19, W1

0x41d8cc MADD	W23, W23, W0, WZR

0x41d8d0 STR	W0, [SP, #152]

0x41d8d4 BL	403aa0

0x41d8d8 ORR	W21, WZR, W0

0x41d8dc BL	403980

0x41d8e0 UDIV	W4, W23, W21

0x41d8e4 ORR	W2, WZR, W0

0x41d8e8 MSUB	W0, W4, W21, W23

0x41d8ec CMP	W2, W0

0x41d8f0 B.CC	41dba4

0x41d8f4 MADD	W2, W4, W2, W0

0x41d8f8 ADD	W0, W4, W2

0x41d8fc STR	W0, [SP, #156]

0x41d900 CMP	W2, W0

0x41d904 B.CS	41db68

0x41d908 LDR	W1, [SP, #152]

0x41d90c STP	X25, X26, [SP, #64]

0x41d910 STP	X27, X28, [SP, #80]

0x41d914 UDIV	W0, W2, W1

0x41d918 LDP	X24, X30, [X20]

0x41d91c LDP	X25, X26, [X20, #16]

0x41d920 LDP	X28, X27, [X20, #32]

0x41d924 MSUB	W1, W0, W1, W2

0x41d928 ADD	W0, W0, W22

0x41d92c SBFM	X6, X0, #0, #31

0x41d930 LDR	W0, [SP, #148]

0x41d934 ADD	W1, W1, W0

0x41d938 SUB	W0, W19, W1

0x41d93c HINT	#0

  (236) 0x41d940 CMP	W4, W0

  (236) 0x41d944 CSEL	W5, W4, W0, #9

  (236) 0x41d948 ADD	W23, W2, W5

  (236) 0x41d94c CMP	W2, W23

  (236) 0x41d950 B.CS	41db44

  (239) 0x41d954 LDR	X3, [X25]

  (239) 0x41d958 LDR	X2, [X27]

  (239) 0x41d95c LDR	X0, [X26]

  (239) 0x41d960 MADD	X17, X3, X6, XZR

  (239) 0x41d964 LDR	X4, [X28]

  (239) 0x41d968 MADD	X16, X2, X6, XZR

  (239) 0x41d96c ADD	X7, X3, X17

  (239) 0x41d970 LDR	X3, [X30]

  (239) 0x41d974 MADD	X15, X0, X6, XZR

  (239) 0x41d978 LDR	X9, [X28, #16]

  (239) 0x41d97c ADD	X8, X2, X16

  (239) 0x41d980 MADD	X2, X6, X4, XZR

  (239) 0x41d984 LDR	X14, [X24]

  (239) 0x41d988 ADD	X0, X0, X15

  (239) 0x41d98c MADD	X10, X6, X3, XZR

  (239) 0x41d990 LDR	X22, [X24, #16]

  (239) 0x41d994 LDR	X19, [X25, #16]

  (239) 0x41d998 MADD	X14, X6, X14, XZR

  (239) 0x41d99c LDR	X18, [X26, #16]

  (239) 0x41d9a0 LDR	X20, [X27, #16]

  (239) 0x41d9a4 LDR	X21, [X30, #16]

  (239) 0x41d9a8 STP	X0, X8, [SP, #96]

  (239) 0x41d9ac STP	X10, X7, [SP, #112]

  (239) 0x41d9b0 STP	X9, X2, [SP, #128]

  (239) 0x41d9b4 CMP	W5, #1

  (239) 0x41d9b8 B.EQ	41db98

  (239) 0x41d9bc SBFM	X1, X1, #0, #31

  (239) 0x41d9c0 UBFM	W4, W5, #1, #31

  (239) 0x41d9c4 ADD	X11, X7, X1

  (239) 0x41d9c8 LDR	X7, [SP, #96]

  (239) 0x41d9cc ADD	X13, X2, X1

  (239) 0x41d9d0 ADD	X13, X9, X13,LSL #3

  (239) 0x41d9d4 ADD	X2, X10, X1

  (239) 0x41d9d8 ADD	X9, X8, X1

  (239) 0x41d9dc ADD	X3, X14, X1

  (239) 0x41d9e0 ADD	X12, X17, X1

  (239) 0x41d9e4 ADD	X11, X19, X11,LSL #3

  (239) 0x41d9e8 ADD	X10, X16, X1

  (239) 0x41d9ec ADD	X8, X15, X1

  (239) 0x41d9f0 ADD	X3, X22, X3,LSL #3

  (239) 0x41d9f4 ADD	X12, X19, X12,LSL #3

  (239) 0x41d9f8 MOVZ	X0, #0

  (239) 0x41d9fc UBFM	X4, X4, #60, #59

  (239) 0x41da00 ADD	X7, X7, X1

  (239) 0x41da04 ADD	X2, X21, X2,LSL #3

  (239) 0x41da08 ADD	X10, X20, X10,LSL #3

  (239) 0x41da0c ADD	X9, X20, X9,LSL #3

  (239) 0x41da10 ADD	X8, X18, X8,LSL #3

  (239) 0x41da14 ADD	X7, X18, X7,LSL #3

  (239) 0x41da18 HINT	#0

  (239) 0x41da1c HINT	#0

    (238) 0x41da20 LDR	Q31, [X13, X0]

    (238) 0x41da24 LDR	Q30, [X3, X0]

    (238) 0x41da28 LDR	Q1, [X2, X0]

    (238) 0x41da2c LDR	Q0, [X10, X0]

    (238) 0x41da30 FMUL	V30.2D, V30.2D, V31.2D

    (238) 0x41da34 LDR	Q2, [X12, X0]

    (238) 0x41da38 LDR	Q27, [X8, X0]

    (238) 0x41da3c LDR	Q28, [X11, X0]

    (238) 0x41da40 FMLA	V0.2D, V1.2D, V30.2D

    (238) 0x41da44 LDR	Q26, [X7, X0]

    (238) 0x41da48 FADD	V2.2D, V2.2D, V30.2D

    (238) 0x41da4c LDR	Q29, [X9, X0]

    (238) 0x41da50 FADD	V27.2D, V27.2D, V31.2D

    (238) 0x41da54 FSUB	V28.2D, V2.2D, V28.2D

    (238) 0x41da58 FSUB	V26.2D, V27.2D, V26.2D

    (238) 0x41da5c FSUB	V29.2D, V0.2D, V29.2D

    (238) 0x41da60 FDIV	V26.2D, V28.2D, V26.2D

    (238) 0x41da64 FDIV	V29.2D, V29.2D, V28.2D

    (238) 0x41da68 STR	Q26, [X3, X0]

    (238) 0x41da6c STR	Q29, [X2, X0]

    (238) 0x41da70 ADD	X0, X0, #16

    (238) 0x41da74 CMP	X0, X4

    (238) 0x41da78 B.NE	41da20

  (239) 0x41da7c AND	W0, W5, #1951

  (239) 0x41da80 TBZ	W5, #0, 41db40

  (240) 0x41da84 LDR	X2, [SP, #136]

  (240) 0x41da88 ADD	X14, X14, X1

  (240) 0x41da8c ADD	X17, X17, X1

  (240) 0x41da90 LDP	X8, X7, [SP, #96]

  (240) 0x41da94 ADD	X16, X16, X1

  (240) 0x41da98 ADD	X15, X15, X1

  (240) 0x41da9c SUB	W5, W5, W0

  (240) 0x41daa0 WHILELO	P7.D, XZR, X5

  (240) 0x41daa4 LDP	X3, X4, [SP, #112]

  (240) 0x41daa8 ADD	X2, X2, X1

  (240) 0x41daac ADD	X7, X7, X1

  (240) 0x41dab0 ADD	X3, X3, X1

  (240) 0x41dab4 ADD	X4, X4, X1

  (240) 0x41dab8 ADD	X1, X8, X1

  (240) 0x41dabc ORR	W8, WZR, W0

  (240) 0x41dac0 LDR	X0, [SP, #128]

  (240) 0x41dac4 ADD	X14, X14, X8

  (240) 0x41dac8 ADD	X3, X3, X8

  (240) 0x41dacc LD1D	{Z25.D}, P7/Z, [X22, X14,LSL #3]

  (240) 0x41dad0 LD1D	{Z6.D}, P7/Z, [X21, X3,LSL #3]

  (240) 0x41dad4 ADD	X2, X2, X8

  (240) 0x41dad8 ADD	X17, X17, X8

  (240) 0x41dadc LD1D	{Z24.D}, P7/Z, [X0, X2,LSL #3]

  (240) 0x41dae0 LD1D	{Z16.D}, P7/Z, [X19, X17,LSL #3]

  (240) 0x41dae4 FMUL	Z25.D, P7/M, Z25.D, Z24.D

  (240) 0x41dae8 ADD	X16, X16, X8

  (240) 0x41daec MOVPRFX	Z22, Z25

  (240) 0x41daf0 FADD	Z22.D, P7/M, Z22.D, Z16.D

  (240) 0x41daf4 LD1D	{Z5.D}, P7/Z, [X20, X16,LSL #3]

  (240) 0x41daf8 ADD	X4, X4, X8

  (240) 0x41dafc FMUL	Z25.D, P7/M, Z25.D, Z6.D

  (240) 0x41db00 LD1D	{Z7.D}, P7/Z, [X19, X4,LSL #3]

  (240) 0x41db04 ADD	X7, X7, X8

  (240) 0x41db08 FSUB	Z22.D, P7/M, Z22.D, Z7.D

  (240) 0x41db0c LD1D	{Z4.D}, P7/Z, [X20, X7,LSL #3]

  (240) 0x41db10 ADD	X15, X15, X8

  (240) 0x41db14 ADD	X1, X1, X8

  (240) 0x41db18 LD1D	{Z3.D}, P7/Z, [X18, X15,LSL #3]

  (240) 0x41db1c LD1D	{Z23.D}, P7/Z, [X18, X1,LSL #3]

  (240) 0x41db20 FADD	Z25.D, P7/M, Z25.D, Z5.D

  (240) 0x41db24 FADD	Z24.D, P7/M, Z24.D, Z3.D

  (240) 0x41db28 FSUB	Z25.D, P7/M, Z25.D, Z4.D

  (240) 0x41db2c FSUB	Z24.D, P7/M, Z24.D, Z23.D

  (240) 0x41db30 FDIV	Z25.D, P7/M, Z25.D, Z22.D

  (240) 0x41db34 FDIV	Z22.D, P7/M, Z22.D, Z24.D

  (240) 0x41db38 ST1D	{Z22.D}, P7, [X22, X14,LSL #3]

  (240) 0x41db3c ST1D	{Z25.D}, P7, [X21, X3,LSL #3]

  (239) 0x41db40 ORR	W2, WZR, W23

  (236) 0x41db44 LDR	W0, [SP, #144]

  (236) 0x41db48 ADD	X6, X6, #1

  (236) 0x41db4c CMP	W0, W6

  (236) 0x41db50 B.LE	41db7c

  (236) 0x41db54 LDR	W0, [SP, #156]

  (236) 0x41db58 LDR	W1, [SP, #148]

  (236) 0x41db5c SUB	W4, W0, W2

  (236) 0x41db60 LDR	W0, [SP, #152]

  (236) 0x41db64 B	41d940

0x41db68 LDP	X23, X24, [SP, #48]

0x41db6c LDP	X19, X20, [SP, #16]

0x41db70 LDP	X21, X22, [SP, #32]

0x41db74 LDP	X29, X30, [SP], #160

0x41db78 RET

(235) 0x41db7c LDP	X23, X24, [SP, #48]

(235) 0x41db80 LDP	X25, X26, [SP, #64]

(235) 0x41db84 LDP	X27, X28, [SP, #80]

(235) 0x41db88 LDP	X19, X20, [SP, #16]

(235) 0x41db8c LDP	X21, X22, [SP, #32]

(235) 0x41db90 LDP	X29, X30, [SP], #160

(235) 0x41db94 RET

  (237) 0x41db98 MOVZ	W0, #0

  (237) 0x41db9c SBFM	X1, X1, #0, #31

  (237) 0x41dba0 B	41da84

0x41dba4 ADD	W4, W4, #1

0x41dba8 MOVZ	W0, #0

0x41dbac B	41d8f4

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	6.88
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41db6c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41db68 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41dba4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41db68 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X24, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X6, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41d8f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	6.88
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41db6c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41db68 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41dba4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #156]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41db68 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X24, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X6, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41d8f4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.16	3.20
▼Loop 235 - advec_cell.cpp:208-216 - exec–	0.00	0.00
○Loop 236 - advec_cell.cpp:210-213 - exec	0.00	0.01
▼Loop 239 - advec_cell.cpp:210-216 - exec–	0.00	0.00
○Loop 238 - advec_cell.cpp:211-216 - exec	4.15	3.18
○Loop 237 - context.h:69-69 - exec	0.00	0.00
○Loop 240 - advec_cell.cpp:211-216 - exec	0.00	0.00

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Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code