OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage (incl. loops): 1.39% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41d370 STP	X29, X30, [SP, #912]!

0x41d374 ADD	X29, SP, #0

0x41d378 STP	X19, X20, [SP, #16]

0x41d37c ORR	X19, XZR, X0

0x41d380 STP	X21, X22, [SP, #32]

0x41d384 LDP	W4, W22, [X0, #48]

0x41d388 LDP	W0, W2, [X0, #40]

0x41d38c SUB	W4, W4, #1

0x41d390 ADD	W22, W22, #4

0x41d394 SUB	W0, W0, #1

0x41d398 STR	W0, [SP, #100]

0x41d39c CMP	W4, W22

0x41d3a0 B.GE	41d5fc

0x41d3a4 STP	X23, X24, [SP, #48]

0x41d3a8 ADD	W23, W2, #4

0x41d3ac SUB	W21, W22, W4

0x41d3b0 STR	W4, [SP, #108]

0x41d3b4 CMP	W0, W23

0x41d3b8 B.GE	41d60c

0x41d3bc SUB	W0, W23, W0

0x41d3c0 MADD	W21, W21, W0, WZR

0x41d3c4 STR	W0, [SP, #104]

0x41d3c8 BL	403aa0

0x41d3cc ORR	W20, WZR, W0

0x41d3d0 BL	403980

0x41d3d4 UDIV	W6, W21, W20

0x41d3d8 ORR	W1, WZR, W0

0x41d3dc LDR	W4, [SP, #108]

0x41d3e0 MSUB	W0, W6, W20, W21

0x41d3e4 CMP	W1, W0

0x41d3e8 B.CC	41d62c

0x41d3ec MADD	W1, W6, W1, W0

0x41d3f0 ADD	W0, W6, W1

0x41d3f4 STR	W0, [SP, #108]

0x41d3f8 CMP	W1, W0

0x41d3fc B.CS	41d60c

0x41d400 LDR	W2, [SP, #104]

0x41d404 STP	X25, X26, [SP, #64]

0x41d408 STP	X27, X28, [SP, #80]

0x41d40c UDIV	W0, W1, W2

0x41d410 LDR	X24, [X19, #32]

0x41d414 LDP	X27, X28, [X19]

0x41d418 LDP	X25, X26, [X19, #16]

0x41d41c MSUB	W3, W0, W2, W1

0x41d420 LDR	W2, [SP, #100]

0x41d424 ADD	W0, W0, W4

0x41d428 SBFM	X0, X0, #0, #31

0x41d42c ADD	W3, W3, W2

0x41d430 SUB	W2, W23, W3

0x41d434 CMP	W6, W2

0x41d438 CSEL	W6, W6, W2, #9

0x41d43c ADD	W21, W1, W6

0x41d440 CMP	W1, W21

0x41d444 B.CS	41d5e0

    (226) 0x41d448 LDR	X8, [X25]

    (226) 0x41d44c ADD	X30, X0, #1

    (226) 0x41d450 LDR	X1, [X24]

    (226) 0x41d454 LDR	X14, [X26]

    (226) 0x41d458 MADD	X16, X0, X8, X8

    (226) 0x41d45c LDR	X15, [X27]

    (226) 0x41d460 MADD	X7, X0, X1, XZR

    (226) 0x41d464 LDR	X13, [X28]

    (226) 0x41d468 SUB	X8, X16, X8

    (226) 0x41d46c MADD	X14, X0, X14, XZR

    (226) 0x41d470 LDR	X19, [X24, #16]

    (226) 0x41d474 MADD	X15, X0, X15, XZR

    (226) 0x41d478 LDR	X17, [X25, #16]

    (226) 0x41d47c MADD	X13, X0, X13, XZR

    (226) 0x41d480 LDR	X20, [X26, #16]

    (226) 0x41d484 LDR	X23, [X27, #16]

    (226) 0x41d488 LDR	X18, [X28, #16]

    (226) 0x41d48c CMP	W6, #1

    (226) 0x41d490 B.EQ	41d620

    (226) 0x41d494 SBFM	X3, X3, #0, #31

    (226) 0x41d498 UBFM	W5, W6, #1, #31

    (226) 0x41d49c ADD	X4, X13, X3

    (226) 0x41d4a0 ADD	X12, X15, X3

    (226) 0x41d4a4 ADD	X4, X4, #1

    (226) 0x41d4a8 ADD	X2, X16, X3

    (226) 0x41d4ac ADD	X12, X23, X12,LSL #3

    (226) 0x41d4b0 ADD	X11, X18, X4,LSL #3

    (226) 0x41d4b4 ADD	X1, X8, X3

    (226) 0x41d4b8 ADD	X10, X14, X3

    (226) 0x41d4bc ADD	X9, X7, X3

    (226) 0x41d4c0 ADD	X2, X17, X2,LSL #3

    (226) 0x41d4c4 MOVZ	X0, #0

    (226) 0x41d4c8 ADD	X1, X17, X1,LSL #3

    (226) 0x41d4cc ORR	X4, XZR, X11

    (226) 0x41d4d0 UBFM	X5, X5, #60, #59

    (226) 0x41d4d4 ADD	X10, X20, X10,LSL #3

    (226) 0x41d4d8 SUB	X11, X11, #8

    (226) 0x41d4dc ADD	X9, X19, X9,LSL #3

      (225) 0x41d4e0 LDR	Q3, [X2, X0]

      (225) 0x41d4e4 LDR	Q2, [X1, X0]

      (225) 0x41d4e8 LDR	Q1, [X4, X0]

      (225) 0x41d4ec LDR	Q0, [X11, X0]

      (225) 0x41d4f0 FSUB	V2.2D, V3.2D, V2.2D

      (225) 0x41d4f4 LDR	Q30, [X12, X0]

      (225) 0x41d4f8 FADD	V1.2D, V2.2D, V1.2D

      (225) 0x41d4fc FSUB	V0.2D, V1.2D, V0.2D

      (225) 0x41d500 FADD	V30.2D, V0.2D, V30.2D

      (225) 0x41d504 STR	Q30, [X10, X0]

      (225) 0x41d508 LDR	Q29, [X2, X0]

      (225) 0x41d50c LDR	Q31, [X1, X0]

      (225) 0x41d510 FSUB	V31.2D, V29.2D, V31.2D

      (225) 0x41d514 FSUB	V31.2D, V30.2D, V31.2D

      (225) 0x41d518 STR	Q31, [X9, X0]

      (225) 0x41d51c ADD	X0, X0, #16

      (225) 0x41d520 CMP	X0, X5

      (225) 0x41d524 B.NE	41d4e0

    (226) 0x41d528 AND	W1, W6, #1951

    (226) 0x41d52c TBZ	W6, #0, 41d5ac

  (227) 0x41d530 ORR	W0, WZR, W1

  (227) 0x41d534 ADD	X13, X3, X13

  (227) 0x41d538 ADD	X16, X3, X16

  (227) 0x41d53c ADD	X8, X3, X8

  (227) 0x41d540 ADD	X13, X13, X0

  (227) 0x41d544 ADD	X15, X3, X15

  (227) 0x41d548 ADD	X14, X3, X14

  (227) 0x41d54c ADD	X3, X3, X7

  (227) 0x41d550 ADD	X16, X16, X0

  (227) 0x41d554 ADD	X8, X8, X0

  (227) 0x41d558 SUB	W6, W6, W1

  (227) 0x41d55c ADD	X15, X15, X0

  (227) 0x41d560 WHILELO	P7.D, XZR, X6

  (227) 0x41d564 LD1D	{Z5.D}, P7/Z, [X18, X13,LSL #3]

  (227) 0x41d568 LD1D	{Z4.D}, P7/Z, [X17, X16,LSL #3]

  (227) 0x41d56c LD1D	{Z7.D}, P7/Z, [X17, X8,LSL #3]

  (227) 0x41d570 LD1D	{Z28.D}, P7/Z, [X23, X15,LSL #3]

  (227) 0x41d574 ADD	X14, X14, X0

  (227) 0x41d578 ADD	X3, X3, X0

  (227) 0x41d57c FSUB	Z4.D, P7/M, Z4.D, Z7.D

  (227) 0x41d580 ADD	X13, X13, #1

  (227) 0x41d584 LD1D	{Z6.D}, P7/Z, [X18, X13,LSL #3]

  (227) 0x41d588 FADD	Z4.D, P7/M, Z4.D, Z6.D

  (227) 0x41d58c FSUB	Z4.D, P7/M, Z4.D, Z5.D

  (227) 0x41d590 FADD	Z28.D, P7/M, Z28.D, Z4.D

  (227) 0x41d594 ST1D	{Z28.D}, P7, [X20, X14,LSL #3]

  (227) 0x41d598 LD1D	{Z26.D}, P7/Z, [X17, X16,LSL #3]

  (227) 0x41d59c LD1D	{Z27.D}, P7/Z, [X17, X8,LSL #3]

  (227) 0x41d5a0 FSUB	Z26.D, P7/M, Z26.D, Z27.D

  (227) 0x41d5a4 FSUB	Z28.D, P7/M, Z28.D, Z26.D

  (227) 0x41d5a8 ST1D	{Z28.D}, P7, [X19, X3,LSL #3]

    (226) 0x41d5ac ORR	W1, WZR, W21

    (226) 0x41d5b0 ORR	X0, XZR, X30

    (226) 0x41d5b4 CMP	W22, W30

    (226) 0x41d5b8 B.LE	41d5f0

      (228) 0x41d5bc LDR	W2, [SP, #108]

      (228) 0x41d5c0 LDR	W3, [SP, #100]

      (228) 0x41d5c4 SUB	W6, W2, W1

      (228) 0x41d5c8 LDR	W2, [SP, #104]

      (228) 0x41d5cc CMP	W6, W2

      (228) 0x41d5d0 CSEL	W6, W6, W2, #9

      (228) 0x41d5d4 ADD	W21, W1, W6

      (228) 0x41d5d8 CMP	W1, W21

      (228) 0x41d5dc B.CC	41d448

      (228) 0x41d5e0 ADD	X30, X0, #1

      (228) 0x41d5e4 ORR	X0, XZR, X30

      (228) 0x41d5e8 CMP	W22, W30

      (228) 0x41d5ec B.GT	41d5bc

(223) 0x41d5f0 LDP	X23, X24, [SP, #48]

(223) 0x41d5f4 LDP	X25, X26, [SP, #64]

(223) 0x41d5f8 LDP	X27, X28, [SP, #80]

(223) 0x41d5fc LDP	X19, X20, [SP, #16]

(223) 0x41d600 LDP	X21, X22, [SP, #32]

(223) 0x41d604 LDP	X29, X30, [SP], #112

(223) 0x41d608 RET

(223) 0x41d60c LDP	X23, X24, [SP, #48]

(223) 0x41d610 LDP	X19, X20, [SP, #16]

(223) 0x41d614 LDP	X21, X22, [SP, #32]

(223) 0x41d618 LDP	X29, X30, [SP], #112

(223) 0x41d61c RET

  (224) 0x41d620 MOVZ	W1, #0

  (224) 0x41d624 SBFM	X3, X3, #0, #31

  (224) 0x41d628 B	41d530

0x41d62c ADD	W6, W6, #1

0x41d630 MOVZ	W0, #0

0x41d634 B	41d3ec

0x41d638 HINT	#0

0x41d63c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:136	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 43% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.58	5.58	5.67	5.67	6.00	5.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00
cycles	4.00	4.00	5.58	5.58	5.67	5.67	6.00	5.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (2.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W4, W22, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d5fc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W4, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W0, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d60c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W23, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W21, W21, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W21, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W4, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB W0, W6, W20, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41d62c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W6, W1, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W6, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41d60c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X24, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X27, X28, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W3, W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR W2, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W0, W0, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X0, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W3, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W23, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W6, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W6, W6, W2, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W21, W1, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41d5e0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41d3ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 43% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.58	5.58	5.67	5.67	6.00	5.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00
cycles	4.00	4.00	5.58	5.58	5.67	5.67	6.00	5.50	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (2.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d370

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W4, W22, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W4, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d5fc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W23, W2, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W22, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W4, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W0, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d60c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W23, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W21, W21, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W6, W21, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W4, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB W0, W6, W20, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41d62c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W6, W1, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W6, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W1, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41d60c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X24, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X27, X28, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W3, W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR W2, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W0, W0, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X0, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W3, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W23, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W6, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W6, W6, W2, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W21, W1, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41d5e0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41d3ec <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.39	1.07
▼Loop 223 - advec_cell.cpp:136-140 - exec–	0.00	0.00
▼Loop 224 - advec_cell.cpp:138-140 - exec–	0.00	0.00
▼Loop 226 - advec_cell.cpp:138-140 - exec–	0.00	0.00
○Loop 225 - advec_cell.cpp:139-140 - exec	1.39	1.07
○Loop 228 - advec_cell.cpp:138-138 - exec	0.00	0.01
○Loop 227 - advec_cell.cpp:139-140 - exec	0.00	0.00

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Vectorization

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Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code