OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.88% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41d060 STP	X29, X30, [SP, #880]!

0x41d064 ADD	X29, SP, #0

0x41d068 STP	X19, X20, [SP, #16]

0x41d06c ORR	X20, XZR, X0

0x41d070 STP	X21, X22, [SP, #32]

0x41d074 LDP	W22, W2, [X0, #56]

0x41d078 LDP	W1, W0, [X0, #48]

0x41d07c ADD	W2, W2, #2

0x41d080 ADD	W22, W22, #1

0x41d084 ADD	W1, W1, #1

0x41d088 STP	W2, W1, [SP, #128]

0x41d08c CMP	W22, W2

0x41d090 B.GE	41d32c

0x41d094 ADD	W19, W0, #2

0x41d098 STP	X23, X24, [SP, #48]

0x41d09c SUB	W23, W2, W22

0x41d0a0 CMP	W1, W19

0x41d0a4 B.GE	41d328

0x41d0a8 SUB	W0, W19, W1

0x41d0ac MADD	W23, W23, W0, WZR

0x41d0b0 STR	W0, [SP, #136]

0x41d0b4 BL	403aa0

0x41d0b8 ORR	W21, WZR, W0

0x41d0bc BL	403980

0x41d0c0 UDIV	W4, W23, W21

0x41d0c4 ORR	W2, WZR, W0

0x41d0c8 MSUB	W0, W4, W21, W23

0x41d0cc CMP	W2, W0

0x41d0d0 B.CC	41d364

0x41d0d4 MADD	W2, W4, W2, W0

0x41d0d8 ADD	W0, W4, W2

0x41d0dc STR	W0, [SP, #140]

0x41d0e0 CMP	W2, W0

0x41d0e4 B.CS	41d328

0x41d0e8 LDR	W1, [SP, #136]

0x41d0ec STP	X25, X26, [SP, #64]

0x41d0f0 STP	X27, X28, [SP, #80]

0x41d0f4 UDIV	W0, W2, W1

0x41d0f8 LDP	X27, X28, [X20]

0x41d0fc LDP	X24, X26, [X20, #16]

0x41d100 LDP	X25, X30, [X20, #32]

0x41d104 MSUB	W1, W0, W1, W2

0x41d108 ADD	W0, W0, W22

0x41d10c SBFM	X9, X0, #0, #31

0x41d110 LDR	W0, [SP, #132]

0x41d114 ADD	W1, W1, W0

0x41d118 SUB	W0, W19, W1

0x41d11c HINT	#0

  (218) 0x41d120 CMP	W4, W0

  (218) 0x41d124 CSEL	W5, W4, W0, #9

  (218) 0x41d128 ADD	W23, W2, W5

  (218) 0x41d12c CMP	W2, W23

  (218) 0x41d130 B.CS	41d304

  (221) 0x41d134 LDR	X0, [X28]

  (221) 0x41d138 LDR	X2, [X25]

  (221) 0x41d13c LDR	X17, [X24]

  (221) 0x41d140 MADD	X11, X9, X0, XZR

  (221) 0x41d144 LDR	X0, [X25, #16]

  (221) 0x41d148 MADD	X10, X9, X2, XZR

  (221) 0x41d14c LDR	X15, [X26]

  (221) 0x41d150 MADD	X17, X9, X17, XZR

  (221) 0x41d154 LDR	X14, [X27]

  (221) 0x41d158 STR	X10, [SP, #120]

  (221) 0x41d15c LDR	X16, [X30]

  (221) 0x41d160 MADD	X15, X9, X15, XZR

  (221) 0x41d164 LDR	X20, [X24, #16]

  (221) 0x41d168 MADD	X14, X9, X14, XZR

  (221) 0x41d16c LDR	X18, [X26, #16]

  (221) 0x41d170 MADD	X16, X9, X16, XZR

  (221) 0x41d174 LDR	X22, [X27, #16]

  (221) 0x41d178 LDR	X21, [X28, #16]

  (221) 0x41d17c LDR	X19, [X30, #16]

  (221) 0x41d180 STP	X11, X0, [SP, #104]

  (221) 0x41d184 CMP	W5, #1

  (221) 0x41d188 B.EQ	41d358

  (221) 0x41d18c SBFM	X3, X1, #0, #31

  (221) 0x41d190 UBFM	W4, W5, #1, #31

  (221) 0x41d194 ADD	X8, X17, X3

  (221) 0x41d198 ADD	X7, X16, X3

  (221) 0x41d19c ADD	X6, X15, X3

  (221) 0x41d1a0 ADD	X13, X20, X8,LSL #3

  (221) 0x41d1a4 ADD	X1, X11, X3

  (221) 0x41d1a8 ADD	X12, X19, X7,LSL #3

  (221) 0x41d1ac ADD	X2, X14, X3

  (221) 0x41d1b0 ADD	X10, X10, X3

  (221) 0x41d1b4 ADD	X11, X18, X6,LSL #3

  (221) 0x41d1b8 ADD	X13, X13, #8

  (221) 0x41d1bc UBFM	X4, X4, #60, #59

  (221) 0x41d1c0 ADD	X8, X20, X8,LSL #3

  (221) 0x41d1c4 ADD	X12, X12, #8

  (221) 0x41d1c8 ADD	X7, X19, X7,LSL #3

  (221) 0x41d1cc ADD	X11, X11, #8

  (221) 0x41d1d0 ADD	X6, X18, X6,LSL #3

  (221) 0x41d1d4 ADD	X2, X22, X2,LSL #3

  (221) 0x41d1d8 ADD	X1, X21, X1,LSL #3

  (221) 0x41d1dc ADD	X10, X0, X10,LSL #3

  (221) 0x41d1e0 MOVZ	X0, #0

    (220) 0x41d1e4 LDR	Q31, [X10, X0]

    (220) 0x41d1e8 LDR	Q30, [X2, X0]

    (220) 0x41d1ec LDR	Q1, [X1, X0]

    (220) 0x41d1f0 LDR	Q0, [X7, X0]

    (220) 0x41d1f4 FMUL	V30.2D, V30.2D, V31.2D

    (220) 0x41d1f8 LDR	Q2, [X8, X0]

    (220) 0x41d1fc LDR	Q27, [X6, X0]

    (220) 0x41d200 LDR	Q28, [X13, X0]

    (220) 0x41d204 FMLA	V0.2D, V1.2D, V30.2D

    (220) 0x41d208 LDR	Q26, [X11, X0]

    (220) 0x41d20c FADD	V2.2D, V2.2D, V30.2D

    (220) 0x41d210 LDR	Q29, [X12, X0]

    (220) 0x41d214 FADD	V27.2D, V27.2D, V31.2D

    (220) 0x41d218 FSUB	V28.2D, V2.2D, V28.2D

    (220) 0x41d21c FSUB	V26.2D, V27.2D, V26.2D

    (220) 0x41d220 FSUB	V29.2D, V0.2D, V29.2D

    (220) 0x41d224 FDIV	V26.2D, V28.2D, V26.2D

    (220) 0x41d228 FDIV	V29.2D, V29.2D, V28.2D

    (220) 0x41d22c STR	Q26, [X2, X0]

    (220) 0x41d230 STR	Q29, [X1, X0]

    (220) 0x41d234 ADD	X0, X0, #16

    (220) 0x41d238 CMP	X0, X4

    (220) 0x41d23c B.NE	41d1e4

  (221) 0x41d240 AND	W0, W5, #1951

  (221) 0x41d244 TBZ	W5, #0, 41d300

  (222) 0x41d248 LDR	X6, [SP, #104]

  (222) 0x41d24c ORR	W1, WZR, W0

  (222) 0x41d250 ADD	X17, X17, X3

  (222) 0x41d254 ADD	X16, X16, X3

  (222) 0x41d258 ADD	X15, X15, X3

  (222) 0x41d25c LDR	X4, [SP, #120]

  (222) 0x41d260 ADD	X17, X17, X1

  (222) 0x41d264 ADD	X16, X16, X1

  (222) 0x41d268 ADD	X15, X15, X1

  (222) 0x41d26c ADD	X14, X14, X3

  (222) 0x41d270 ADD	X2, X20, X17,LSL #3

  (222) 0x41d274 SUB	W5, W5, W0

  (222) 0x41d278 ADD	X0, X18, X15,LSL #3

  (222) 0x41d27c WHILELO	P7.D, XZR, X5

  (222) 0x41d280 ADD	X14, X14, X1

  (222) 0x41d284 LD1D	{Z16.D}, P7/Z, [X20, X17,LSL #3]

  (222) 0x41d288 LD1D	{Z25.D}, P7/Z, [X22, X14,LSL #3]

  (222) 0x41d28c LD1D	{Z5.D}, P7/Z, [X19, X16,LSL #3]

  (222) 0x41d290 LD1D	{Z3.D}, P7/Z, [X18, X15,LSL #3]

  (222) 0x41d294 ADD	X2, X2, #8

  (222) 0x41d298 LD1D	{Z7.D}, P7/Z, [X2, MUL VL]

  (222) 0x41d29c ADD	X0, X0, #8

  (222) 0x41d2a0 LD1D	{Z23.D}, P7/Z, [X0, MUL VL]

  (222) 0x41d2a4 ADD	X4, X4, X3

  (222) 0x41d2a8 ADD	X3, X6, X3

  (222) 0x41d2ac ADD	X6, X19, X16,LSL #3

  (222) 0x41d2b0 ADD	X3, X3, X1

  (222) 0x41d2b4 ADD	X4, X4, X1

  (222) 0x41d2b8 LDR	X1, [SP, #112]

  (222) 0x41d2bc LD1D	{Z6.D}, P7/Z, [X21, X3,LSL #3]

  (222) 0x41d2c0 LD1D	{Z24.D}, P7/Z, [X1, X4,LSL #3]

  (222) 0x41d2c4 ADD	X6, X6, #8

  (222) 0x41d2c8 FMUL	Z25.D, P7/M, Z25.D, Z24.D

  (222) 0x41d2cc LD1D	{Z4.D}, P7/Z, [X6, MUL VL]

  (222) 0x41d2d0 MOVPRFX	Z22, Z25

  (222) 0x41d2d4 FADD	Z22.D, P7/M, Z22.D, Z16.D

  (222) 0x41d2d8 FADD	Z24.D, P7/M, Z24.D, Z3.D

  (222) 0x41d2dc FSUB	Z22.D, P7/M, Z22.D, Z7.D

  (222) 0x41d2e0 FMUL	Z25.D, P7/M, Z25.D, Z6.D

  (222) 0x41d2e4 FSUB	Z24.D, P7/M, Z24.D, Z23.D

  (222) 0x41d2e8 FADD	Z25.D, P7/M, Z25.D, Z5.D

  (222) 0x41d2ec FSUB	Z25.D, P7/M, Z25.D, Z4.D

  (222) 0x41d2f0 FDIV	Z25.D, P7/M, Z25.D, Z22.D

  (222) 0x41d2f4 FDIV	Z22.D, P7/M, Z22.D, Z24.D

  (222) 0x41d2f8 ST1D	{Z22.D}, P7, [X22, X14,LSL #3]

  (222) 0x41d2fc ST1D	{Z25.D}, P7, [X21, X3,LSL #3]

  (221) 0x41d300 ORR	W2, WZR, W23

  (218) 0x41d304 LDR	W0, [SP, #128]

  (218) 0x41d308 ADD	X9, X9, #1

  (218) 0x41d30c CMP	W0, W9

  (218) 0x41d310 B.LE	41d33c

  (218) 0x41d314 LDR	W0, [SP, #140]

  (218) 0x41d318 LDR	W1, [SP, #132]

  (218) 0x41d31c SUB	W4, W0, W2

  (218) 0x41d320 LDR	W0, [SP, #136]

  (218) 0x41d324 B	41d120

0x41d328 LDP	X23, X24, [SP, #48]

0x41d32c LDP	X19, X20, [SP, #16]

0x41d330 LDP	X21, X22, [SP, #32]

0x41d334 LDP	X29, X30, [SP], #144

0x41d338 RET

(217) 0x41d33c LDP	X23, X24, [SP, #48]

(217) 0x41d340 LDP	X25, X26, [SP, #64]

(217) 0x41d344 LDP	X27, X28, [SP, #80]

(217) 0x41d348 LDP	X19, X20, [SP, #16]

(217) 0x41d34c LDP	X21, X22, [SP, #32]

(217) 0x41d350 LDP	X29, X30, [SP], #144

(217) 0x41d354 RET

  (219) 0x41d358 MOVZ	W0, #0

  (219) 0x41d35c SBFM	X3, X1, #0, #31

  (219) 0x41d360 B	41d248

0x41d364 ADD	W4, W4, #1

0x41d368 MOVZ	W0, #0

0x41d36c B	41d0d4

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	6.88
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d32c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d328 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41d364 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41d328 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X27, X28, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X26, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X30, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X9, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41d0d4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	6.83	6.50	6.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	6.88
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

5% of peak load performance is reached (5.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W1, W0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W2, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W2, W1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d32c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41d328 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41d364 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41d328 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X27, X28, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X26, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X30, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X9, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W0, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41d0d4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.88	2.99
▼Loop 217 - advec_cell.cpp:117-125 - exec–	0.00	0.00
○Loop 218 - advec_cell.cpp:119-122 - exec	0.00	0.01
▼Loop 221 - advec_cell.cpp:119-125 - exec–	0.00	0.01
○Loop 220 - advec_cell.cpp:120-125 - exec	3.88	2.97
○Loop 219 - context.h:69-69 - exec	0.00	0.00
○Loop 222 - advec_cell.cpp:120-125 - exec	0.00	0.00

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Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code