OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 6.69% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

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40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41c2c0 STP	X29, X30, [SP, #624]!

0x41c2c4 ADD	X29, SP, #0

0x41c2c8 STP	X19, X20, [SP, #16]

0x41c2cc ORR	X20, XZR, X0

0x41c2d0 STP	X21, X22, [SP, #32]

0x41c2d4 LDP	W22, W1, [X0, #96]

0x41c2d8 LDP	W0, W2, [X0, #88]

0x41c2dc ADD	W1, W1, #3

0x41c2e0 ADD	W22, W22, #1

0x41c2e4 ADD	W0, W0, #1

0x41c2e8 STR	W1, [SP, #304]

0x41c2ec STR	W0, [SP, #308]

0x41c2f0 CMP	W22, W1

0x41c2f4 B.GE	41c994

0x41c2f8 ADD	W19, W2, #3

0x41c2fc STP	X23, X24, [SP, #48]

0x41c300 SUB	W23, W1, W22

0x41c304 CMP	W0, W19

0x41c308 B.GE	41c990

0x41c30c SUB	W0, W19, W0

0x41c310 MADD	W23, W23, W0, WZR

0x41c314 STR	W0, [SP, #312]

0x41c318 BL	403aa0

0x41c31c ORR	W21, WZR, W0

0x41c320 BL	403980

0x41c324 UDIV	W4, W23, W21

0x41c328 ORR	W3, WZR, W0

0x41c32c MSUB	W0, W4, W21, W23

0x41c330 CMP	W3, W0

0x41c334 B.CC	41c9cc

0x41c338 MADD	W3, W4, W3, W0

0x41c33c ADD	W0, W4, W3

0x41c340 STR	W0, [SP, #316]

0x41c344 CMP	W3, W0

0x41c348 B.CS	41c990

0x41c34c LDR	W1, [SP, #312]

0x41c350 FMOV	V28.2D, #0.2500000

0x41c354 FDUP	Z30.D, #80

0x41c358 STP	X25, X26, [SP, #64]

0x41c35c STP	X27, X28, [SP, #80]

0x41c360 UDIV	W0, W3, W1

0x41c364 LDP	X2, X5, [X20]

0x41c368 LDR	D29, [X20, #80]

0x41c36c DUP	Z31.D, Z29.D[0]

0x41c370 STR	X2, [SP, #344]

0x41c374 STR	X5, [SP, #376]

0x41c378 LDP	X2, X5, [X20, #16]

0x41c37c MSUB	W1, W0, W1, W3

0x41c380 ADD	W0, W0, W22

0x41c384 SBFM	X25, X0, #0, #31

0x41c388 DUP	V29.2D, V29.D[0]

0x41c38c STP	X5, X2, [SP, #320]

0x41c390 LDP	X0, X2, [X20, #32]

0x41c394 STR	X0, [SP, #352]

0x41c398 LDR	W0, [SP, #308]

0x41c39c STR	X2, [SP, #392]

0x41c3a0 ADD	W1, W1, W0

0x41c3a4 LDP	X0, X5, [X20, #48]

0x41c3a8 SUB	W2, W19, W1

0x41c3ac STR	X0, [SP, #336]

0x41c3b0 STR	X5, [SP, #368]

0x41c3b4 LDP	X0, X5, [X20, #64]

0x41c3b8 STR	X0, [SP, #360]

0x41c3bc STR	X5, [SP, #384]

  (198) 0x41c3c0 CMP	W4, W2

  (198) 0x41c3c4 CSEL	W0, W4, W2, #9

  (198) 0x41c3c8 STR	W0, [SP, #168]

  (198) 0x41c3cc ADD	W0, W3, W0

  (198) 0x41c3d0 STR	W0, [SP, #172]

  (198) 0x41c3d4 CMP	W3, W0

  (198) 0x41c3d8 B.CS	41c96c

  (201) 0x41c3dc LDP	X6, X7, [SP, #320]

  (201) 0x41c3e0 SUB	W4, W25, #1

  (201) 0x41c3e4 SBFM	X4, X4, #0, #31

  (201) 0x41c3e8 LDP	X9, X12, [SP, #352]

  (201) 0x41c3ec LDP	X11, X8, [SP, #336]

  (201) 0x41c3f0 LDP	X14, X10, [SP, #384]

  (201) 0x41c3f4 LDR	X3, [X6]

  (201) 0x41c3f8 LDR	X2, [X7]

  (201) 0x41c3fc LDR	X0, [X8]

  (201) 0x41c400 MADD	X15, X4, X3, XZR

  (201) 0x41c404 LDR	X5, [X9]

  (201) 0x41c408 MADD	X16, X3, X25, XZR

  (201) 0x41c40c MADD	X17, X4, X2, XZR

  (201) 0x41c410 LDR	X3, [X10]

  (201) 0x41c414 MADD	X21, X2, X25, XZR

  (201) 0x41c418 MADD	X23, X4, X0, XZR

  (201) 0x41c41c LDR	X2, [X11]

  (201) 0x41c420 MADD	X26, X0, X25, XZR

  (201) 0x41c424 MADD	X22, X4, X5, XZR

  (201) 0x41c428 LDR	X0, [X12]

  (201) 0x41c42c MADD	X24, X5, X25, XZR

  (201) 0x41c430 LDP	X5, X13, [SP, #368]

  (201) 0x41c434 MADD	X27, X4, X3, XZR

  (201) 0x41c438 MADD	X20, X3, X25, XZR

  (201) 0x41c43c MADD	X2, X25, X2, XZR

  (201) 0x41c440 MADD	X0, X25, X0, XZR

  (201) 0x41c444 LDR	X4, [X5]

  (201) 0x41c448 STR	X2, [SP, #160]

  (201) 0x41c44c STP	X27, X20, [SP, #192]

  (201) 0x41c450 STP	X22, X23, [SP, #232]

  (201) 0x41c454 MADD	X3, X25, X4, XZR

  (201) 0x41c458 STP	X24, X26, [SP, #248]

  (201) 0x41c45c STP	X21, X16, [SP, #272]

  (201) 0x41c460 STP	X17, X15, [SP, #288]

  (201) 0x41c464 LDR	X2, [X13]

  (201) 0x41c468 STR	X0, [SP, #144]

  (201) 0x41c46c LDR	X0, [X14]

  (201) 0x41c470 STR	X3, [SP, #128]

  (201) 0x41c474 LDR	X5, [X5, #16]

  (201) 0x41c478 MADD	X4, X25, X2, XZR

  (201) 0x41c47c LDR	X3, [X6, #16]

  (201) 0x41c480 MADD	X6, X25, X0, XZR

  (201) 0x41c484 LDR	X2, [X7, #16]

  (201) 0x41c488 STR	X4, [SP, #224]

  (201) 0x41c48c LDR	X0, [X8, #16]

  (201) 0x41c490 LDR	X30, [X9, #16]

  (201) 0x41c494 LDR	X7, [X14, #16]

  (201) 0x41c498 STR	X0, [SP, #152]

  (201) 0x41c49c LDR	X9, [X13, #16]

  (201) 0x41c4a0 LDR	X28, [X10, #16]

  (201) 0x41c4a4 STP	X3, X2, [SP, #96]

  (201) 0x41c4a8 ORR	X2, XZR, X6

  (201) 0x41c4ac STP	X7, X5, [SP, #112]

  (201) 0x41c4b0 STP	X6, X9, [SP, #208]

  (201) 0x41c4b4 LDR	X6, [X11, #16]

  (201) 0x41c4b8 LDR	W8, [SP, #168]

  (201) 0x41c4bc ORR	X3, XZR, X6

  (201) 0x41c4c0 LDR	X6, [X12, #16]

  (201) 0x41c4c4 STR	X3, [SP, #264]

  (201) 0x41c4c8 STR	X6, [SP, #136]

  (201) 0x41c4cc CMP	W8, #1

  (201) 0x41c4d0 B.EQ	41c9c0

  (201) 0x41c4d4 SBFM	X1, X1, #0, #31

  (201) 0x41c4d8 UBFM	W5, W8, #1, #31

  (201) 0x41c4dc ADD	X18, X17, X1

  (201) 0x41c4e0 ADD	X17, X16, X1

  (201) 0x41c4e4 ADD	X16, X21, X1

  (201) 0x41c4e8 LDR	X21, [SP, #144]

  (201) 0x41c4ec ADD	X6, X4, X1

  (201) 0x41c4f0 ORR	X4, XZR, X20

  (201) 0x41c4f4 ADD	X19, X15, X1

  (201) 0x41c4f8 ADD	X11, X9, X6,LSL #3

  (201) 0x41c4fc LDR	X20, [SP, #96]

  (201) 0x41c500 UBFM	X19, X19, #61, #60

  (201) 0x41c504 UBFM	X18, X18, #61, #60

  (201) 0x41c508 ADD	X15, X26, X1

  (201) 0x41c50c SUB	X26, X18, #8

  (201) 0x41c510 UBFM	X17, X17, #61, #60

  (201) 0x41c514 LDR	X9, [SP, #160]

  (201) 0x41c518 ADD	X14, X23, X1

  (201) 0x41c51c ADD	X21, X21, X1

  (201) 0x41c520 SUB	X23, X17, #8

  (201) 0x41c524 ADD	X8, X24, X1

  (201) 0x41c528 UBFM	X16, X16, #61, #60

  (201) 0x41c52c STP	X21, X5, [SP, #176]

  (201) 0x41c530 ADD	X5, X4, X1

  (201) 0x41c534 ADD	X4, X27, X1

  (201) 0x41c538 ADD	X13, X30, X8,LSL #3

  (201) 0x41c53c SUB	X27, X19, #8

  (201) 0x41c540 ADD	X19, X20, X19

  (201) 0x41c544 ADD	X10, X28, X5,LSL #3

  (201) 0x41c548 ADD	X27, X20, X27

  (201) 0x41c54c ADD	X24, X9, X1

  (201) 0x41c550 ADD	X9, X28, X4,LSL #3

  (201) 0x41c554 LDR	X20, [SP, #104]

  (201) 0x41c558 ADD	X24, X3, X24,LSL #3

  (201) 0x41c55c ADD	X7, X22, X1

  (201) 0x41c560 SUB	X22, X16, #8

  (201) 0x41c564 ADD	X2, X2, X1

  (201) 0x41c568 ADD	X12, X30, X7,LSL #3

  (201) 0x41c56c ORR	X8, XZR, X13

  (201) 0x41c570 LDR	X3, [SP, #152]

  (201) 0x41c574 ORR	X6, XZR, X11

  (201) 0x41c578 ORR	X5, XZR, X10

  (201) 0x41c57c ORR	X7, XZR, X12

  (201) 0x41c580 ORR	X4, XZR, X9

  (201) 0x41c584 LDR	X21, [SP, #128]

  (201) 0x41c588 MOVZ	X0, #0

  (201) 0x41c58c SUB	X13, X13, #8

  (201) 0x41c590 ADD	X26, X20, X26

  (201) 0x41c594 ADD	X18, X20, X18

  (201) 0x41c598 LDR	X20, [SP, #96]

  (201) 0x41c59c SUB	X12, X12, #8

  (201) 0x41c5a0 SUB	X11, X11, #8

  (201) 0x41c5a4 ADD	X14, X3, X14,LSL #3

  (201) 0x41c5a8 SUB	X10, X10, #8

  (201) 0x41c5ac SUB	X9, X9, #8

  (201) 0x41c5b0 ADD	X15, X3, X15,LSL #3

  (201) 0x41c5b4 LDR	X3, [SP, #136]

  (201) 0x41c5b8 ADD	X21, X21, X1

  (201) 0x41c5bc ADD	X23, X20, X23

  (201) 0x41c5c0 LDR	X20, [SP, #96]

  (201) 0x41c5c4 ADD	X17, X20, X17

  (201) 0x41c5c8 LDR	X20, [SP, #104]

  (201) 0x41c5cc ADD	X22, X20, X22

  (201) 0x41c5d0 ADD	X16, X20, X16

  (201) 0x41c5d4 LDR	X20, [SP, #176]

  (201) 0x41c5d8 ADD	X3, X3, X20,LSL #3

  (201) 0x41c5dc LDR	X20, [SP, #120]

  (201) 0x41c5e0 ADD	X21, X20, X21,LSL #3

  (201) 0x41c5e4 LDR	X20, [SP, #112]

  (201) 0x41c5e8 ADD	X2, X20, X2,LSL #3

  (201) 0x41c5ec LDR	X20, [SP, #184]

  (201) 0x41c5f0 UBFM	X20, X20, #60, #59

  (201) 0x41c5f4 HINT	#0

  (201) 0x41c5f8 HINT	#0

  (201) 0x41c5fc HINT	#0

    (200) 0x41c600 LDR	Q6, [X22, X0]

    (200) 0x41c604 LDR	Q24, [X23, X0]

    (200) 0x41c608 LDR	Q27, [X26, X0]

    (200) 0x41c60c LDR	Q1, [X27, X0]

    (200) 0x41c610 FMUL	V24.2D, V6.2D, V24.2D

    (200) 0x41c614 LDR	Q23, [X16, X0]

    (200) 0x41c618 LDR	Q0, [X17, X0]

    (200) 0x41c61c LDR	Q19, [X18, X0]

    (200) 0x41c620 FMLA	V24.2D, V27.2D, V1.2D

    (200) 0x41c624 LDR	Q2, [X19, X0]

    (200) 0x41c628 LDR	Q22, [X7, X0]

    (200) 0x41c62c FMLA	V24.2D, V23.2D, V0.2D

    (200) 0x41c630 LDR	Q21, [X12, X0]

    (200) 0x41c634 LDR	Q3, [X8, X0]

    (200) 0x41c638 LDR	Q5, [X13, X0]

    (200) 0x41c63c FMLA	V24.2D, V19.2D, V2.2D

    (200) 0x41c640 LDR	Q20, [X14, X0]

    (200) 0x41c644 FSUB	V21.2D, V22.2D, V21.2D

    (200) 0x41c648 LDR	Q18, [X15, X0]

    (200) 0x41c64c FSUB	V5.2D, V3.2D, V5.2D

    (200) 0x41c650 LDR	Q16, [X24, X0]

    (200) 0x41c654 FMUL	V20.2D, V21.2D, V20.2D

    (200) 0x41c658 FMUL	V24.2D, V24.2D, V28.2D

    (200) 0x41c65c FMLA	V20.2D, V5.2D, V18.2D

    (200) 0x41c660 FDIV	V24.2D, V29.2D, V24.2D

    (200) 0x41c664 FMLS	V16.2D, V20.2D, V24.2D

    (200) 0x41c668 STR	Q16, [X3, X0]

    (200) 0x41c66c LDR	Q7, [X13, X0]

    (200) 0x41c670 LDR	Q1, [X12, X0]

    (200) 0x41c674 LDR	Q25, [X8, X0]

    (200) 0x41c678 LDR	Q4, [X7, X0]

    (200) 0x41c67c LDR	Q27, [X11, X0]

    (200) 0x41c680 FSUB	V1.2D, V7.2D, V1.2D

    (200) 0x41c684 LDR	Q17, [X6, X0]

    (200) 0x41c688 FSUB	V4.2D, V25.2D, V4.2D

    (200) 0x41c68c LDR	Q26, [X21, X0]

    (200) 0x41c690 FMUL	V27.2D, V1.2D, V27.2D

    (200) 0x41c694 FMLA	V27.2D, V4.2D, V17.2D

    (200) 0x41c698 FMLS	V26.2D, V27.2D, V24.2D

    (200) 0x41c69c STR	Q26, [X2, X0]

    (200) 0x41c6a0 LDR	Q2, [X4, X0]

    (200) 0x41c6a4 LDR	Q3, [X9, X0]

    (200) 0x41c6a8 LDR	Q0, [X5, X0]

    (200) 0x41c6ac LDR	Q19, [X10, X0]

    (200) 0x41c6b0 LDR	Q5, [X14, X0]

    (200) 0x41c6b4 FSUB	V3.2D, V2.2D, V3.2D

    (200) 0x41c6b8 LDR	Q23, [X15, X0]

    (200) 0x41c6bc FSUB	V19.2D, V0.2D, V19.2D

    (200) 0x41c6c0 LDR	Q6, [X3, X0]

    (200) 0x41c6c4 FMUL	V5.2D, V3.2D, V5.2D

    (200) 0x41c6c8 FMLA	V5.2D, V23.2D, V19.2D

    (200) 0x41c6cc FMLS	V6.2D, V24.2D, V5.2D

    (200) 0x41c6d0 STR	Q6, [X3, X0]

    (200) 0x41c6d4 LDR	Q18, [X2, X0]

    (200) 0x41c6d8 LDR	Q16, [X10, X0]

    (200) 0x41c6dc LDR	Q4, [X9, X0]

    (200) 0x41c6e0 LDR	Q21, [X5, X0]

    (200) 0x41c6e4 LDR	Q20, [X4, X0]

    (200) 0x41c6e8 LDR	Q17, [X11, X0]

    (200) 0x41c6ec FSUB	V4.2D, V16.2D, V4.2D

    (200) 0x41c6f0 LDR	Q22, [X6, X0]

    (200) 0x41c6f4 FSUB	V20.2D, V21.2D, V20.2D

    (200) 0x41c6f8 FMUL	V17.2D, V4.2D, V17.2D

    (200) 0x41c6fc FMLA	V17.2D, V22.2D, V20.2D

    (200) 0x41c700 FMLS	V18.2D, V24.2D, V17.2D

    (200) 0x41c704 STR	Q18, [X2, X0]

    (200) 0x41c708 ADD	X0, X0, #16

    (200) 0x41c70c CMP	X0, X20

    (200) 0x41c710 B.NE	41c600

  (201) 0x41c714 LDR	W0, [SP, #168]

  (201) 0x41c718 AND	W6, W0, #1951

  (201) 0x41c71c TBZ	W0, #0, 41c968

  (202) 0x41c720 LDP	X0, X2, [SP, #288]

  (202) 0x41c724 LDP	X24, X23, [SP, #96]

  (202) 0x41c728 ADD	X8, X2, X1

  (202) 0x41c72c ADD	X3, X0, X1

  (202) 0x41c730 LDR	X2, [SP, #248]

  (202) 0x41c734 LDR	X0, [SP, #280]

  (202) 0x41c738 LDR	W13, [SP, #168]

  (202) 0x41c73c ADD	X12, X2, X1

  (202) 0x41c740 LDR	X2, [SP, #232]

  (202) 0x41c744 ADD	X4, X0, X1

  (202) 0x41c748 LDR	X0, [SP, #272]

  (202) 0x41c74c ADD	X11, X2, X1

  (202) 0x41c750 LDP	X26, X2, [SP, #216]

  (202) 0x41c754 ADD	X5, X0, X1

  (202) 0x41c758 ORR	W0, WZR, W6

  (202) 0x41c75c SUB	W6, W13, W6

  (202) 0x41c760 WHILELO	P7.D, XZR, X6

  (202) 0x41c764 LDP	X13, X20, [SP, #256]

  (202) 0x41c768 ADD	X4, X4, X0

  (202) 0x41c76c UBFM	X4, X4, #61, #60

  (202) 0x41c770 ADD	X3, X3, X0

  (202) 0x41c774 ADD	X9, X2, X1

  (202) 0x41c778 ADD	X5, X5, X0

  (202) 0x41c77c ADD	X8, X8, X0

  (202) 0x41c780 UBFM	X3, X3, #61, #60

  (202) 0x41c784 LDR	X2, [SP, #200]

  (202) 0x41c788 UBFM	X5, X5, #61, #60

  (202) 0x41c78c UBFM	X8, X8, #61, #60

  (202) 0x41c790 ADD	X17, X13, X1

  (202) 0x41c794 SUB	X21, X3, #8

  (202) 0x41c798 LDR	X6, [SP, #240]

  (202) 0x41c79c ADD	X12, X12, X0

  (202) 0x41c7a0 ADD	X11, X11, X0

  (202) 0x41c7a4 LD1D	{Z6.D}, P7/Z, [X30, X12,LSL #3]

  (202) 0x41c7a8 LD1D	{Z4.D}, P7/Z, [X30, X11,LSL #3]

  (202) 0x41c7ac ADD	X9, X9, X0

  (202) 0x41c7b0 ADD	X17, X17, X0

  (202) 0x41c7b4 ADD	X18, X30, X12,LSL #3

  (202) 0x41c7b8 ADD	X3, X23, X3

  (202) 0x41c7bc ADD	X21, X23, X21

  (202) 0x41c7c0 LD1D	{Z3.D}, P7/Z, [X3, MUL VL]

  (202) 0x41c7c4 LD1D	{Z1.D}, P7/Z, [X21, MUL VL]

  (202) 0x41c7c8 ADD	X19, X30, X11,LSL #3

  (202) 0x41c7cc ADD	X7, X2, X1

  (202) 0x41c7d0 LDR	X2, [SP, #192]

  (202) 0x41c7d4 ADD	X13, X26, X9,LSL #3

  (202) 0x41c7d8 ADD	X3, X24, X8

  (202) 0x41c7dc ADD	X7, X7, X0

  (202) 0x41c7e0 SUB	X18, X18, #8

  (202) 0x41c7e4 ADD	X16, X6, X1

  (202) 0x41c7e8 LDP	X22, X6, [SP, #152]

  (202) 0x41c7ec LD1D	{Z23.D}, P7/Z, [X22, X17,LSL #3]

  (202) 0x41c7f0 SUB	X19, X19, #8

  (202) 0x41c7f4 ADD	X16, X16, X0

  (202) 0x41c7f8 LD1D	{Z21.D}, P7/Z, [X22, X16,LSL #3]

  (202) 0x41c7fc SUB	X13, X13, #8

  (202) 0x41c800 ADD	X10, X2, X1

  (202) 0x41c804 LDP	X15, X2, [SP, #136]

  (202) 0x41c808 ADD	X10, X10, X0

  (202) 0x41c80c ADD	X14, X6, X1

  (202) 0x41c810 ADD	X14, X14, X0

  (202) 0x41c814 LD1D	{Z5.D}, P7/Z, [X20, X14,LSL #3]

  (202) 0x41c818 SUB	X20, X4, #8

  (202) 0x41c81c LDR	X6, [SP, #208]

  (202) 0x41c820 ADD	X20, X24, X20

  (202) 0x41c824 ADD	X4, X24, X4

  (202) 0x41c828 LD1D	{Z27.D}, P7/Z, [X20, MUL VL]

  (202) 0x41c82c LD1D	{Z25.D}, P7/Z, [X4, MUL VL]

  (202) 0x41c830 ADD	X2, X2, X1

  (202) 0x41c834 SUB	X20, X5, #8

  (202) 0x41c838 ADD	X14, X28, X10,LSL #3

  (202) 0x41c83c ADD	X2, X2, X0

  (202) 0x41c840 SUB	X4, X8, #8

  (202) 0x41c844 ADD	X2, X15, X2,LSL #3

  (202) 0x41c848 LDR	X15, [SP, #128]

  (202) 0x41c84c ADD	X20, X23, X20

  (202) 0x41c850 ADD	X4, X24, X4

  (202) 0x41c854 LD1D	{Z0.D}, P7/Z, [X20, MUL VL]

  (202) 0x41c858 LD1D	{Z7.D}, P7/Z, [X4, MUL VL]

  (202) 0x41c85c LD1D	{Z2.D}, P7/Z, [X3, MUL VL]

  (202) 0x41c860 LD1D	{Z16.D}, P7/Z, [X18, MUL VL]

  (202) 0x41c864 LD1D	{Z20.D}, P7/Z, [X19, MUL VL]

  (202) 0x41c868 FSUB	Z6.D, P7/M, Z6.D, Z16.D

  (202) 0x41c86c ADD	X6, X6, X1

  (202) 0x41c870 FSUB	Z4.D, P7/M, Z4.D, Z20.D

  (202) 0x41c874 FMUL	Z7.D, P7/M, Z7.D, Z1.D

  (202) 0x41c878 FMUL	Z23.D, P7/M, Z23.D, Z6.D

  (202) 0x41c87c FMLA	Z7.D, P7/M, Z27.D, Z0.D

  (202) 0x41c880 ADD	X6, X6, X0

  (202) 0x41c884 FMLA	Z23.D, P7/M, Z21.D, Z4.D

  (202) 0x41c888 ADD	X3, X23, X5

  (202) 0x41c88c LD1D	{Z19.D}, P7/Z, [X3, MUL VL]

  (202) 0x41c890 FMLA	Z7.D, P7/M, Z25.D, Z19.D

  (202) 0x41c894 FMLA	Z7.D, P7/M, Z2.D, Z3.D

  (202) 0x41c898 FMUL	Z7.D, P7/M, Z7.D, Z30.D

  (202) 0x41c89c MOVPRFX	Z26, Z31

  (202) 0x41c8a0 FDIV	Z26.D, P7/M, Z26.D, Z7.D

  (202) 0x41c8a4 FMLS	Z5.D, P7/M, Z26.D, Z23.D

  (202) 0x41c8a8 ST1D	{Z5.D}, P7, [X2, MUL VL]

  (202) 0x41c8ac ADD	X1, X15, X1

  (202) 0x41c8b0 ADD	X15, X28, X7,LSL #3

  (202) 0x41c8b4 LD1D	{Z0.D}, P7/Z, [X30, X11,LSL #3]

  (202) 0x41c8b8 LD1D	{Z27.D}, P7/Z, [X19, MUL VL]

  (202) 0x41c8bc LD1D	{Z1.D}, P7/Z, [X30, X12,LSL #3]

  (202) 0x41c8c0 ADD	X1, X1, X0

  (202) 0x41c8c4 LDR	X0, [SP, #112]

  (202) 0x41c8c8 LD1D	{Z25.D}, P7/Z, [X13, MUL VL]

  (202) 0x41c8cc FSUB	Z1.D, P7/M, Z1.D, Z0.D

  (202) 0x41c8d0 LD1D	{Z18.D}, P7/Z, [X26, X9,LSL #3]

  (202) 0x41c8d4 LD1D	{Z19.D}, P7/Z, [X18, MUL VL]

  (202) 0x41c8d8 SUB	X14, X14, #8

  (202) 0x41c8dc SUB	X15, X15, #8

  (202) 0x41c8e0 FMUL	Z18.D, P7/M, Z18.D, Z1.D

  (202) 0x41c8e4 FSUB	Z19.D, P7/M, Z19.D, Z27.D

  (202) 0x41c8e8 FMLA	Z18.D, P7/M, Z25.D, Z19.D

  (202) 0x41c8ec ADD	X6, X0, X6,LSL #3

  (202) 0x41c8f0 LDR	X0, [SP, #120]

  (202) 0x41c8f4 LD1D	{Z17.D}, P7/Z, [X0, X1,LSL #3]

  (202) 0x41c8f8 FMLS	Z17.D, P7/M, Z26.D, Z18.D

  (202) 0x41c8fc ST1D	{Z17.D}, P7, [X6, MUL VL]

  (202) 0x41c900 LD1D	{Z7.D}, P7/Z, [X28, X7,LSL #3]

  (202) 0x41c904 LD1D	{Z16.D}, P7/Z, [X15, MUL VL]

  (202) 0x41c908 LD1D	{Z3.D}, P7/Z, [X22, X17,LSL #3]

  (202) 0x41c90c LD1D	{Z4.D}, P7/Z, [X28, X10,LSL #3]

  (202) 0x41c910 LD1D	{Z2.D}, P7/Z, [X2, MUL VL]

  (202) 0x41c914 LD1D	{Z6.D}, P7/Z, [X22, X16,LSL #3]

  (202) 0x41c918 LD1D	{Z5.D}, P7/Z, [X14, MUL VL]

  (202) 0x41c91c FSUB	Z7.D, P7/M, Z7.D, Z16.D

  (202) 0x41c920 FSUB	Z4.D, P7/M, Z4.D, Z5.D

  (202) 0x41c924 FMUL	Z3.D, P7/M, Z3.D, Z7.D

  (202) 0x41c928 FMLA	Z3.D, P7/M, Z6.D, Z4.D

  (202) 0x41c92c FMLS	Z2.D, P7/M, Z26.D, Z3.D

  (202) 0x41c930 ST1D	{Z2.D}, P7, [X2, MUL VL]

  (202) 0x41c934 LD1D	{Z0.D}, P7/Z, [X28, X7,LSL #3]

  (202) 0x41c938 LD1D	{Z1.D}, P7/Z, [X28, X10,LSL #3]

  (202) 0x41c93c LD1D	{Z23.D}, P7/Z, [X26, X9,LSL #3]

  (202) 0x41c940 LD1D	{Z27.D}, P7/Z, [X15, MUL VL]

  (202) 0x41c944 LD1D	{Z20.D}, P7/Z, [X14, MUL VL]

  (202) 0x41c948 FSUB	Z0.D, P7/M, Z0.D, Z1.D

  (202) 0x41c94c LD1D	{Z25.D}, P7/Z, [X13, MUL VL]

  (202) 0x41c950 FMUL	Z23.D, P7/M, Z23.D, Z0.D

  (202) 0x41c954 LD1D	{Z21.D}, P7/Z, [X6, MUL VL]

  (202) 0x41c958 FSUB	Z27.D, P7/M, Z27.D, Z20.D

  (202) 0x41c95c FMLA	Z23.D, P7/M, Z25.D, Z27.D

  (202) 0x41c960 FMLS	Z21.D, P7/M, Z26.D, Z23.D

  (202) 0x41c964 ST1D	{Z21.D}, P7, [X6, MUL VL]

  (201) 0x41c968 LDR	W3, [SP, #172]

  (198) 0x41c96c ADD	X25, X25, #1

  (198) 0x41c970 LDR	W0, [SP, #304]

  (198) 0x41c974 CMP	W0, W25

  (198) 0x41c978 B.LE	41c9a4

  (198) 0x41c97c LDR	W0, [SP, #316]

  (198) 0x41c980 LDR	W1, [SP, #308]

  (198) 0x41c984 LDR	W2, [SP, #312]

  (198) 0x41c988 SUB	W4, W0, W3

  (198) 0x41c98c B	41c3c0

0x41c990 LDP	X23, X24, [SP, #48]

0x41c994 LDP	X19, X20, [SP, #16]

0x41c998 LDP	X21, X22, [SP, #32]

0x41c99c LDP	X29, X30, [SP], #400

0x41c9a0 RET

(197) 0x41c9a4 LDP	X23, X24, [SP, #48]

(197) 0x41c9a8 LDP	X25, X26, [SP, #64]

(197) 0x41c9ac LDP	X27, X28, [SP, #80]

(197) 0x41c9b0 LDP	X19, X20, [SP, #16]

(197) 0x41c9b4 LDP	X21, X22, [SP, #32]

(197) 0x41c9b8 LDP	X29, X30, [SP], #400

(197) 0x41c9bc RET

  (199) 0x41c9c0 MOVZ	W6, #0

  (199) 0x41c9c4 SBFM	X1, X1, #0, #31

  (199) 0x41c9c8 B	41c720

0x41c9cc ADD	W4, W4, #1

0x41c9d0 MOVZ	W0, #0

0x41c9d4 B	41c338

0x41c9d8 HINT	#0

0x41c9dc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	accelerate(global_variables&)	accelerate.cpp:66	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 176 bytes. The binary function is storing 192 bytes.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	1.00	1.00	1.00	1.00	11.17	10.83	11.00	9.50	9.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	1.00	1.00	1.00	1.00	11.17	10.83	11.00	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	9.00
Overall L1	11.17-25.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	22%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

7% of peak load performance is reached (7.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #624]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W1, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W0, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41c994 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41c990 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41c9cc <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x70c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W4, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #316]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41c990 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V28.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X2, X5, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D29, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z31.D, Z29.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X2, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X5, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
DUP V29.2D, V29.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP X5, X2, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X0, X2, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W0, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X0, X5, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W2, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #400	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41c338 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 55% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 176 bytes. The binary function is storing 192 bytes.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	1.00	1.00	1.00	1.00	11.17	10.83	11.00	9.50	9.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	1.00	1.00	1.00	1.00	11.17	10.83	11.00	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	9.00
Overall L1	11.17-25.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	22%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

7% of peak load performance is reached (7.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #624]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W1, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W0, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41c994 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 41c990 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 41c9cc <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x70c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W4, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #316]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 41c990 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V28.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X2, X5, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D29, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z31.D, Z29.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X2, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X5, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
DUP V29.2D, V29.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP X5, X2, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X0, X2, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W0, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X0, X5, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W2, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #400	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 41c338 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.69	5.16
▼Loop 197 - accelerate.cpp:40-53 - exec–	0.00	0.00
▼Loop 201 - accelerate.cpp:42-53 - exec–	0.01	0.01
○Loop 200 - accelerate.cpp:43-53 - exec	6.68	5.12
○Loop 202 - accelerate.cpp:43-53 - exec	0.00	0.01
○Loop 198 - accelerate.cpp:42-48 - exec	0.00	0.01
○Loop 199 - context.h:69-69 - exec	0.00	0.00

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Vectorization ratios

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ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code