OV - exec - Function revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ...	Module: exec	Source: revert.cpp:34-38 [...]	Coverage (incl. loops): 2.19% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42aea0 STP	X29, X30, [SP, #944]!

0x42aea4 ADD	X29, SP, #0

0x42aea8 STP	X19, X20, [SP, #16]

0x42aeac STP	X21, X22, [SP, #32]

0x42aeb0 STP	X25, X26, [SP, #64]

0x42aeb4 LDP	W25, W19, [X0, #40]

0x42aeb8 LDP	W20, W22, [X0, #32]

0x42aebc ADD	W25, W25, #1

0x42aec0 ADD	W19, W19, #2

0x42aec4 CMP	W25, W19

0x42aec8 B.GE	42b044

0x42aecc ADD	W20, W20, #1

0x42aed0 ADD	W22, W22, #2

0x42aed4 SUB	W26, W19, W25

0x42aed8 CMP	W20, W22

0x42aedc B.GE	42b044

0x42aee0 SUB	W21, W22, W20

0x42aee4 STP	X23, X24, [SP, #48]

0x42aee8 ORR	X23, XZR, X0

0x42aeec MADD	W26, W26, W21, WZR

0x42aef0 BL	403aa0

0x42aef4 ORR	W24, WZR, W0

0x42aef8 BL	403980

0x42aefc UDIV	W1, W26, W24

0x42af00 ORR	W2, WZR, W0

0x42af04 MSUB	W0, W1, W24, W26

0x42af08 CMP	W2, W0

0x42af0c B.CC	42b064

0x42af10 MADD	W2, W1, W2, W0

0x42af14 ADD	W18, W1, W2

0x42af18 CMP	W2, W18

0x42af1c B.CS	42b040

0x42af20 UDIV	W0, W2, W21

0x42af24 LDP	X16, X17, [X23]

0x42af28 LDP	X14, X15, [X23, #16]

0x42af2c MSUB	W3, W0, W21, W2

0x42af30 ADD	W0, W0, W25

0x42af34 SBFM	X7, X0, #0, #31

0x42af38 ADD	W3, W3, W20

0x42af3c SUB	W0, W22, W3

  (508) 0x42af40 CMP	W1, W0

  (508) 0x42af44 CSEL	W1, W1, W0, #9

  (508) 0x42af48 ADD	W13, W2, W1

  (508) 0x42af4c CMP	W2, W13

  (508) 0x42af50 B.CS	42b024

  (511) 0x42af54 LDR	X10, [X14]

  (511) 0x42af58 LDR	X8, [X15]

  (511) 0x42af5c LDR	X23, [X16]

  (511) 0x42af60 MADD	X10, X7, X10, XZR

  (511) 0x42af64 LDR	X9, [X17]

  (511) 0x42af68 MADD	X8, X7, X8, XZR

  (511) 0x42af6c LDR	X30, [X14, #16]

  (511) 0x42af70 MADD	X23, X7, X23, XZR

  (511) 0x42af74 LDR	X11, [X15, #16]

  (511) 0x42af78 MADD	X9, X7, X9, XZR

  (511) 0x42af7c LDR	X22, [X16, #16]

  (511) 0x42af80 LDR	X12, [X17, #16]

  (511) 0x42af84 CMP	W1, #1

  (511) 0x42af88 B.EQ	42b058

  (511) 0x42af8c SBFM	X3, X3, #0, #31

  (511) 0x42af90 UBFM	W2, W1, #1, #31

  (511) 0x42af94 ADD	X24, X23, X3

  (511) 0x42af98 ADD	X6, X9, X3

  (511) 0x42af9c ADD	X5, X10, X3

  (511) 0x42afa0 ADD	X4, X8, X3

  (511) 0x42afa4 ADD	X24, X22, X24,LSL #3

  (511) 0x42afa8 ADD	X6, X12, X6,LSL #3

  (511) 0x42afac MOVZ	X0, #0

  (511) 0x42afb0 UBFM	X2, X2, #60, #59

  (511) 0x42afb4 ADD	X5, X30, X5,LSL #3

  (511) 0x42afb8 ADD	X4, X11, X4,LSL #3

  (511) 0x42afbc HINT	#0

    (510) 0x42afc0 LDR	Q31, [X24, X0]

    (510) 0x42afc4 STR	Q31, [X6, X0]

    (510) 0x42afc8 LDR	Q31, [X5, X0]

    (510) 0x42afcc STR	Q31, [X4, X0]

    (510) 0x42afd0 ADD	X0, X0, #16

    (510) 0x42afd4 CMP	X0, X2

    (510) 0x42afd8 B.NE	42afc0

  (511) 0x42afdc AND	W2, W1, #1951

  (511) 0x42afe0 TBZ	W1, #0, 42b020

  (512) 0x42afe4 ORR	W0, WZR, W2

  (512) 0x42afe8 ADD	X23, X23, X3

  (512) 0x42afec ADD	X9, X9, X3

  (512) 0x42aff0 ADD	X10, X10, X3

  (512) 0x42aff4 ADD	X8, X8, X3

  (512) 0x42aff8 SUB	W1, W1, W2

  (512) 0x42affc WHILELO	P7.D, XZR, X1

  (512) 0x42b000 ADD	X23, X23, X0

  (512) 0x42b004 ADD	X9, X9, X0

  (512) 0x42b008 LD1D	{Z30.D}, P7/Z, [X22, X23,LSL #3]

  (512) 0x42b00c ST1D	{Z30.D}, P7, [X12, X9,LSL #3]

  (512) 0x42b010 ADD	X10, X10, X0

  (512) 0x42b014 ADD	X8, X8, X0

  (512) 0x42b018 LD1D	{Z31.D}, P7/Z, [X30, X10,LSL #3]

  (512) 0x42b01c ST1D	{Z31.D}, P7, [X11, X8,LSL #3]

  (511) 0x42b020 ORR	W2, WZR, W13

  (508) 0x42b024 ADD	X7, X7, #1

  (508) 0x42b028 CMP	W19, W7

  (508) 0x42b02c B.LE	42b040

  (508) 0x42b030 SUB	W1, W18, W2

  (508) 0x42b034 ORR	W0, WZR, W21

  (508) 0x42b038 ORR	W3, WZR, W20

  (508) 0x42b03c B	42af40

(507) 0x42b040 LDP	X23, X24, [SP, #48]

(507) 0x42b044 LDP	X19, X20, [SP, #16]

(507) 0x42b048 LDP	X21, X22, [SP, #32]

(507) 0x42b04c LDP	X25, X26, [SP, #64]

(507) 0x42b050 LDP	X29, X30, [SP], #80

(507) 0x42b054 RET

  (509) 0x42b058 MOVZ	W2, #0

  (509) 0x42b05c SBFM	X3, X3, #0, #31

  (509) 0x42b060 B	42afe4

0x42b064 ADD	W1, W1, #1

0x42b068 MOVZ	W0, #0

0x42b06c B	42af10

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	revert(global_variables&)	revert.cpp:48	exec
○	PdV(global_variables&, bool)	PdV.cpp:131	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50
cycles	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	5.38
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42aea0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W22, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42b044 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42b044 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W1, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 42b064 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W18, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 42b040 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X16, X17, [X23]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X14, X15, [X23, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W3, W0, W21, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X7, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W3, W3, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W22, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 42af10 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50
cycles	3.50	3.50	4.83	4.83	4.83	4.83	6.00	4.67	0.00	0.00	0.00	0.00	3.17	2.83	3.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	5.38
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42aea0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W25, W19, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W20, W22, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42b044 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W26, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W20, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42b044 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W26, W26, W21, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W24, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W26, W24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W1, W24, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 42b064 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W18, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 42b040 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X16, X17, [X23]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X14, X15, [X23, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W3, W0, W21, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X7, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
ADD W3, W3, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W22, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 42af10 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.19	1.69
▼Loop 507 - revert.cpp:34-38 - exec–	0.00	0.00
○Loop 508 - revert.cpp:36-38 - exec	0.00	0.01
▼Loop 511 - revert.cpp:36-38 - exec–	0.00	0.00
○Loop 510 - revert.cpp:37-38 - exec	2.19	1.68
○Loop 509 - context.h:69-69 - exec	0.00	0.00
○Loop 512 - revert.cpp:37-38 - exec	0.00	0.00

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ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code