OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 7.87% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

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69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x429d50 STP	X29, X30, [SP, #528]!

0x429d54 ADD	X29, SP, #0

0x429d58 STP	X19, X20, [SP, #16]

0x429d5c ORR	X20, XZR, X0

0x429d60 STP	X21, X22, [SP, #32]

0x429d64 LDP	W22, W1, [X0, #120]

0x429d68 LDP	W0, W2, [X0, #112]

0x429d6c ADD	W1, W1, #2

0x429d70 ADD	W22, W22, #1

0x429d74 ADD	W0, W0, #1

0x429d78 STR	W1, [SP, #376]

0x429d7c STR	W0, [SP, #380]

0x429d80 CMP	W22, W1

0x429d84 B.GE	42a4bc

0x429d88 ADD	W19, W2, #2

0x429d8c STP	X23, X24, [SP, #48]

0x429d90 SUB	W23, W1, W22

0x429d94 CMP	W0, W19

0x429d98 B.GE	42a4b8

0x429d9c SUB	W0, W19, W0

0x429da0 MADD	W23, W23, W0, WZR

0x429da4 STR	W0, [SP, #384]

0x429da8 BL	403aa0

0x429dac ORR	W21, WZR, W0

0x429db0 BL	403980

0x429db4 UDIV	W4, W23, W21

0x429db8 ORR	W3, WZR, W0

0x429dbc MSUB	W0, W4, W21, W23

0x429dc0 CMP	W3, W0

0x429dc4 B.CC	42a4f4

0x429dc8 MADD	W3, W4, W3, W0

0x429dcc ADD	W0, W4, W3

0x429dd0 STR	W0, [SP, #388]

0x429dd4 CMP	W3, W0

0x429dd8 B.CS	42a4b8

0x429ddc LDR	W1, [SP, #384]

0x429de0 FMOV	V27.2D, #0.2500000

0x429de4 FMOV	V26.2D, #1.0000000

0x429de8 FDUP	Z30.D, #80

0x429dec FDUP	Z29.D, #112

0x429df0 STP	X25, X26, [SP, #64]

0x429df4 STP	X27, X28, [SP, #80]

0x429df8 UDIV	W0, W3, W1

0x429dfc LDP	X2, X5, [X20, #8]

0x429e00 LDR	D28, [X20]

0x429e04 DUP	Z31.D, Z28.D[0]

0x429e08 STR	X2, [SP, #392]

0x429e0c STR	X5, [SP, #416]

0x429e10 LDP	X2, X5, [X20, #24]

0x429e14 MSUB	W1, W0, W1, W3

0x429e18 ADD	W0, W0, W22

0x429e1c SBFM	X21, X0, #0, #31

0x429e20 DUP	V28.2D, V28.D[0]

0x429e24 STR	X2, [SP, #440]

0x429e28 STR	X5, [SP, #456]

0x429e2c LDP	X0, X2, [X20, #40]

0x429e30 STR	X0, [SP, #488]

0x429e34 LDR	W0, [SP, #380]

0x429e38 STR	X2, [SP, #472]

0x429e3c ADD	W1, W1, W0

0x429e40 LDP	X0, X5, [X20, #56]

0x429e44 SUB	W2, W19, W1

0x429e48 ORR	X19, XZR, X21

0x429e4c STR	X5, [SP, #448]

0x429e50 STR	X0, [SP, #480]

0x429e54 LDP	X0, X5, [X20, #72]

0x429e58 STR	X5, [SP, #400]

0x429e5c STR	X0, [SP, #464]

0x429e60 LDP	X0, X5, [X20, #88]

0x429e64 STR	X0, [SP, #408]

0x429e68 LDR	X0, [X20, #104]

0x429e6c STP	X5, X0, [SP, #424]

  (483) 0x429e70 CMP	W4, W2

  (483) 0x429e74 CSEL	W0, W4, W2, #9

  (483) 0x429e78 STR	W0, [SP, #272]

  (483) 0x429e7c ADD	W0, W3, W0

  (483) 0x429e80 STR	W0, [SP, #276]

  (483) 0x429e84 CMP	W3, W0

  (483) 0x429e88 B.CS	42a494

  (486) 0x429e8c LDP	X13, X9, [SP, #392]

  (486) 0x429e90 LDP	X10, X11, [SP, #408]

  (486) 0x429e94 LDP	X12, X15, [SP, #424]

  (486) 0x429e98 LDP	X18, X20, [SP, #440]

  (486) 0x429e9c LDR	X4, [X9]

  (486) 0x429ea0 LDR	X5, [X10]

  (486) 0x429ea4 LDR	X2, [X12]

  (486) 0x429ea8 MADD	X6, X4, X19, XZR

  (486) 0x429eac LDR	X0, [X15]

  (486) 0x429eb0 MADD	X7, X5, X19, XZR

  (486) 0x429eb4 LDR	X3, [X11]

  (486) 0x429eb8 ADD	X25, X4, X6

  (486) 0x429ebc MADD	X17, X2, X19, XZR

  (486) 0x429ec0 LDR	X4, [X13]

  (486) 0x429ec4 ADD	X26, X5, X7

  (486) 0x429ec8 MADD	X8, X0, X19, XZR

  (486) 0x429ecc LDR	X21, [SP, #456]

  (486) 0x429ed0 ADD	X27, X2, X17

  (486) 0x429ed4 MADD	X16, X3, X19, XZR

  (486) 0x429ed8 LDR	X5, [X18]

  (486) 0x429edc ADD	X0, X0, X8

  (486) 0x429ee0 MADD	X28, X19, X4, XZR

  (486) 0x429ee4 ORR	X4, XZR, X8

  (486) 0x429ee8 ADD	X3, X3, X16

  (486) 0x429eec LDR	X2, [X21]

  (486) 0x429ef0 STP	X27, X8, [SP, #296]

  (486) 0x429ef4 MADD	X5, X19, X5, XZR

  (486) 0x429ef8 LDP	X8, X22, [SP, #464]

  (486) 0x429efc MADD	X2, X19, X2, XZR

  (486) 0x429f00 STP	X5, X0, [SP, #240]

  (486) 0x429f04 STR	X3, [SP, #256]

  (486) 0x429f08 STP	X17, X16, [SP, #312]

  (486) 0x429f0c STP	X26, X7, [SP, #328]

  (486) 0x429f10 STP	X25, X6, [SP, #344]

  (486) 0x429f14 LDR	X3, [X20]

  (486) 0x429f18 STR	X2, [SP, #208]

  (486) 0x429f1c LDR	X0, [X8]

  (486) 0x429f20 STR	X28, [SP, #368]

  (486) 0x429f24 LDR	X8, [X8, #16]

  (486) 0x429f28 MADD	X14, X19, X3, XZR

  (486) 0x429f2c MADD	X24, X19, X0, XZR

  (486) 0x429f30 STR	X14, [SP, #224]

  (486) 0x429f34 STR	X24, [SP, #192]

  (486) 0x429f38 LDR	X14, [X12, #16]

  (486) 0x429f3c LDP	X23, X24, [SP, #480]

  (486) 0x429f40 LDR	X5, [X13, #16]

  (486) 0x429f44 LDR	X2, [X23]

  (486) 0x429f48 LDR	X0, [X24]

  (486) 0x429f4c STR	X5, [SP, #360]

  (486) 0x429f50 LDR	X15, [X15, #16]

  (486) 0x429f54 MADD	X13, X19, X2, XZR

  (486) 0x429f58 LDR	X2, [X9, #16]

  (486) 0x429f5c MADD	X9, X19, X0, XZR

  (486) 0x429f60 LDR	X3, [X22]

  (486) 0x429f64 STR	X13, [SP, #160]

  (486) 0x429f68 LDR	X12, [X21, #16]

  (486) 0x429f6c STR	X9, [SP, #176]

  (486) 0x429f70 LDR	X0, [X11, #16]

  (486) 0x429f74 MADD	X30, X19, X3, XZR

  (486) 0x429f78 LDR	X11, [X20, #16]

  (486) 0x429f7c STP	X15, X14, [SP, #104]

  (486) 0x429f80 STP	X2, X8, [SP, #128]

  (486) 0x429f84 LDR	X13, [X10, #16]

  (486) 0x429f88 STR	X30, [SP, #144]

  (486) 0x429f8c LDR	X10, [X18, #16]

  (486) 0x429f90 STR	X12, [SP, #200]

  (486) 0x429f94 LDR	X18, [X22, #16]

  (486) 0x429f98 STR	X13, [SP, #120]

  (486) 0x429f9c LDR	X20, [X23, #16]

  (486) 0x429fa0 STR	X11, [SP, #216]

  (486) 0x429fa4 LDR	X21, [X24, #16]

  (486) 0x429fa8 STR	X18, [SP, #152]

  (486) 0x429fac LDR	W22, [SP, #272]

  (486) 0x429fb0 STR	X20, [SP, #168]

  (486) 0x429fb4 STR	X10, [SP, #232]

  (486) 0x429fb8 STR	X21, [SP, #184]

  (486) 0x429fbc STR	X0, [SP, #264]

  (486) 0x429fc0 CMP	W22, #1

  (486) 0x429fc4 B.EQ	42a4e8

  (486) 0x429fc8 SBFM	X1, X1, #0, #31

  (486) 0x429fcc ORR	X0, XZR, X5

  (486) 0x429fd0 ADD	X9, X7, X1

  (486) 0x429fd4 ADD	X8, X26, X1

  (486) 0x429fd8 ADD	X10, X25, X1

  (486) 0x429fdc ADD	X26, X13, X9,LSL #3

  (486) 0x429fe0 ADD	X12, X28, X1

  (486) 0x429fe4 ADD	X25, X13, X8,LSL #3

  (486) 0x429fe8 LDR	X13, [SP, #160]

  (486) 0x429fec ADD	X7, X17, X1

  (486) 0x429ff0 ADD	X11, X6, X1

  (486) 0x429ff4 ADD	X30, X5, X12,LSL #3

  (486) 0x429ff8 ADD	X5, X27, X1

  (486) 0x429ffc ADD	X6, X4, X1

  (486) 0x42a000 ADD	X24, X14, X7,LSL #3

  (486) 0x42a004 UBFM	W3, W22, #1, #31

  (486) 0x42a008 ADD	X20, X16, X1

  (486) 0x42a00c LDP	X4, X16, [SP, #248]

  (486) 0x42a010 ADD	X22, X14, X5,LSL #3

  (486) 0x42a014 ORR	X21, XZR, X15

  (486) 0x42a018 ADD	X30, X30, #8

  (486) 0x42a01c ADD	X12, X0, X12,LSL #3

  (486) 0x42a020 ADD	X26, X26, #8

  (486) 0x42a024 ADD	X25, X25, #8

  (486) 0x42a028 ADD	X14, X13, X1

  (486) 0x42a02c ADD	X28, X2, X11,LSL #3

  (486) 0x42a030 ADD	X24, X24, #8

  (486) 0x42a034 LDR	X13, [SP, #176]

  (486) 0x42a038 ADD	X27, X2, X10,LSL #3

  (486) 0x42a03c ADD	X22, X22, #8

  (486) 0x42a040 UBFM	X3, X3, #60, #59

  (486) 0x42a044 ADD	X17, X16, X1

  (486) 0x42a048 ADD	X4, X4, X1

  (486) 0x42a04c ADD	X23, X15, X6,LSL #3

  (486) 0x42a050 LDR	X0, [SP, #120]

  (486) 0x42a054 ADD	X21, X21, X4,LSL #3

  (486) 0x42a058 ADD	X28, X28, #8

  (486) 0x42a05c ADD	X27, X27, #8

  (486) 0x42a060 ADD	X23, X23, #8

  (486) 0x42a064 LDR	X16, [SP, #240]

  (486) 0x42a068 ADD	X21, X21, #8

  (486) 0x42a06c ADD	X13, X13, X1

  (486) 0x42a070 LDR	X15, [SP, #192]

  (486) 0x42a074 STP	X17, X13, [SP, #280]

  (486) 0x42a078 ADD	X9, X0, X9,LSL #3

  (486) 0x42a07c ADD	X8, X0, X8,LSL #3

  (486) 0x42a080 ADD	X18, X16, X1

  (486) 0x42a084 LDR	X13, [SP, #128]

  (486) 0x42a088 LDR	X16, [SP, #224]

  (486) 0x42a08c ADD	X11, X13, X11,LSL #3

  (486) 0x42a090 ADD	X10, X13, X10,LSL #3

  (486) 0x42a094 LDP	X13, X0, [SP, #104]

  (486) 0x42a098 ADD	X17, X16, X1

  (486) 0x42a09c LDR	X16, [SP, #208]

  (486) 0x42a0a0 ADD	X6, X13, X6,LSL #3

  (486) 0x42a0a4 ADD	X4, X13, X4,LSL #3

  (486) 0x42a0a8 LDR	X13, [SP, #280]

  (486) 0x42a0ac ADD	X7, X0, X7,LSL #3

  (486) 0x42a0b0 ADD	X5, X0, X5,LSL #3

  (486) 0x42a0b4 LDR	X0, [SP, #264]

  (486) 0x42a0b8 ADD	X2, X16, X1

  (486) 0x42a0bc ADD	X16, X15, X1

  (486) 0x42a0c0 LDR	X15, [SP, #144]

  (486) 0x42a0c4 ADD	X13, X0, X13,LSL #3

  (486) 0x42a0c8 ADD	X20, X0, X20,LSL #3

  (486) 0x42a0cc LDR	X0, [SP, #232]

  (486) 0x42a0d0 ADD	X15, X15, X1

  (486) 0x42a0d4 STR	X13, [SP, #280]

  (486) 0x42a0d8 LDR	X13, [SP, #288]

  (486) 0x42a0dc STR	X19, [SP, #288]

  (486) 0x42a0e0 ADD	X18, X0, X18,LSL #3

  (486) 0x42a0e4 LDR	X0, [SP, #216]

  (486) 0x42a0e8 LDR	X19, [SP, #280]

  (486) 0x42a0ec ADD	X17, X0, X17,LSL #3

  (486) 0x42a0f0 LDR	X0, [SP, #200]

  (486) 0x42a0f4 ADD	X2, X0, X2,LSL #3

  (486) 0x42a0f8 LDR	X0, [SP, #136]

  (486) 0x42a0fc ADD	X16, X0, X16,LSL #3

  (486) 0x42a100 LDR	X0, [SP, #152]

  (486) 0x42a104 ADD	X15, X0, X15,LSL #3

  (486) 0x42a108 LDR	X0, [SP, #168]

  (486) 0x42a10c ADD	X14, X0, X14,LSL #3

  (486) 0x42a110 LDR	X0, [SP, #184]

  (486) 0x42a114 ADD	X13, X0, X13,LSL #3

  (486) 0x42a118 MOVZ	X0, #0

  (486) 0x42a11c HINT	#0

    (485) 0x42a120 LDR	Q6, [X27, X0]

    (485) 0x42a124 LDR	Q18, [X28, X0]

    (485) 0x42a128 LDR	Q2, [X10, X0]

    (485) 0x42a12c LDR	Q24, [X11, X0]

    (485) 0x42a130 LDR	Q25, [X24, X0]

    (485) 0x42a134 FADD	V18.2D, V6.2D, V18.2D

    (485) 0x42a138 LDR	Q3, [X26, X0]

    (485) 0x42a13c LDR	Q0, [X7, X0]

    (485) 0x42a140 FADD	V24.2D, V2.2D, V24.2D

    (485) 0x42a144 LDR	Q20, [X22, X0]

    (485) 0x42a148 LDR	Q19, [X5, X0]

    (485) 0x42a14c FADD	V3.2D, V18.2D, V3.2D

    (485) 0x42a150 LDR	Q23, [X9, X0]

    (485) 0x42a154 FADD	V0.2D, V25.2D, V0.2D

    (485) 0x42a158 LDR	Q4, [X6, X0]

    (485) 0x42a15c LDR	Q25, [X25, X0]

    (485) 0x42a160 FADD	V19.2D, V20.2D, V19.2D

    (485) 0x42a164 LDR	Q7, [X4, X0]

    (485) 0x42a168 FADD	V23.2D, V24.2D, V23.2D

    (485) 0x42a16c LDR	Q1, [X8, X0]

    (485) 0x42a170 FADD	V4.2D, V0.2D, V4.2D

    (485) 0x42a174 LDR	Q0, [X30, X0]

    (485) 0x42a178 FADD	V25.2D, V3.2D, V25.2D

    (485) 0x42a17c LDR	Q17, [X21, X0]

    (485) 0x42a180 FADD	V7.2D, V19.2D, V7.2D

    (485) 0x42a184 LDR	Q5, [X12, X0]

    (485) 0x42a188 FADD	V1.2D, V23.2D, V1.2D

    (485) 0x42a18c FMUL	V0.2D, V25.2D, V0.2D

    (485) 0x42a190 LDR	Q22, [X23, X0]

    (485) 0x42a194 LDR	Q16, [X19, X0]

    (485) 0x42a198 FADD	V17.2D, V7.2D, V17.2D

    (485) 0x42a19c FMUL	V5.2D, V1.2D, V5.2D

    (485) 0x42a1a0 LDR	Q21, [X20, X0]

    (485) 0x42a1a4 FMUL	V0.2D, V0.2D, V27.2D

    (485) 0x42a1a8 FADD	V22.2D, V4.2D, V22.2D

    (485) 0x42a1ac LDR	Q20, [X2, X0]

    (485) 0x42a1b0 FMUL	V16.2D, V17.2D, V16.2D

    (485) 0x42a1b4 LDR	Q19, [X16, X0]

    (485) 0x42a1b8 FMUL	V5.2D, V5.2D, V27.2D

    (485) 0x42a1bc FMUL	V0.2D, V0.2D, V28.2D

    (485) 0x42a1c0 LDR	Q7, [X17, X0]

    (485) 0x42a1c4 FMUL	V21.2D, V22.2D, V21.2D

    (485) 0x42a1c8 LDR	Q4, [X18, X0]

    (485) 0x42a1cc FMUL	V16.2D, V16.2D, V27.2D

    (485) 0x42a1d0 FDIV	V19.2D, V19.2D, V20.2D

    (485) 0x42a1d4 LDR	Q17, [X15, X0]

    (485) 0x42a1d8 FMLS	V0.2D, V28.2D, V5.2D

    (485) 0x42a1dc FDIV	V7.2D, V7.2D, V20.2D

    (485) 0x42a1e0 FMUL	V21.2D, V21.2D, V27.2D

    (485) 0x42a1e4 FMLA	V0.2D, V16.2D, V28.2D

    (485) 0x42a1e8 FADD	V7.2D, V19.2D, V7.2D

    (485) 0x42a1ec FMLS	V0.2D, V21.2D, V28.2D

    (485) 0x42a1f0 FADD	V22.2D, V4.2D, V0.2D

    (485) 0x42a1f4 FMUL	V7.2D, V7.2D, V0.2D

    (485) 0x42a1f8 FDIV	V22.2D, V4.2D, V22.2D

    (485) 0x42a1fc FDIV	V4.2D, V26.2D, V4.2D

    (485) 0x42a200 FMLS	V17.2D, V7.2D, V4.2D

    (485) 0x42a204 STR	Q17, [X14, X0]

    (485) 0x42a208 LDR	Q2, [X2, X0]

    (485) 0x42a20c FMUL	V2.2D, V2.2D, V22.2D

    (485) 0x42a210 STR	Q2, [X13, X0]

    (485) 0x42a214 ADD	X0, X0, #16

    (485) 0x42a218 CMP	X0, X3

    (485) 0x42a21c B.NE	42a120

  (486) 0x42a220 LDR	W0, [SP, #272]

  (486) 0x42a224 LDR	X19, [SP, #288]

  (486) 0x42a228 AND	W7, W0, #1951

  (486) 0x42a22c TBZ	W0, #0, 42a490

  (487) 0x42a230 LDP	X0, X2, [SP, #344]

  (487) 0x42a234 LDP	X20, X17, [SP, #104]

  (487) 0x42a238 ADD	X9, X2, X1

  (487) 0x42a23c ADD	X4, X0, X1

  (487) 0x42a240 ORR	W0, WZR, W7

  (487) 0x42a244 LDR	X2, [SP, #336]

  (487) 0x42a248 ADD	X4, X4, X0

  (487) 0x42a24c ADD	X9, X9, X0

  (487) 0x42a250 LDR	X13, [SP, #128]

  (487) 0x42a254 LDR	W14, [SP, #272]

  (487) 0x42a258 ADD	X10, X2, X1

  (487) 0x42a25c LDR	X2, [SP, #328]

  (487) 0x42a260 ADD	X10, X10, X0

  (487) 0x42a264 ADD	X11, X13, X4,LSL #3

  (487) 0x42a268 LDR	X12, [SP, #248]

  (487) 0x42a26c SUB	W7, W14, W7

  (487) 0x42a270 WHILELO	P7.D, XZR, X7

  (487) 0x42a274 LD1D	{Z5.D}, P7/Z, [X13, X4,LSL #3]

  (487) 0x42a278 LD1D	{Z1.D}, P7/Z, [X13, X9,LSL #3]

  (487) 0x42a27c ADD	X11, X11, #8

  (487) 0x42a280 LDR	X14, [SP, #120]

  (487) 0x42a284 ADD	X7, X13, X9,LSL #3

  (487) 0x42a288 LD1D	{Z6.D}, P7/Z, [X14, X10,LSL #3]

  (487) 0x42a28c LD1D	{Z0.D}, P7/Z, [X11, MUL VL]

  (487) 0x42a290 FADD	Z1.D, P7/M, Z1.D, Z5.D

  (487) 0x42a294 ADD	X8, X2, X1

  (487) 0x42a298 LDP	X4, X2, [SP, #360]

  (487) 0x42a29c FADD	Z1.D, P7/M, Z1.D, Z6.D

  (487) 0x42a2a0 ADD	X8, X8, X0

  (487) 0x42a2a4 LD1D	{Z18.D}, P7/Z, [X14, X8,LSL #3]

  (487) 0x42a2a8 ADD	X7, X7, #8

  (487) 0x42a2ac FADD	Z1.D, P7/M, Z1.D, Z18.D

  (487) 0x42a2b0 ADD	X12, X12, X1

  (487) 0x42a2b4 ADD	X12, X12, X0

  (487) 0x42a2b8 ADD	X9, X14, X10,LSL #3

  (487) 0x42a2bc ADD	X6, X2, X1

  (487) 0x42a2c0 LDR	X2, [SP, #296]

  (487) 0x42a2c4 ADD	X10, X14, X8,LSL #3

  (487) 0x42a2c8 ADD	X6, X6, X0

  (487) 0x42a2cc LD1D	{Z24.D}, P7/Z, [X4, X6,LSL #3]

  (487) 0x42a2d0 ADD	X9, X9, #8

  (487) 0x42a2d4 ADD	X18, X20, X12,LSL #3

  (487) 0x42a2d8 FMUL	Z24.D, P7/M, Z24.D, Z1.D

  (487) 0x42a2dc LDR	X8, [SP, #256]

  (487) 0x42a2e0 ADD	X13, X4, X6,LSL #3

  (487) 0x42a2e4 ADD	X10, X10, #8

  (487) 0x42a2e8 FMUL	Z24.D, P7/M, Z24.D, Z30.D

  (487) 0x42a2ec ADD	X18, X18, #8

  (487) 0x42a2f0 LDR	X6, [SP, #192]

  (487) 0x42a2f4 ADD	X13, X13, #8

  (487) 0x42a2f8 ADD	X5, X2, X1

  (487) 0x42a2fc ADD	X5, X5, X0

  (487) 0x42a300 LDR	X4, [SP, #224]

  (487) 0x42a304 LD1D	{Z6.D}, P7/Z, [X17, X5,LSL #3]

  (487) 0x42a308 ADD	X11, X8, X1

  (487) 0x42a30c LDP	X2, X8, [SP, #312]

  (487) 0x42a310 ADD	X16, X17, X5,LSL #3

  (487) 0x42a314 ADD	X11, X11, X0

  (487) 0x42a318 ADD	X16, X16, #8

  (487) 0x42a31c LDR	X5, [SP, #144]

  (487) 0x42a320 ADD	X15, X4, X1

  (487) 0x42a324 ADD	X3, X2, X1

  (487) 0x42a328 ADD	X14, X8, X1

  (487) 0x42a32c LDR	X2, [SP, #304]

  (487) 0x42a330 ADD	X3, X3, X0

  (487) 0x42a334 ADD	X8, X6, X1

  (487) 0x42a338 LD1D	{Z25.D}, P7/Z, [X17, X3,LSL #3]

  (487) 0x42a33c ADD	X3, X17, X3,LSL #3

  (487) 0x42a340 ADD	X14, X14, X0

  (487) 0x42a344 ADD	X15, X15, X0

  (487) 0x42a348 LDR	X4, [SP, #208]

  (487) 0x42a34c ADD	X8, X8, X0

  (487) 0x42a350 ADD	X17, X5, X1

  (487) 0x42a354 ADD	X3, X3, #8

  (487) 0x42a358 LDR	X5, [SP, #160]

  (487) 0x42a35c ADD	X17, X17, X0

  (487) 0x42a360 ADD	X2, X2, X1

  (487) 0x42a364 LDR	X6, [SP, #240]

  (487) 0x42a368 ADD	X2, X2, X0

  (487) 0x42a36c LD1D	{Z2.D}, P7/Z, [X20, X2,LSL #3]

  (487) 0x42a370 ADD	X2, X20, X2,LSL #3

  (487) 0x42a374 ADD	X4, X4, X1

  (487) 0x42a378 LDR	X21, [SP, #176]

  (487) 0x42a37c ADD	X4, X4, X0

  (487) 0x42a380 LD1D	{Z7.D}, P7/Z, [X9, MUL VL]

  (487) 0x42a384 LD1D	{Z19.D}, P7/Z, [X10, MUL VL]

  (487) 0x42a388 LD1D	{Z3.D}, P7/Z, [X7, MUL VL]

  (487) 0x42a38c ADD	X5, X5, X1

  (487) 0x42a390 ADD	X2, X2, #8

  (487) 0x42a394 FADD	Z3.D, P7/M, Z3.D, Z0.D

  (487) 0x42a398 FADD	Z3.D, P7/M, Z3.D, Z7.D

  (487) 0x42a39c FADD	Z3.D, P7/M, Z3.D, Z19.D

  (487) 0x42a3a0 ADD	X5, X5, X0

  (487) 0x42a3a4 LD1D	{Z17.D}, P7/Z, [X2, MUL VL]

  (487) 0x42a3a8 LDR	X2, [SP, #264]

  (487) 0x42a3ac LD1D	{Z0.D}, P7/Z, [X20, X12,LSL #3]

  (487) 0x42a3b0 LD1D	{Z23.D}, P7/Z, [X13, MUL VL]

  (487) 0x42a3b4 ADD	X6, X6, X1

  (487) 0x42a3b8 FMUL	Z23.D, P7/M, Z23.D, Z3.D

  (487) 0x42a3bc LD1D	{Z20.D}, P7/Z, [X3, MUL VL]

  (487) 0x42a3c0 LD1D	{Z1.D}, P7/Z, [X16, MUL VL]

  (487) 0x42a3c4 LD1D	{Z5.D}, P7/Z, [X2, X11,LSL #3]

  (487) 0x42a3c8 ADD	X6, X6, X0

  (487) 0x42a3cc LD1D	{Z22.D}, P7/Z, [X2, X14,LSL #3]

  (487) 0x42a3d0 LDR	X2, [SP, #216]

  (487) 0x42a3d4 FMUL	Z23.D, P7/M, Z23.D, Z30.D

  (487) 0x42a3d8 FADD	Z25.D, P7/M, Z25.D, Z20.D

  (487) 0x42a3dc ADD	X1, X21, X1

  (487) 0x42a3e0 FADD	Z25.D, P7/M, Z25.D, Z2.D

  (487) 0x42a3e4 FADD	Z6.D, P7/M, Z6.D, Z1.D

  (487) 0x42a3e8 FADD	Z25.D, P7/M, Z25.D, Z17.D

  (487) 0x42a3ec FADD	Z6.D, P7/M, Z6.D, Z0.D

  (487) 0x42a3f0 ADD	X1, X1, X0

  (487) 0x42a3f4 LDR	X0, [SP, #232]

  (487) 0x42a3f8 LD1D	{Z3.D}, P7/Z, [X0, X6,LSL #3]

  (487) 0x42a3fc LD1D	{Z1.D}, P7/Z, [X2, X15,LSL #3]

  (487) 0x42a400 LD1D	{Z7.D}, P7/Z, [X18, MUL VL]

  (487) 0x42a404 MOVPRFX	Z4, Z31

  (487) 0x42a408 FMUL	Z4.D, P7/M, Z4.D, Z23.D

  (487) 0x42a40c FMUL	Z22.D, P7/M, Z22.D, Z25.D

  (487) 0x42a410 FMLS	Z4.D, P7/M, Z31.D, Z24.D

  (487) 0x42a414 FADD	Z6.D, P7/M, Z6.D, Z7.D

  (487) 0x42a418 FMUL	Z22.D, P7/M, Z22.D, Z30.D

  (487) 0x42a41c LDR	X0, [SP, #152]

  (487) 0x42a420 LD1D	{Z0.D}, P7/Z, [X0, X17,LSL #3]

  (487) 0x42a424 FMUL	Z5.D, P7/M, Z5.D, Z6.D

  (487) 0x42a428 MOVPRFX	Z23, Z29

  (487) 0x42a42c FDIV	Z23.D, P7/M, Z23.D, Z3.D

  (487) 0x42a430 FMUL	Z5.D, P7/M, Z5.D, Z30.D

  (487) 0x42a434 MOVPRFX	Z19, Z31

  (487) 0x42a438 FMUL	Z19.D, P7/M, Z19.D, Z5.D

  (487) 0x42a43c FADD	Z19.D, P7/M, Z19.D, Z4.D

  (487) 0x42a440 FMLS	Z19.D, P7/M, Z31.D, Z22.D

  (487) 0x42a444 MOVPRFX	Z2, Z19

  (487) 0x42a448 FADD	Z2.D, P7/M, Z2.D, Z3.D

  (487) 0x42a44c MOVPRFX	Z20, Z3

  (487) 0x42a450 FDIV	Z20.D, P7/M, Z20.D, Z2.D

  (487) 0x42a454 LDR	X0, [SP, #168]

  (487) 0x42a458 LDR	X3, [SP, #136]

  (487) 0x42a45c LD1D	{Z25.D}, P7/Z, [X3, X8,LSL #3]

  (487) 0x42a460 LDR	X2, [SP, #200]

  (487) 0x42a464 LD1D	{Z17.D}, P7/Z, [X2, X4,LSL #3]

  (487) 0x42a468 FDIV	Z1.D, P7/M, Z1.D, Z17.D

  (487) 0x42a46c FDIV	Z25.D, P7/M, Z25.D, Z17.D

  (487) 0x42a470 FADD	Z1.D, P7/M, Z1.D, Z25.D

  (487) 0x42a474 FMUL	Z19.D, P7/M, Z19.D, Z1.D

  (487) 0x42a478 FMLS	Z0.D, P7/M, Z23.D, Z19.D

  (487) 0x42a47c ST1D	{Z0.D}, P7, [X0, X5,LSL #3]

  (487) 0x42a480 LD1D	{Z18.D}, P7/Z, [X2, X4,LSL #3]

  (487) 0x42a484 FMUL	Z20.D, P7/M, Z20.D, Z18.D

  (487) 0x42a488 LDR	X0, [SP, #184]

  (487) 0x42a48c ST1D	{Z20.D}, P7, [X0, X1,LSL #3]

  (486) 0x42a490 LDR	W3, [SP, #276]

  (483) 0x42a494 ADD	X19, X19, #1

  (483) 0x42a498 LDR	W0, [SP, #376]

  (483) 0x42a49c CMP	W0, W19

  (483) 0x42a4a0 B.LE	42a4cc

  (483) 0x42a4a4 LDR	W0, [SP, #388]

  (483) 0x42a4a8 LDR	W1, [SP, #380]

  (483) 0x42a4ac LDR	W2, [SP, #384]

  (483) 0x42a4b0 SUB	W4, W0, W3

  (483) 0x42a4b4 B	429e70

0x42a4b8 LDP	X23, X24, [SP, #48]

0x42a4bc LDP	X19, X20, [SP, #16]

0x42a4c0 LDP	X21, X22, [SP, #32]

0x42a4c4 LDP	X29, X30, [SP], #496

0x42a4c8 RET

(482) 0x42a4cc LDP	X23, X24, [SP, #48]

(482) 0x42a4d0 LDP	X25, X26, [SP, #64]

(482) 0x42a4d4 LDP	X27, X28, [SP, #80]

(482) 0x42a4d8 LDP	X19, X20, [SP, #16]

(482) 0x42a4dc LDP	X21, X22, [SP, #32]

(482) 0x42a4e0 LDP	X29, X30, [SP], #496

(482) 0x42a4e4 RET

  (484) 0x42a4e8 MOVZ	W7, #0

  (484) 0x42a4ec SBFM	X1, X1, #0, #31

  (484) 0x42a4f0 B	42a230

0x42a4f4 ADD	W4, W4, #1

0x42a4f8 MOVZ	W0, #0

0x42a4fc B	429dc8

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 54% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 200 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	1.50	1.50	1.50	1.50	12.67	12.67	12.67	11.00	11.00
cycles	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	1.50	1.50	1.50	1.50	12.67	12.67	12.67	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	10.00
Overall L1	12.67-25.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	20%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429d50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #528]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W1, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W0, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42a4bc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x76c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42a4b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 42a4f4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W4, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #388]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 42a4b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V27.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV V26.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDUP Z29.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X2, X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D28, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z31.D, Z28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X2, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X5, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X21, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
DUP V28.2D, V28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X2, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X2, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W0, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X0, X5, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W2, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X5, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X5, X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #496	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 429dc8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 54% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 200 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	1.50	1.50	1.50	1.50	12.67	12.67	12.67	11.00	11.00
cycles	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	1.50	1.50	1.50	1.50	12.67	12.67	12.67	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	10.00
Overall L1	12.67-25.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	20%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429d50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #528]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W2, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W1, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W0, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42a4bc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x76c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42a4b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 42a4f4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W4, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #388]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 42a4b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V27.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV V26.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDUP Z29.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X2, X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D28, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z31.D, Z28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X2, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X5, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X21, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
DUP V28.2D, V28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X2, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X2, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W0, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X0, X5, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W2, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X5, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X5, X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #496	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 429dc8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	7.87	6.07
▼Loop 482 - PdV.cpp:69-83 - exec–	0.00	0.00
▼Loop 486 - PdV.cpp:71-83 - exec–	0.01	0.01
○Loop 485 - PdV.cpp:72-83 - exec	7.86	6.02
○Loop 483 - PdV.cpp:71-75 - exec	0.00	0.01
○Loop 487 - PdV.cpp:72-83 - exec	0.00	0.00
○Loop 484 - context.h:69-69 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code