OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 6.10% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x429700 STP	X29, X30, [SP, #656]!

0x429704 ADD	X29, SP, #0

0x429708 STP	X19, X20, [SP, #16]

0x42970c ORR	X20, XZR, X0

0x429710 STP	X21, X22, [SP, #32]

0x429714 LDP	W22, W1, [X0, #104]

0x429718 LDP	W0, W3, [X0, #96]

0x42971c ADD	W1, W1, #2

0x429720 ADD	W22, W22, #1

0x429724 ADD	W0, W0, #1

0x429728 STR	W1, [SP, #264]

0x42972c STR	W0, [SP, #268]

0x429730 CMP	W22, W1

0x429734 B.GE	429d0c

0x429738 ADD	W19, W3, #2

0x42973c STP	X23, X24, [SP, #48]

0x429740 SUB	W23, W1, W22

0x429744 CMP	W0, W19

0x429748 B.GE	429d08

0x42974c SUB	W0, W19, W0

0x429750 MADD	W23, W23, W0, WZR

0x429754 STR	W0, [SP, #272]

0x429758 BL	403aa0

0x42975c ORR	W21, WZR, W0

0x429760 BL	403980

0x429764 UDIV	W4, W23, W21

0x429768 ORR	W2, WZR, W0

0x42976c MSUB	W0, W4, W21, W23

0x429770 CMP	W2, W0

0x429774 B.CC	429d44

0x429778 MADD	W2, W4, W2, W0

0x42977c ADD	W0, W4, W2

0x429780 STR	W0, [SP, #276]

0x429784 CMP	W2, W0

0x429788 B.CS	429d08

0x42978c LDR	W1, [SP, #272]

0x429790 FMOV	V26.2D, #0.2500000

0x429794 FMOV	V25.2D, #0.5000000

0x429798 FDUP	Z30.D, #80

0x42979c FDUP	Z29.D, #96

0x4297a0 STP	X25, X26, [SP, #64]

0x4297a4 FMOV	V24.2D, #1.0000000

0x4297a8 FDUP	Z28.D, #112

0x4297ac STP	X27, X28, [SP, #80]

0x4297b0 UDIV	W0, W2, W1

0x4297b4 LDP	X3, X5, [X20, #8]

0x4297b8 LDR	D27, [X20]

0x4297bc DUP	Z31.D, Z27.D[0]

0x4297c0 STR	X3, [SP, #280]

0x4297c4 STR	X5, [SP, #296]

0x4297c8 LDP	X3, X5, [X20, #24]

0x4297cc MSUB	W1, W0, W1, W2

0x4297d0 ADD	W0, W0, W22

0x4297d4 SBFM	X27, X0, #0, #31

0x4297d8 DUP	V27.2D, V27.D[0]

0x4297dc STR	X3, [SP, #312]

0x4297e0 STR	X5, [SP, #328]

0x4297e4 LDP	X0, X3, [X20, #40]

0x4297e8 STR	X0, [SP, #360]

0x4297ec LDR	W0, [SP, #268]

0x4297f0 STR	X3, [SP, #344]

0x4297f4 ADD	W1, W1, W0

0x4297f8 LDP	X0, X5, [X20, #56]

0x4297fc SUB	W3, W19, W1

0x429800 STR	X5, [SP, #320]

0x429804 STR	X0, [SP, #352]

0x429808 LDP	X0, X5, [X20, #72]

0x42980c STR	X0, [SP, #336]

0x429810 LDR	X0, [X20, #88]

0x429814 STR	X5, [SP, #288]

0x429818 STR	X0, [SP, #304]

0x42981c HINT	#0

  (477) 0x429820 CMP	W4, W3

  (477) 0x429824 CSEL	W4, W4, W3, #9

  (477) 0x429828 ADD	W0, W2, W4

  (477) 0x42982c STR	W0, [SP, #204]

  (477) 0x429830 CMP	W2, W0

  (477) 0x429834 B.CS	429ce4

  (480) 0x429838 LDP	X8, X9, [SP, #296]

  (480) 0x42983c LDP	X11, X7, [SP, #280]

  (480) 0x429840 LDP	X12, X13, [SP, #312]

  (480) 0x429844 LDR	X0, [X9]

  (480) 0x429848 LDR	X3, [X7]

  (480) 0x42984c LDR	X6, [X11]

  (480) 0x429850 MADD	X25, X0, X27, XZR

  (480) 0x429854 LDR	X5, [X12]

  (480) 0x429858 MADD	X26, X3, X27, XZR

  (480) 0x42985c LDR	X2, [X8]

  (480) 0x429860 ADD	X20, X0, X25

  (480) 0x429864 MADD	X19, X27, X6, XZR

  (480) 0x429868 ADD	X17, X3, X26

  (480) 0x42986c LDR	X3, [X13]

  (480) 0x429870 MADD	X0, X27, X5, XZR

  (480) 0x429874 LDP	X6, X5, [SP, #328]

  (480) 0x429878 MADD	X10, X2, X27, XZR

  (480) 0x42987c STR	X19, [SP, #256]

  (480) 0x429880 MADD	X3, X27, X3, XZR

  (480) 0x429884 ADD	X18, X2, X10

  (480) 0x429888 LDR	X2, [X6]

  (480) 0x42988c STP	X10, X17, [SP, #240]

  (480) 0x429890 STP	X3, X0, [SP, #184]

  (480) 0x429894 MADD	X15, X27, X2, XZR

  (480) 0x429898 STP	X20, X18, [SP, #224]

  (480) 0x42989c LDR	X0, [X5]

  (480) 0x4298a0 STR	X15, [SP, #168]

  (480) 0x4298a4 LDP	X14, X15, [SP, #344]

  (480) 0x4298a8 MADD	X16, X27, X0, XZR

  (480) 0x4298ac LDR	X30, [X11, #16]

  (480) 0x4298b0 LDR	X3, [X14]

  (480) 0x4298b4 STR	X16, [SP, #152]

  (480) 0x4298b8 LDR	X16, [SP, #360]

  (480) 0x4298bc LDR	X2, [X15]

  (480) 0x4298c0 MADD	X21, X27, X3, XZR

  (480) 0x4298c4 LDR	X5, [X5, #16]

  (480) 0x4298c8 LDR	X0, [X16]

  (480) 0x4298cc STR	X21, [SP, #112]

  (480) 0x4298d0 MADD	X11, X27, X2, XZR

  (480) 0x4298d4 LDR	X6, [X6, #16]

  (480) 0x4298d8 LDR	X24, [X7, #16]

  (480) 0x4298dc MADD	X7, X27, X0, XZR

  (480) 0x4298e0 STR	X5, [SP, #104]

  (480) 0x4298e4 LDR	X28, [X8, #16]

  (480) 0x4298e8 STR	X6, [SP, #160]

  (480) 0x4298ec LDR	X8, [X12, #16]

  (480) 0x4298f0 LDR	X23, [X9, #16]

  (480) 0x4298f4 LDR	X12, [X14, #16]

  (480) 0x4298f8 ORR	X0, XZR, X8

  (480) 0x4298fc LDR	X9, [X13, #16]

  (480) 0x429900 LDR	X14, [X16, #16]

  (480) 0x429904 LDR	X13, [X15, #16]

  (480) 0x429908 STR	X9, [SP, #176]

  (480) 0x42990c STP	X11, X8, [SP, #208]

  (480) 0x429910 STP	X12, X13, [SP, #120]

  (480) 0x429914 STP	X7, X14, [SP, #136]

  (480) 0x429918 CMP	W4, #1

  (480) 0x42991c B.EQ	429d38

  (480) 0x429920 SBFM	X1, X1, #0, #31

  (480) 0x429924 UBFM	W3, W4, #1, #31

  (480) 0x429928 LDR	X2, [SP, #192]

  (480) 0x42992c ADD	X7, X17, X1

  (480) 0x429930 ADD	X17, X10, X1

  (480) 0x429934 ADD	X11, X11, X1

  (480) 0x429938 ADD	X9, X19, X1

  (480) 0x42993c ADD	X17, X28, X17,LSL #3

  (480) 0x429940 LDR	X10, [SP, #152]

  (480) 0x429944 ADD	X5, X20, X1

  (480) 0x429948 ADD	X8, X26, X1

  (480) 0x42994c ADD	X22, X30, X9,LSL #3

  (480) 0x429950 ADD	X6, X25, X1

  (480) 0x429954 ADD	X21, X24, X8,LSL #3

  (480) 0x429958 ADD	X16, X18, X1

  (480) 0x42995c ADD	X20, X24, X7,LSL #3

  (480) 0x429960 ORR	X9, XZR, X22

  (480) 0x429964 UBFM	X3, X3, #60, #59

  (480) 0x429968 ADD	X15, X2, X1

  (480) 0x42996c ADD	X19, X23, X6,LSL #3

  (480) 0x429970 ORR	X8, XZR, X21

  (480) 0x429974 ADD	X15, X0, X15,LSL #3

  (480) 0x429978 LDP	X0, X2, [SP, #176]

  (480) 0x42997c ORR	X7, XZR, X20

  (480) 0x429980 ADD	X22, X22, #8

  (480) 0x429984 ADD	X13, X10, X1

  (480) 0x429988 ADD	X18, X23, X5,LSL #3

  (480) 0x42998c ADD	X21, X21, #8

  (480) 0x429990 ADD	X6, X23, X6,LSL #3

  (480) 0x429994 ADD	X20, X20, #8

  (480) 0x429998 ADD	X19, X19, #8

  (480) 0x42999c ADD	X5, X23, X5,LSL #3

  (480) 0x4299a0 ADD	X18, X18, #8

  (480) 0x4299a4 LDR	X10, [SP, #112]

  (480) 0x4299a8 ADD	X16, X28, X16,LSL #3

  (480) 0x4299ac ADD	X14, X2, X1

  (480) 0x4299b0 ADD	X14, X0, X14,LSL #3

  (480) 0x4299b4 LDP	X0, X2, [SP, #160]

  (480) 0x4299b8 ADD	X12, X10, X1

  (480) 0x4299bc LDR	X10, [SP, #136]

  (480) 0x4299c0 ADD	X2, X2, X1

  (480) 0x4299c4 ADD	X2, X0, X2,LSL #3

  (480) 0x4299c8 LDR	X0, [SP, #104]

  (480) 0x4299cc ADD	X10, X10, X1

  (480) 0x4299d0 ADD	X13, X0, X13,LSL #3

  (480) 0x4299d4 LDR	X0, [SP, #120]

  (480) 0x4299d8 ADD	X12, X0, X12,LSL #3

  (480) 0x4299dc LDR	X0, [SP, #128]

  (480) 0x4299e0 ADD	X11, X0, X11,LSL #3

  (480) 0x4299e4 LDR	X0, [SP, #144]

  (480) 0x4299e8 ADD	X10, X0, X10,LSL #3

  (480) 0x4299ec MOVZ	X0, #0

    (479) 0x4299f0 LDR	Q2, [X6, X0]

    (479) 0x4299f4 LDR	Q18, [X19, X0]

    (479) 0x4299f8 LDR	Q21, [X21, X0]

    (479) 0x4299fc LDR	Q20, [X20, X0]

    (479) 0x429a00 FADD	V17.2D, V18.2D, V2.2D

    (479) 0x429a04 LDR	Q23, [X8, X0]

    (479) 0x429a08 LDR	Q22, [X7, X0]

    (479) 0x429a0c LDR	Q7, [X5, X0]

    (479) 0x429a10 FADD	V17.2D, V17.2D, V2.2D

    (479) 0x429a14 LDR	Q6, [X18, X0]

    (479) 0x429a18 FADD	V2.2D, V20.2D, V21.2D

    (479) 0x429a1c FADD	V0.2D, V22.2D, V23.2D

    (479) 0x429a20 LDR	Q16, [X17, X0]

    (479) 0x429a24 LDR	Q19, [X9, X0]

    (479) 0x429a28 FADD	V17.2D, V17.2D, V18.2D

    (479) 0x429a2c LDR	Q1, [X16, X0]

    (479) 0x429a30 FADD	V2.2D, V2.2D, V21.2D

    (479) 0x429a34 FADD	V5.2D, V6.2D, V7.2D

    (479) 0x429a38 LDR	Q4, [X13, X0]

    (479) 0x429a3c FADD	V0.2D, V0.2D, V23.2D

    (479) 0x429a40 LDR	Q3, [X14, X0]

    (479) 0x429a44 FMUL	V16.2D, V17.2D, V16.2D

    (479) 0x429a48 LDR	Q17, [X22, X0]

    (479) 0x429a4c FADD	V2.2D, V2.2D, V20.2D

    (479) 0x429a50 FADD	V5.2D, V5.2D, V7.2D

    (479) 0x429a54 LDR	Q7, [X15, X0]

    (479) 0x429a58 FADD	V0.2D, V0.2D, V22.2D

    (479) 0x429a5c FMUL	V16.2D, V16.2D, V26.2D

    (479) 0x429a60 FMUL	V17.2D, V2.2D, V17.2D

    (479) 0x429a64 FADD	V5.2D, V5.2D, V6.2D

    (479) 0x429a68 FMUL	V19.2D, V0.2D, V19.2D

    (479) 0x429a6c FMUL	V16.2D, V16.2D, V27.2D

    (479) 0x429a70 FMUL	V17.2D, V17.2D, V26.2D

    (479) 0x429a74 FMUL	V1.2D, V5.2D, V1.2D

    (479) 0x429a78 LDR	Q5, [X2, X0]

    (479) 0x429a7c FMUL	V19.2D, V19.2D, V26.2D

    (479) 0x429a80 FMUL	V17.2D, V17.2D, V27.2D

    (479) 0x429a84 FMUL	V1.2D, V1.2D, V26.2D

    (479) 0x429a88 FMUL	V19.2D, V19.2D, V27.2D

    (479) 0x429a8c FDIV	V4.2D, V4.2D, V5.2D

    (479) 0x429a90 FDIV	V3.2D, V3.2D, V5.2D

    (479) 0x429a94 FMUL	V17.2D, V17.2D, V25.2D

    (479) 0x429a98 FMUL	V1.2D, V1.2D, V27.2D

    (479) 0x429a9c FADD	V3.2D, V4.2D, V3.2D

    (479) 0x429aa0 FMLS	V17.2D, V19.2D, V25.2D

    (479) 0x429aa4 FMLA	V17.2D, V1.2D, V25.2D

    (479) 0x429aa8 LDR	Q1, [X12, X0]

    (479) 0x429aac FMLS	V17.2D, V16.2D, V25.2D

    (479) 0x429ab0 FADD	V6.2D, V7.2D, V17.2D

    (479) 0x429ab4 FMUL	V3.2D, V3.2D, V17.2D

    (479) 0x429ab8 FDIV	V6.2D, V7.2D, V6.2D

    (479) 0x429abc FDIV	V7.2D, V24.2D, V7.2D

    (479) 0x429ac0 FMLS	V1.2D, V3.2D, V7.2D

    (479) 0x429ac4 STR	Q1, [X11, X0]

    (479) 0x429ac8 LDR	Q18, [X2, X0]

    (479) 0x429acc FMUL	V18.2D, V18.2D, V6.2D

    (479) 0x429ad0 STR	Q18, [X10, X0]

    (479) 0x429ad4 ADD	X0, X0, #16

    (479) 0x429ad8 CMP	X0, X3

    (479) 0x429adc B.NE	4299f0

  (480) 0x429ae0 AND	W3, W4, #1951

  (480) 0x429ae4 TBZ	W4, #0, 429ce0

  (481) 0x429ae8 LDR	X0, [SP, #248]

  (481) 0x429aec ADD	X26, X26, X1

  (481) 0x429af0 SUB	W4, W4, W3

  (481) 0x429af4 WHILELO	P7.D, XZR, X4

  (481) 0x429af8 ADD	X25, X25, X1

  (481) 0x429afc LDR	X7, [SP, #224]

  (481) 0x429b00 LDR	X8, [SP, #192]

  (481) 0x429b04 ADD	X2, X0, X1

  (481) 0x429b08 ORR	W0, WZR, W3

  (481) 0x429b0c ADD	X26, X26, X0

  (481) 0x429b10 ADD	X5, X2, X0

  (481) 0x429b14 LDR	X2, [SP, #256]

  (481) 0x429b18 LD1D	{Z5.D}, P7/Z, [X24, X5,LSL #3]

  (481) 0x429b1c LD1D	{Z2.D}, P7/Z, [X24, X26,LSL #3]

  (481) 0x429b20 ADD	X6, X24, X26,LSL #3

  (481) 0x429b24 ADD	X25, X25, X0

  (481) 0x429b28 ADD	X7, X7, X1

  (481) 0x429b2c MOVPRFX	Z4, Z2

  (481) 0x429b30 FADD	Z4.D, P7/M, Z4.D, Z5.D

  (481) 0x429b34 FADD	Z2.D, P7/M, Z2.D, Z4.D

  (481) 0x429b38 ADD	X3, X24, X5,LSL #3

  (481) 0x429b3c ADD	X7, X7, X0

  (481) 0x429b40 FADD	Z5.D, P7/M, Z5.D, Z2.D

  (481) 0x429b44 LD1D	{Z17.D}, P7/Z, [X23, X25,LSL #3]

  (481) 0x429b48 LDR	X10, [SP, #136]

  (481) 0x429b4c ADD	X6, X6, #8

  (481) 0x429b50 LD1D	{Z19.D}, P7/Z, [X6, MUL VL]

  (481) 0x429b54 ADD	X4, X23, X25,LSL #3

  (481) 0x429b58 ADD	X8, X8, X1

  (481) 0x429b5c LDP	X5, X6, [SP, #232]

  (481) 0x429b60 ADD	X3, X3, #8

  (481) 0x429b64 LD1D	{Z1.D}, P7/Z, [X3, MUL VL]

  (481) 0x429b68 MOVPRFX	Z4, Z19

  (481) 0x429b6c FADD	Z4.D, P7/M, Z4.D, Z1.D

  (481) 0x429b70 FADD	Z19.D, P7/M, Z19.D, Z4.D

  (481) 0x429b74 ADD	X2, X2, X1

  (481) 0x429b78 ADD	X3, X23, X7,LSL #3

  (481) 0x429b7c FADD	Z1.D, P7/M, Z1.D, Z19.D

  (481) 0x429b80 ADD	X4, X4, #8

  (481) 0x429b84 ADD	X2, X2, X0

  (481) 0x429b88 LD1D	{Z0.D}, P7/Z, [X30, X2,LSL #3]

  (481) 0x429b8c FMUL	Z0.D, P7/M, Z0.D, Z5.D

  (481) 0x429b90 FMUL	Z0.D, P7/M, Z0.D, Z30.D

  (481) 0x429b94 MOVPRFX	Z3, Z31

  (481) 0x429b98 FMUL	Z3.D, P7/M, Z3.D, Z0.D

  (481) 0x429b9c ADD	X2, X30, X2,LSL #3

  (481) 0x429ba0 LD1D	{Z0.D}, P7/Z, [X4, MUL VL]

  (481) 0x429ba4 MOVPRFX	Z19, Z17

  (481) 0x429ba8 FADD	Z19.D, P7/M, Z19.D, Z0.D

  (481) 0x429bac ADD	X8, X8, X0

  (481) 0x429bb0 FADD	Z17.D, P7/M, Z17.D, Z19.D

  (481) 0x429bb4 ADD	X3, X3, #8

  (481) 0x429bb8 LD1D	{Z19.D}, P7/Z, [X23, X7,LSL #3]

  (481) 0x429bbc LDR	X7, [SP, #216]

  (481) 0x429bc0 FADD	Z0.D, P7/M, Z0.D, Z17.D

  (481) 0x429bc4 LD1D	{Z17.D}, P7/Z, [X3, MUL VL]

  (481) 0x429bc8 ADD	X6, X6, X1

  (481) 0x429bcc ADD	X2, X2, #8

  (481) 0x429bd0 LD1D	{Z7.D}, P7/Z, [X2, MUL VL]

  (481) 0x429bd4 MOVPRFX	Z4, Z19

  (481) 0x429bd8 FADD	Z4.D, P7/M, Z4.D, Z17.D

  (481) 0x429bdc FMUL	Z7.D, P7/M, Z7.D, Z1.D

  (481) 0x429be0 ADD	X6, X6, X0

  (481) 0x429be4 LDR	X4, [SP, #184]

  (481) 0x429be8 LD1D	{Z2.D}, P7/Z, [X28, X6,LSL #3]

  (481) 0x429bec FMUL	Z2.D, P7/M, Z2.D, Z0.D

  (481) 0x429bf0 LD1D	{Z0.D}, P7/Z, [X7, X8,LSL #3]

  (481) 0x429bf4 LDP	X6, X3, [SP, #168]

  (481) 0x429bf8 ADD	X5, X5, X1

  (481) 0x429bfc FADD	Z19.D, P7/M, Z19.D, Z4.D

  (481) 0x429c00 FADD	Z17.D, P7/M, Z17.D, Z19.D

  (481) 0x429c04 FMUL	Z2.D, P7/M, Z2.D, Z30.D

  (481) 0x429c08 ADD	X5, X5, X0

  (481) 0x429c0c LD1D	{Z1.D}, P7/Z, [X28, X5,LSL #3]

  (481) 0x429c10 FMUL	Z1.D, P7/M, Z1.D, Z17.D

  (481) 0x429c14 FMUL	Z1.D, P7/M, Z1.D, Z30.D

  (481) 0x429c18 FMUL	Z7.D, P7/M, Z7.D, Z30.D

  (481) 0x429c1c MOVPRFX	Z5, Z31

  (481) 0x429c20 FMUL	Z5.D, P7/M, Z5.D, Z1.D

  (481) 0x429c24 MOVPRFX	Z18, Z31

  (481) 0x429c28 FMUL	Z18.D, P7/M, Z18.D, Z2.D

  (481) 0x429c2c MOVPRFX	Z6, Z31

  (481) 0x429c30 FMUL	Z6.D, P7/M, Z6.D, Z7.D

  (481) 0x429c34 FMUL	Z5.D, P7/M, Z5.D, #0

  (481) 0x429c38 MOVPRFX	Z7, Z28

  (481) 0x429c3c FDIV	Z7.D, P7/M, Z7.D, Z0.D

  (481) 0x429c40 LDP	X7, X2, [SP, #152]

  (481) 0x429c44 FMUL	Z6.D, P7/M, Z6.D, #0

  (481) 0x429c48 FMLS	Z6.D, P7/M, Z3.D, Z29.D

  (481) 0x429c4c FADD	Z5.D, P7/M, Z5.D, Z6.D

  (481) 0x429c50 FMLS	Z5.D, P7/M, Z18.D, Z29.D

  (481) 0x429c54 ADD	X4, X4, X1

  (481) 0x429c58 MOVPRFX	Z2, Z5

  (481) 0x429c5c FADD	Z2.D, P7/M, Z2.D, Z0.D

  (481) 0x429c60 MOVPRFX	Z17, Z0

  (481) 0x429c64 FDIV	Z17.D, P7/M, Z17.D, Z2.D

  (481) 0x429c68 ADD	X6, X6, X1

  (481) 0x429c6c ADD	X4, X4, X0

  (481) 0x429c70 LD1D	{Z1.D}, P7/Z, [X3, X4,LSL #3]

  (481) 0x429c74 ADD	X6, X6, X0

  (481) 0x429c78 LD1D	{Z4.D}, P7/Z, [X2, X6,LSL #3]

  (481) 0x429c7c FDIV	Z1.D, P7/M, Z1.D, Z4.D

  (481) 0x429c80 LDR	X8, [SP, #112]

  (481) 0x429c84 ADD	X7, X7, X1

  (481) 0x429c88 LDR	X9, [SP, #208]

  (481) 0x429c8c ADD	X7, X7, X0

  (481) 0x429c90 ADD	X8, X8, X1

  (481) 0x429c94 ADD	X8, X8, X0

  (481) 0x429c98 ADD	X9, X9, X1

  (481) 0x429c9c ADD	X1, X10, X1

  (481) 0x429ca0 ADD	X9, X9, X0

  (481) 0x429ca4 ADD	X1, X1, X0

  (481) 0x429ca8 LDR	X0, [SP, #104]

  (481) 0x429cac LD1D	{Z19.D}, P7/Z, [X0, X7,LSL #3]

  (481) 0x429cb0 FDIV	Z19.D, P7/M, Z19.D, Z4.D

  (481) 0x429cb4 FADD	Z1.D, P7/M, Z1.D, Z19.D

  (481) 0x429cb8 FMUL	Z5.D, P7/M, Z5.D, Z1.D

  (481) 0x429cbc LDR	X0, [SP, #120]

  (481) 0x429cc0 LD1D	{Z0.D}, P7/Z, [X0, X8,LSL #3]

  (481) 0x429cc4 FMLS	Z0.D, P7/M, Z7.D, Z5.D

  (481) 0x429cc8 LDR	X0, [SP, #128]

  (481) 0x429ccc ST1D	{Z0.D}, P7, [X0, X9,LSL #3]

  (481) 0x429cd0 LD1D	{Z6.D}, P7/Z, [X2, X6,LSL #3]

  (481) 0x429cd4 FMUL	Z17.D, P7/M, Z17.D, Z6.D

  (481) 0x429cd8 LDR	X0, [SP, #144]

  (481) 0x429cdc ST1D	{Z17.D}, P7, [X0, X1,LSL #3]

  (480) 0x429ce0 LDR	W2, [SP, #204]

  (477) 0x429ce4 ADD	X27, X27, #1

  (477) 0x429ce8 LDR	W0, [SP, #264]

  (477) 0x429cec CMP	W0, W27

  (477) 0x429cf0 B.LE	429d1c

  (477) 0x429cf4 LDR	W0, [SP, #276]

  (477) 0x429cf8 LDR	W1, [SP, #268]

  (477) 0x429cfc LDR	W3, [SP, #272]

  (477) 0x429d00 SUB	W4, W0, W2

  (477) 0x429d04 B	429820

0x429d08 LDP	X23, X24, [SP, #48]

0x429d0c LDP	X19, X20, [SP, #16]

0x429d10 LDP	X21, X22, [SP, #32]

0x429d14 LDP	X29, X30, [SP], #368

0x429d18 RET

(476) 0x429d1c LDP	X23, X24, [SP, #48]

(476) 0x429d20 LDP	X25, X26, [SP, #64]

(476) 0x429d24 LDP	X27, X28, [SP, #80]

(476) 0x429d28 LDP	X19, X20, [SP, #16]

(476) 0x429d2c LDP	X21, X22, [SP, #32]

(476) 0x429d30 LDP	X29, X30, [SP], #368

(476) 0x429d34 RET

  (478) 0x429d38 MOVZ	W3, #0

  (478) 0x429d3c SBFM	X1, X1, #0, #31

  (478) 0x429d40 B	429ae8

0x429d44 ADD	W4, W4, #1

0x429d48 MOVZ	W0, #0

0x429d4c B	429778

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:48	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 54% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	2.00	2.00	2.00	2.00	12.17	11.83	12.00	10.50	10.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	2.00	2.00	2.00	2.00	12.17	11.83	12.00	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	9.88
Overall L1	12.17-25.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	22%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

7% of peak load performance is reached (7.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W3, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W1, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W0, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 429d0c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 429d08 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 429d44 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 429d08 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V26.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV V25.2D, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDUP Z29.D, #96	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV V24.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z28.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X3, X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D27, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z31.D, Z27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X3, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X5, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X27, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
DUP V27.2D, V27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X3, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W0, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X0, X5, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W3, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X5, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 429778 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 54% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	2.00	2.00	2.00	2.00	12.17	11.83	12.00	10.50	10.50
cycles	4.00	4.00	4.83	4.83	4.83	4.83	6.00	4.67	2.00	2.00	2.00	2.00	12.17	11.83	12.00	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	9.88
Overall L1	12.17-25.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	22%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

7% of peak load performance is reached (7.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W3, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W1, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W0, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 429d0c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W3, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 429d08 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W4, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 429d44 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W2, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 429d08 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV V26.2D, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMOV V25.2D, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDUP Z29.D, #96	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV V24.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z28.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W2, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X3, X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D27, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z31.D, Z27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X3, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X5, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X27, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
DUP V27.2D, V27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X3, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W0, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X0, X5, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W3, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X5, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 429778 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.10	4.70
▼Loop 476 - PdV.cpp:48-63 - exec–	0.00	0.00
▼Loop 480 - PdV.cpp:50-63 - exec–	0.01	0.01
○Loop 479 - PdV.cpp:51-63 - exec	6.09	4.66
○Loop 477 - PdV.cpp:50-55 - exec	0.00	0.01
○Loop 481 - PdV.cpp:51-63 - exec	0.00	0.00
○Loop 478 - context.h:69-69 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code