OV - exec - Function initialise_chunk(int, global_variables&) [clone ._omp

	Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4]	Module: exec	Source: initialise_chunk.cpp:77-82 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 77 - 82

--------------------------------------------------------------------------------

77: #pragma omp parallel for simd collapse(2)

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x425b20 STP	X29, X30, [SP, #960]!

0x425b24 ADD	X29, SP, #0

0x425b28 STP	X19, X20, [SP, #16]

0x425b2c LDP	W19, W20, [X0, #24]

0x425b30 CMP	W20, #0

0x425b34 B.LE	425cb0

0x425b38 CMP	W19, #0

0x425b3c B.LE	425cb0

0x425b40 STP	X21, X22, [SP, #32]

0x425b44 ORR	X22, XZR, X0

0x425b48 STR	X23, [SP, #48]

0x425b4c MADD	W23, W20, W19, WZR

0x425b50 BL	403aa0

0x425b54 ORR	W21, WZR, W0

0x425b58 BL	403980

0x425b5c UDIV	W1, W23, W21

0x425b60 ORR	W2, WZR, W0

0x425b64 MSUB	W3, W1, W21, W23

0x425b68 CMP	W0, W3

0x425b6c B.CC	425cc8

0x425b70 MADD	W2, W1, W2, W3

0x425b74 ADD	W14, W1, W2

0x425b78 CMP	W2, W14

0x425b7c B.CS	425ca8

0x425b80 UDIV	W8, W2, W19

0x425b84 LDP	D30, D31, [X22]

0x425b88 PTRUE	P6.B, ALL

0x425b8c LDR	X9, [X22, #16]

0x425b90 MSUB	W3, W8, W19, W2

0x425b94 SBFM	X8, X8, #0, #31

0x425b98 SUB	W0, W19, W3

0x425b9c HINT	#0

  (411) 0x425ba0 CMP	W1, W0

  (411) 0x425ba4 CSEL	W1, W1, W0, #9

  (411) 0x425ba8 ADD	W15, W2, W1

  (411) 0x425bac CMP	W2, W15

  (411) 0x425bb0 B.CS	425c8c

  (414) 0x425bb4 ADD	X0, X9, #672

  (414) 0x425bb8 LDR	X4, [X9, #584]

  (414) 0x425bbc FMUL	D29, D31, D30

  (414) 0x425bc0 LDP	X30, X11, [X0]

  (414) 0x425bc4 LDP	X16, X10, [X0, #24]

  (414) 0x425bc8 ADD	X4, X4, X8,LSL #3

  (414) 0x425bcc MADD	X11, X8, X11, XZR

  (414) 0x425bd0 LDR	X12, [X9, #656]

  (414) 0x425bd4 MADD	X10, X8, X10, XZR

  (414) 0x425bd8 LDR	X17, [X9, #552]

  (414) 0x425bdc LDR	X13, [X9, #720]

  (414) 0x425be0 MADD	X12, X8, X12, XZR

  (414) 0x425be4 CMP	W1, #1

  (414) 0x425be8 B.EQ	425cbc

  (414) 0x425bec SBFM	X18, X3, #0, #31

  (414) 0x425bf0 DUP	V28.2D, V29.D[0]

  (414) 0x425bf4 UBFM	W2, W1, #1, #31

  (414) 0x425bf8 ADD	X3, X17, W3,UXTW #3

  (414) 0x425bfc ADD	X7, X12, X18

  (414) 0x425c00 ADD	X6, X11, X18

  (414) 0x425c04 ADD	X5, X10, X18

  (414) 0x425c08 ADD	X7, X30, X7,LSL #3

  (414) 0x425c0c MOVZ	X0, #0

  (414) 0x425c10 ADD	X6, X16, X6,LSL #3

  (414) 0x425c14 UBFM	X2, X2, #60, #59

  (414) 0x425c18 ADD	X5, X13, X5,LSL #3

  (414) 0x425c1c HINT	#0

    (413) 0x425c20 STR	Q28, [X7, X0]

    (413) 0x425c24 LD1R	{V1.2D}, [X4]

    (413) 0x425c28 STR	Q1, [X6, X0]

    (413) 0x425c2c LDR	Q27, [X3, X0]

    (413) 0x425c30 STR	Q27, [X5, X0]

    (413) 0x425c34 ADD	X0, X0, #16

    (413) 0x425c38 CMP	X2, X0

    (413) 0x425c3c B.NE	425c20

  (414) 0x425c40 AND	W0, W1, #1951

  (414) 0x425c44 TBZ	W1, #0, 425c88

  (415) 0x425c48 ORR	W2, WZR, W0

  (415) 0x425c4c ADD	X12, X12, X18

  (415) 0x425c50 LD1RD	{Z0.D}, P6/Z, [X4]

  (415) 0x425c54 DUP	Z29.D, Z29.D[0]

  (415) 0x425c58 ADD	X11, X11, X18

  (415) 0x425c5c ADD	X10, X10, X18

  (415) 0x425c60 SUB	W1, W1, W0

  (415) 0x425c64 ADD	X12, X12, X2

  (415) 0x425c68 WHILELO	P7.D, WZR, W1

  (415) 0x425c6c ST1D	{Z29.D}, P7, [X30, X12,LSL #3]

  (415) 0x425c70 ADD	X11, X11, X2

  (415) 0x425c74 ADD	X0, X18, X2

  (415) 0x425c78 ST1D	{Z0.D}, P7, [X16, X11,LSL #3]

  (415) 0x425c7c LD1D	{Z27.D}, P7/Z, [X17, X0,LSL #3]

  (415) 0x425c80 ADD	X10, X10, X2

  (415) 0x425c84 ST1D	{Z27.D}, P7, [X13, X10,LSL #3]

  (414) 0x425c88 ORR	W2, WZR, W15

  (411) 0x425c8c ADD	X8, X8, #1

  (411) 0x425c90 CMP	W20, W8

  (411) 0x425c94 B.LE	425ca8

  (411) 0x425c98 SUB	W1, W14, W2

  (411) 0x425c9c ORR	W0, WZR, W19

  (411) 0x425ca0 MOVZ	W3, #0

  (411) 0x425ca4 B	425ba0

(410) 0x425ca8 LDR	X23, [SP, #48]

(410) 0x425cac LDP	X21, X22, [SP, #32]

(410) 0x425cb0 LDP	X19, X20, [SP, #16]

(410) 0x425cb4 LDP	X29, X30, [SP], #64

(410) 0x425cb8 RET

  (412) 0x425cbc MOVZ	W0, #0

  (412) 0x425cc0 SBFM	X18, X3, #0, #31

  (412) 0x425cc4 B	425c48

0x425cc8 ADD	W1, W1, #1

0x425ccc MOVZ	W3, #0

0x425cd0 B	425b70

0x425cd4 HINT	#0

0x425cd8 HINT	#0

0x425cdc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.04+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00
cycles	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	4.25
Overall L1	10.00-25.00

Vectorization ratios

all	4%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W19, W20, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 425cb0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W19, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 425cb0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD W23, W20, W19, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 425cc8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W14, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 425ca8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W8, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
LDP D30, D31, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
LDR X9, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB W3, W8, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W0, W19, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 425b70 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00
cycles	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	4.25
Overall L1	10.00-25.00

Vectorization ratios

all	4%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W19, W20, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 425cb0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W19, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 425cb0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD W23, W20, W19, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 425cc8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W14, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 425ca8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W8, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
LDP D30, D31, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
LDR X9, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB W3, W8, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W0, W19, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 425b70 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4]–	0.02	0.02
▼Loop 410 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
○Loop 415 - initialise_chunk.cpp:80-82 - exec	0.00	0.00
▼Loop 414 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
○Loop 413 - initialise_chunk.cpp:80-82 - exec	0.02	0.02
○Loop 412 - context.h:69-69 - exec	0.00	0.00
○Loop 411 - initialise_chunk.cpp:77-80 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code