OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0]	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 74 - 80

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4247e0 STP	X29, X30, [SP, #928]!

0x4247e4 ADD	X29, SP, #0

0x4247e8 STP	X19, X20, [SP, #16]

0x4247ec STP	X21, X22, [SP, #32]

0x4247f0 LDP	W20, W21, [X0, #40]

0x4247f4 CMP	W21, #0

0x4247f8 B.LE	4249ac

0x4247fc CMP	W20, #0

0x424800 B.LE	4249ac

0x424804 MADD	W22, W21, W20, WZR

0x424808 STP	X27, X28, [SP, #80]

0x42480c ORR	X27, XZR, X0

0x424810 BL	403aa0

0x424814 ORR	W19, WZR, W0

0x424818 BL	403980

0x42481c UDIV	W1, W22, W19

0x424820 ORR	W2, WZR, W0

0x424824 MSUB	W3, W1, W19, W22

0x424828 CMP	W0, W3

0x42482c B.CC	4249c8

0x424830 MADD	W2, W1, W2, W3

0x424834 ADD	W22, W1, W2

0x424838 CMP	W2, W22

0x42483c B.CS	4249a8

0x424840 UDIV	W12, W2, W20

0x424844 STP	X23, X24, [SP, #48]

0x424848 PTRUE	P6.B, ALL

0x42484c STP	X25, X26, [SP, #64]

0x424850 LDR	X16, [X27, #32]

0x424854 LDP	X25, X26, [X27]

0x424858 MSUB	W7, W12, W20, W2

0x42485c LDP	X23, X24, [X27, #16]

0x424860 SBFM	X12, X12, #0, #31

0x424864 SUB	W0, W20, W7

  (382) 0x424868 CMP	W1, W0

  (382) 0x42486c CSEL	W1, W1, W0, #9

  (382) 0x424870 ADD	W27, W2, W1

  (382) 0x424874 CMP	W2, W27

  (382) 0x424878 B.CS	424984

  (385) 0x42487c ORR	X0, XZR, X16

  (385) 0x424880 LDR	X28, [X16, #48]

  (385) 0x424884 LDR	X15, [X0], #168

  (385) 0x424888 LDR	X14, [X16, #168]

  (385) 0x42488c MADD	X28, X12, X28, XZR

  (385) 0x424890 LDR	X13, [X16, #216]

  (385) 0x424894 MADD	X15, X12, X15, XZR

  (385) 0x424898 LDR	X9, [X23, #8]

  (385) 0x42489c MADD	X14, X12, X14, XZR

  (385) 0x4248a0 LDR	X8, [X24, #8]

  (385) 0x4248a4 MADD	X13, X12, X13, XZR

  (385) 0x4248a8 LDR	X10, [X25, #8]

  (385) 0x4248ac LDR	X11, [X26, #8]

  (385) 0x4248b0 LDR	X18, [X0, #16]

  (385) 0x4248b4 LDR	X30, [X16, #16]

  (385) 0x4248b8 LDR	X19, [X16, #64]

  (385) 0x4248bc LDR	X17, [X16, #232]

  (385) 0x4248c0 CMP	W1, #1

  (385) 0x4248c4 B.EQ	4249bc

  (385) 0x4248c8 SBFM	X7, X7, #0, #31

  (385) 0x4248cc UBFM	W2, W1, #1, #31

  (385) 0x4248d0 ADD	X6, X28, X7

  (385) 0x4248d4 ADD	X5, X15, X7

  (385) 0x4248d8 ADD	X4, X14, X7

  (385) 0x4248dc ADD	X3, X13, X7

  (385) 0x4248e0 ADD	X6, X19, X6,LSL #3

  (385) 0x4248e4 ADD	X5, X30, X5,LSL #3

  (385) 0x4248e8 MOVZ	X0, #0

  (385) 0x4248ec UBFM	X2, X2, #60, #59

  (385) 0x4248f0 ADD	X4, X18, X4,LSL #3

  (385) 0x4248f4 ADD	X3, X17, X3,LSL #3

  (385) 0x4248f8 HINT	#0

  (385) 0x4248fc HINT	#0

    (384) 0x424900 LD1R	{V28.2D}, [X11]

    (384) 0x424904 STR	Q28, [X6, X0]

    (384) 0x424908 LD1R	{V29.2D}, [X10]

    (384) 0x42490c STR	Q29, [X5, X0]

    (384) 0x424910 LD1R	{V30.2D}, [X9]

    (384) 0x424914 STR	Q30, [X4, X0]

    (384) 0x424918 LD1R	{V31.2D}, [X8]

    (384) 0x42491c STR	Q31, [X3, X0]

    (384) 0x424920 ADD	X0, X0, #16

    (384) 0x424924 CMP	X0, X2

    (384) 0x424928 B.NE	424900

  (385) 0x42492c AND	W2, W1, #1951

  (385) 0x424930 TBZ	W1, #0, 424980

  (386) 0x424934 ORR	W0, WZR, W2

  (386) 0x424938 ADD	X28, X28, X7

  (386) 0x42493c LD1RD	{Z27.D}, P6/Z, [X11]

  (386) 0x424940 LD1RD	{Z26.D}, P6/Z, [X10]

  (386) 0x424944 LD1RD	{Z25.D}, P6/Z, [X9]

  (386) 0x424948 ADD	X15, X15, X7

  (386) 0x42494c ADD	X14, X14, X7

  (386) 0x424950 LD1RD	{Z24.D}, P6/Z, [X8]

  (386) 0x424954 ADD	X13, X13, X7

  (386) 0x424958 SUB	W1, W1, W2

  (386) 0x42495c WHILELO	P7.D, WZR, W1

  (386) 0x424960 ADD	X28, X28, X0

  (386) 0x424964 ADD	X15, X15, X0

  (386) 0x424968 ST1D	{Z27.D}, P7, [X19, X28,LSL #3]

  (386) 0x42496c ST1D	{Z26.D}, P7, [X30, X15,LSL #3]

  (386) 0x424970 ADD	X14, X14, X0

  (386) 0x424974 ADD	X13, X13, X0

  (386) 0x424978 ST1D	{Z25.D}, P7, [X18, X14,LSL #3]

  (386) 0x42497c ST1D	{Z24.D}, P7, [X17, X13,LSL #3]

  (385) 0x424980 ORR	W2, WZR, W27

  (382) 0x424984 ADD	X12, X12, #1

  (382) 0x424988 CMP	W21, W12

  (382) 0x42498c B.LE	4249a0

  (382) 0x424990 SUB	W1, W22, W2

  (382) 0x424994 ORR	W0, WZR, W20

  (382) 0x424998 MOVZ	W7, #0

  (382) 0x42499c B	424868

(381) 0x4249a0 LDP	X23, X24, [SP, #48]

(381) 0x4249a4 LDP	X25, X26, [SP, #64]

(381) 0x4249a8 LDP	X27, X28, [SP, #80]

(381) 0x4249ac LDP	X19, X20, [SP, #16]

(381) 0x4249b0 LDP	X21, X22, [SP, #32]

(381) 0x4249b4 LDP	X29, X30, [SP], #96

(381) 0x4249b8 RET

  (383) 0x4249bc MOVZ	W2, #0

  (383) 0x4249c0 SBFM	X7, X7, #0, #31

  (383) 0x4249c4 B	424934

0x4249c8 ADD	W1, W1, #1

0x4249cc MOVZ	W3, #0

0x4249d0 B	424830

0x4249d4 HINT	#0

0x4249d8 HINT	#0

0x4249dc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.01+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 56% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00
cycles	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	4.63
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4247e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W20, W21, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W21, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4249ac <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4249ac <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W21, W20, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W22, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W19, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4249c8 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W22, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 4249a8 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W12, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X16, [X27, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X26, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W7, W12, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X23, X24, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SBFM X12, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W0, W20, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 424830 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00
cycles	3.50	3.50	3.33	3.42	3.50	3.33	6.00	3.42	0.00	0.00	0.00	0.00	3.33	3.33	3.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	4.63
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4247e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W20, W21, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W21, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4249ac <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4249ac <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W22, W21, W20, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W22, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W3, W1, W19, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4249c8 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W22, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 4249a8 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W12, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X16, [X27, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X25, X26, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W7, W12, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X23, X24, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SBFM X12, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W0, W20, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 424830 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0]–	0.05	0.04
▼Loop 381 - generate_chunk.cpp:74-80 - exec–	0.00	0.00
○Loop 382 - generate_chunk.cpp:74-80 - exec	0.00	0.00
▼Loop 385 - generate_chunk.cpp:74-80 - exec–	0.00	0.00
○Loop 384 - generate_chunk.cpp:77-80 - exec	0.05	0.04
○Loop 383 - context.h:69-69 - exec	0.00	0.00
○Loop 386 - generate_chunk.cpp:77-80 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code