OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage (incl. loops): 4.59% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x424260 STP	X29, X30, [SP, #784]!

0x424264 ADD	X29, SP, #0

0x424268 STP	X19, X20, [SP, #16]

0x42426c ORR	X20, XZR, X0

0x424270 STP	X21, X22, [SP, #32]

0x424274 LDP	W22, W1, [X0, #80]

0x424278 LDP	W0, W4, [X0, #72]

0x42427c ADD	W1, W1, #3

0x424280 ADD	W22, W22, #1

0x424284 ADD	W0, W0, #1

0x424288 STP	W1, W0, [SP, #216]

0x42428c CMP	W22, W1

0x424290 B.GE	424608

0x424294 ADD	W19, W4, #3

0x424298 STP	X23, X24, [SP, #48]

0x42429c SUB	W23, W1, W22

0x4242a0 CMP	W0, W19

0x4242a4 B.GE	424604

0x4242a8 SUB	W0, W19, W0

0x4242ac MADD	W23, W23, W0, WZR

0x4242b0 STR	W0, [SP, #224]

0x4242b4 BL	403aa0

0x4242b8 ORR	W21, WZR, W0

0x4242bc BL	403980

0x4242c0 UDIV	W2, W23, W21

0x4242c4 ORR	W3, WZR, W0

0x4242c8 MSUB	W0, W2, W21, W23

0x4242cc CMP	W3, W0

0x4242d0 B.CC	424640

0x4242d4 MADD	W3, W2, W3, W0

0x4242d8 ADD	W0, W2, W3

0x4242dc STR	W0, [SP, #228]

0x4242e0 CMP	W3, W0

0x4242e4 B.CS	424604

0x4242e8 LDR	W1, [SP, #224]

0x4242ec FMOV	D30, #0.2500000

0x4242f0 STP	X25, X26, [SP, #64]

0x4242f4 STP	X27, X28, [SP, #80]

0x4242f8 UDIV	W0, W3, W1

0x4242fc LDP	X4, X25, [X20, #8]

0x424300 LDR	D31, [X20]

0x424304 STR	X4, [SP, #232]

0x424308 LDP	X5, X26, [X20, #24]

0x42430c MSUB	W1, W0, W1, W3

0x424310 ADD	W0, W0, W22

0x424314 SBFM	X28, X0, #0, #31

0x424318 LDP	X23, X27, [X20, #40]

0x42431c ORR	X22, XZR, X5

0x424320 LDP	X24, X30, [X20, #56]

0x424324 LDR	W0, [SP, #220]

0x424328 ADD	W1, W1, W0

0x42432c SUB	W4, W19, W1

  (374) 0x424330 CMP	W2, W4

  (374) 0x424334 CSEL	W4, W2, W4, #9

  (374) 0x424338 ADD	W0, W3, W4

  (374) 0x42433c STR	W0, [SP, #156]

  (374) 0x424340 CMP	W3, W0

  (374) 0x424344 B.CS	4245e4

  (377) 0x424348 LDR	X7, [SP, #232]

  (377) 0x42434c FMUL	D29, D31, D30

  (377) 0x424350 LDR	X2, [X22]

  (377) 0x424354 LDR	X0, [X23]

  (377) 0x424358 LDR	X3, [X7]

  (377) 0x42435c MADD	X17, X2, X28, XZR

  (377) 0x424360 LDR	X6, [X24]

  (377) 0x424364 MADD	X16, X0, X28, XZR

  (377) 0x424368 LDR	X5, [X25]

  (377) 0x42436c ADD	X8, X2, X17

  (377) 0x424370 MADD	X9, X28, X3, XZR

  (377) 0x424374 LDR	X3, [X26]

  (377) 0x424378 ADD	X0, X0, X16

  (377) 0x42437c MADD	X2, X28, X6, XZR

  (377) 0x424380 LDR	X12, [X25, #16]

  (377) 0x424384 MADD	X5, X28, X5, XZR

  (377) 0x424388 STR	X9, [SP, #208]

  (377) 0x42438c LDR	X7, [X7, #16]

  (377) 0x424390 MADD	X3, X28, X3, XZR

  (377) 0x424394 LDR	X13, [X30, #16]

  (377) 0x424398 LDR	X21, [X22, #16]

  (377) 0x42439c STR	X7, [SP, #144]

  (377) 0x4243a0 LDR	X20, [X23, #16]

  (377) 0x4243a4 LDR	X19, [X26, #16]

  (377) 0x4243a8 LDR	X18, [X27, #16]

  (377) 0x4243ac STP	X12, X5, [SP, #104]

  (377) 0x4243b0 STP	X2, X0, [SP, #128]

  (377) 0x4243b4 STP	X3, X8, [SP, #192]

  (377) 0x4243b8 LDR	X0, [X30]

  (377) 0x4243bc LDR	X2, [X27]

  (377) 0x4243c0 MADD	X11, X28, X0, XZR

  (377) 0x4243c4 ORR	X0, XZR, X13

  (377) 0x4243c8 MADD	X10, X28, X2, XZR

  (377) 0x4243cc ORR	X7, XZR, X11

  (377) 0x4243d0 LDR	X11, [X24, #16]

  (377) 0x4243d4 STP	X7, X13, [SP, #168]

  (377) 0x4243d8 STR	X11, [SP, #120]

  (377) 0x4243dc STR	X10, [SP, #184]

  (377) 0x4243e0 CMP	W4, #1

  (377) 0x4243e4 B.EQ	424634

  (377) 0x4243e8 LDR	X6, [SP, #136]

  (377) 0x4243ec SBFM	X1, X1, #0, #31

  (377) 0x4243f0 DUP	V28.2D, V29.D[0]

  (377) 0x4243f4 UBFM	W2, W4, #1, #31

  (377) 0x4243f8 ADD	X15, X9, X1

  (377) 0x4243fc ADD	X5, X3, X1

  (377) 0x424400 ADD	X11, X8, X1

  (377) 0x424404 ADD	X14, X19, X5,LSL #3

  (377) 0x424408 ADD	X3, X10, X1

  (377) 0x42440c ADD	X13, X18, X3,LSL #3

  (377) 0x424410 ADD	X12, X17, X1

  (377) 0x424414 ADD	X10, X16, X1

  (377) 0x424418 ORR	X5, XZR, X14

  (377) 0x42441c ADD	X12, X21, X12,LSL #3

  (377) 0x424420 ADD	X14, X14, #8

  (377) 0x424424 ADD	X9, X6, X1

  (377) 0x424428 LDR	X6, [SP, #128]

  (377) 0x42442c ADD	X11, X21, X11,LSL #3

  (377) 0x424430 ORR	X3, XZR, X13

  (377) 0x424434 STR	X5, [SP, #160]

  (377) 0x424438 ADD	X10, X20, X10,LSL #3

  (377) 0x42443c ADD	X13, X13, #8

  (377) 0x424440 UBFM	X2, X2, #60, #59

  (377) 0x424444 ADD	X9, X20, X9,LSL #3

  (377) 0x424448 ADD	X8, X6, X1

  (377) 0x42444c LDR	X6, [SP, #112]

  (377) 0x424450 ADD	X5, X6, X1

  (377) 0x424454 ADD	X6, X7, X1

  (377) 0x424458 LDR	X7, [SP, #144]

  (377) 0x42445c ADD	X6, X0, X6,LSL #3

  (377) 0x424460 MOVZ	X0, #0

  (377) 0x424464 ADD	X15, X7, X15,LSL #3

  (377) 0x424468 LDR	X7, [SP, #120]

  (377) 0x42446c ADD	X8, X7, X8,LSL #3

  (377) 0x424470 LDR	X7, [SP, #104]

  (377) 0x424474 ADD	X7, X7, X5,LSL #3

  (377) 0x424478 LDR	X5, [SP, #160]

  (377) 0x42447c HINT	#0

    (376) 0x424480 LDR	Q27, [X11, X0]

    (376) 0x424484 LDR	Q24, [X12, X0]

    (376) 0x424488 LDR	Q23, [X10, X0]

    (376) 0x42448c LDR	Q22, [X9, X0]

    (376) 0x424490 FADD	V24.2D, V27.2D, V24.2D

    (376) 0x424494 LDR	Q21, [X15, X0]

    (376) 0x424498 FADD	V23.2D, V24.2D, V23.2D

    (376) 0x42449c FMUL	V21.2D, V21.2D, V28.2D

    (376) 0x4244a0 FADD	V22.2D, V23.2D, V22.2D

    (376) 0x4244a4 FMUL	V21.2D, V22.2D, V21.2D

    (376) 0x4244a8 STR	Q21, [X8, X0]

    (376) 0x4244ac LDR	Q20, [X14, X0]

    (376) 0x4244b0 LDR	Q19, [X5, X0]

    (376) 0x4244b4 LDR	Q18, [X3, X0]

    (376) 0x4244b8 LDR	Q17, [X13, X0]

    (376) 0x4244bc FADD	V19.2D, V20.2D, V19.2D

    (376) 0x4244c0 LDR	Q16, [X7, X0]

    (376) 0x4244c4 FADD	V18.2D, V19.2D, V18.2D

    (376) 0x4244c8 FMUL	V16.2D, V16.2D, V28.2D

    (376) 0x4244cc FADD	V17.2D, V18.2D, V17.2D

    (376) 0x4244d0 FMUL	V16.2D, V17.2D, V16.2D

    (376) 0x4244d4 STR	Q16, [X6, X0]

    (376) 0x4244d8 ADD	X0, X0, #16

    (376) 0x4244dc CMP	X0, X2

    (376) 0x4244e0 B.NE	424480

  (377) 0x4244e4 AND	W5, W4, #1951

  (377) 0x4244e8 TBZ	W4, #0, 4245e0

  (378) 0x4244ec LDP	X0, X6, [SP, #192]

  (378) 0x4244f0 SUB	W4, W4, W5

  (378) 0x4244f4 WHILELO	P7.D, XZR, X4

  (378) 0x4244f8 ADD	X17, X17, X1

  (378) 0x4244fc DUP	Z29.D, Z29.D[0]

  (378) 0x424500 ADD	X16, X16, X1

  (378) 0x424504 LDR	X12, [SP, #112]

  (378) 0x424508 ADD	X8, X6, X1

  (378) 0x42450c ADD	X3, X0, X1

  (378) 0x424510 LDR	X6, [SP, #208]

  (378) 0x424514 LDR	X0, [SP, #184]

  (378) 0x424518 ADD	X12, X12, X1

  (378) 0x42451c LDR	X11, [SP, #128]

  (378) 0x424520 ADD	X9, X6, X1

  (378) 0x424524 LDP	X6, X4, [SP, #136]

  (378) 0x424528 ADD	X2, X0, X1

  (378) 0x42452c ORR	W0, WZR, W5

  (378) 0x424530 ADD	X3, X3, X0

  (378) 0x424534 ADD	X2, X2, X0

  (378) 0x424538 LDR	X13, [SP, #168]

  (378) 0x42453c ADD	X11, X11, X1

  (378) 0x424540 ADD	X17, X17, X0

  (378) 0x424544 ADD	X7, X19, X3,LSL #3

  (378) 0x424548 LD1D	{Z4.D}, P7/Z, [X21, X17,LSL #3]

  (378) 0x42454c ADD	X10, X6, X1

  (378) 0x424550 ADD	X8, X8, X0

  (378) 0x424554 ADD	X6, X18, X2,LSL #3

  (378) 0x424558 LD1D	{Z6.D}, P7/Z, [X21, X8,LSL #3]

  (378) 0x42455c FADD	Z4.D, P7/M, Z4.D, Z6.D

  (378) 0x424560 ADD	X16, X16, X0

  (378) 0x424564 ADD	X9, X9, X0

  (378) 0x424568 LD1D	{Z5.D}, P7/Z, [X20, X16,LSL #3]

  (378) 0x42456c LD1D	{Z7.D}, P7/Z, [X4, X9,LSL #3]

  (378) 0x424570 FADD	Z4.D, P7/M, Z4.D, Z5.D

  (378) 0x424574 ADD	X11, X11, X0

  (378) 0x424578 ADD	X12, X12, X0

  (378) 0x42457c MOVPRFX	Z3, Z29

  (378) 0x424580 FMUL	Z3.D, P7/M, Z3.D, Z7.D

  (378) 0x424584 ADD	X10, X10, X0

  (378) 0x424588 LD1D	{Z26.D}, P7/Z, [X20, X10,LSL #3]

  (378) 0x42458c FADD	Z4.D, P7/M, Z4.D, Z26.D

  (378) 0x424590 FMUL	Z3.D, P7/M, Z3.D, Z4.D

  (378) 0x424594 ADD	X7, X7, #8

  (378) 0x424598 ADD	X1, X13, X1

  (378) 0x42459c ADD	X6, X6, #8

  (378) 0x4245a0 ADD	X1, X1, X0

  (378) 0x4245a4 LDR	X0, [SP, #120]

  (378) 0x4245a8 ST1D	{Z3.D}, P7, [X0, X11,LSL #3]

  (378) 0x4245ac LD1D	{Z25.D}, P7/Z, [X19, X3,LSL #3]

  (378) 0x4245b0 LD1D	{Z0.D}, P7/Z, [X18, X2,LSL #3]

  (378) 0x4245b4 LD1D	{Z1.D}, P7/Z, [X7, MUL VL]

  (378) 0x4245b8 LD1D	{Z27.D}, P7/Z, [X6, MUL VL]

  (378) 0x4245bc FADD	Z25.D, P7/M, Z25.D, Z1.D

  (378) 0x4245c0 FADD	Z25.D, P7/M, Z25.D, Z0.D

  (378) 0x4245c4 FADD	Z25.D, P7/M, Z25.D, Z27.D

  (378) 0x4245c8 LDR	X0, [SP, #104]

  (378) 0x4245cc LD1D	{Z2.D}, P7/Z, [X0, X12,LSL #3]

  (378) 0x4245d0 FMUL	Z29.D, P7/M, Z29.D, Z2.D

  (378) 0x4245d4 FMUL	Z29.D, P7/M, Z29.D, Z25.D

  (378) 0x4245d8 LDR	X0, [SP, #176]

  (378) 0x4245dc ST1D	{Z29.D}, P7, [X0, X1,LSL #3]

  (377) 0x4245e0 LDR	W3, [SP, #156]

  (374) 0x4245e4 ADD	X28, X28, #1

  (374) 0x4245e8 LDR	W0, [SP, #216]

  (374) 0x4245ec CMP	W0, W28

  (374) 0x4245f0 B.LE	424618

  (374) 0x4245f4 LDR	W0, [SP, #228]

  (374) 0x4245f8 LDP	W1, W4, [SP, #220]

  (374) 0x4245fc SUB	W2, W0, W3

  (374) 0x424600 B	424330

0x424604 LDP	X23, X24, [SP, #48]

0x424608 LDP	X19, X20, [SP, #16]

0x42460c LDP	X21, X22, [SP, #32]

0x424610 LDP	X29, X30, [SP], #240

0x424614 RET

(373) 0x424618 LDP	X23, X24, [SP, #48]

(373) 0x42461c LDP	X25, X26, [SP, #64]

(373) 0x424620 LDP	X27, X28, [SP, #80]

(373) 0x424624 LDP	X19, X20, [SP, #16]

(373) 0x424628 LDP	X21, X22, [SP, #32]

(373) 0x42462c LDP	X29, X30, [SP], #240

(373) 0x424630 RET

  (375) 0x424634 MOVZ	W5, #0

  (375) 0x424638 SBFM	X1, X1, #0, #31

  (375) 0x42463c B	4244ec

0x424640 ADD	W2, W2, #1

0x424644 MOVZ	W0, #0

0x424648 B	4242d4

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	flux_calc(global_variables&)	flux_calc.cpp:53	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 56% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	0.25	0.25	0.25	0.25	7.67	7.67	7.67	5.00	5.00
cycles	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	0.25	0.25	0.25	0.25	7.67	7.67	7.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.50
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #784]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W1, W0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424608 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W4, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424604 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W2, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 424640 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W2, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W2, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 424604 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D30, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X4, X25, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X26, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X28, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDP X23, X27, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X24, X30, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR W0, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4242d4 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 56% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	0.25	0.25	0.25	0.25	7.67	7.67	7.67	5.00	5.00
cycles	4.00	4.00	5.00	5.00	5.00	5.00	6.00	5.00	0.25	0.25	0.25	0.25	7.67	7.67	7.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.50
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #784]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W1, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W1, W0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP W22, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424608 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W4, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB W23, W1, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 424604 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W23, W23, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR W0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W23, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MSUB W0, W2, W21, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 424640 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W2, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W2, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W0, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W3, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 424604 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D30, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UDIV W0, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X4, X25, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X26, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X28, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDP X23, X27, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X24, X30, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR W0, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W4, W19, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4242d4 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.59	3.53
▼Loop 373 - flux_calc.cpp:36-40 - exec–	0.00	0.00
○Loop 378 - flux_calc.cpp:39-40 - exec	0.00	0.01
▼Loop 377 - flux_calc.cpp:38-40 - exec–	0.00	0.01
○Loop 376 - flux_calc.cpp:39-40 - exec	4.58	3.51
○Loop 374 - flux_calc.cpp:38-40 - exec	0.00	0.01
○Loop 375 - context.h:69-69 - exec	0.00	0.00

Report Configuration

Code clean check

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code