OV - exec - Function field_summary(global_variables&, parallel_&) [clone ._omp

	Function: field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]	Module: exec	Source: field_summary.cpp:75-91 [...]	Coverage (incl. loops): 0.32% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 75 - 91

--------------------------------------------------------------------------------

75: #pragma omp parallel for simd reduction(+ : press) reduction(+ : ke) reduction(+ : ie) reduction(+ : mass) reduction(+ : vol)

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x423de0 STP	X29, X30, [SP, #816]!

0x423de4 ADD	X29, SP, #0

0x423de8 STP	X19, X20, [SP, #16]

0x423dec ORR	X19, XZR, X0

0x423df0 STP	X21, X22, [SP, #32]

0x423df4 STP	X23, X24, [SP, #48]

0x423df8 STR	D15, [SP, #88]

0x423dfc LDP	W21, W24, [X0, #48]

0x423e00 LDP	W0, W23, [X0, #56]

0x423e04 SUB	W21, W21, W24

0x423e08 ADD	W21, W21, #1

0x423e0c SUB	W0, W0, W23

0x423e10 ADD	W20, W0, #1

0x423e14 MADD	W21, W0, W21, W21

0x423e18 BL	403aa0

0x423e1c ORR	W22, WZR, W0

0x423e20 BL	403980

0x423e24 SDIV	W1, W21, W22

0x423e28 ORR	W5, WZR, W0

0x423e2c MSUB	W0, W1, W22, W21

0x423e30 CMP	W5, W0

0x423e34 B.LT	424074

(368) 0x423e38 MADD	W5, W1, W5, W0

(368) 0x423e3c ADD	W0, W1, W5

(368) 0x423e40 CMP	W5, W0

(368) 0x423e44 B.GE	424018

(368) 0x423e48 MOVI	D22, #0

(368) 0x423e4c STP	X25, X26, [SP, #64]

(368) 0x423e50 FMOV	D23, #0.2500000

(368) 0x423e54 ADD	W10, W23, #1

(368) 0x423e58 ADD	W11, W24, #1

(368) 0x423e5c FMOV	D16, #0.5000000

(368) 0x423e60 LDR	X1, [X19]

(368) 0x423e64 FMOV	D17, D22

(368) 0x423e68 FMOV	D18, D22

(368) 0x423e6c FMOV	D19, D22

(368) 0x423e70 FMOV	D20, D22

(368) 0x423e74 FMOV	D21, D22

(368) 0x423e78 LDR	X30, [X1]

(368) 0x423e7c LDR	X18, [X1, #16]

(368) 0x423e80 LDR	X17, [X1, #48]

(368) 0x423e84 LDR	X16, [X1, #64]

(368) 0x423e88 LDR	X15, [X1, #96]

(368) 0x423e8c LDR	X14, [X1, #112]

(368) 0x423e90 LDR	X9, [X1, #168]

(368) 0x423e94 LDR	X7, [X1, #184]

(368) 0x423e98 LDR	X8, [X1, #216]

(368) 0x423e9c LDR	X6, [X1, #232]

(368) 0x423ea0 LDR	X13, [X1, #656]

(368) 0x423ea4 LDR	X12, [X1, #672]

(368) 0x423ea8 STR	X27, [SP, #80]

  (369) 0x423eac SDIV	W1, W5, W20

  (369) 0x423eb0 ADD	W2, W1, W11

  (369) 0x423eb4 MSUB	W1, W1, W20, W5

  (369) 0x423eb8 ADD	W5, W5, #1

  (369) 0x423ebc SBFM	X3, X2, #0, #31

  (369) 0x423ec0 ADD	W2, W2, #1

  (369) 0x423ec4 SBFM	X2, X2, #0, #31

  (369) 0x423ec8 MADD	X23, X3, X8, XZR

  (369) 0x423ecc ADD	W1, W1, W10

  (369) 0x423ed0 SBFM	X4, X1, #0, #31

  (369) 0x423ed4 MADD	X22, X3, X9, XZR

  (369) 0x423ed8 ADD	W1, W1, #1

  (369) 0x423edc SBFM	X1, X1, #0, #31

  (369) 0x423ee0 MADD	X21, X2, X8, XZR

  (369) 0x423ee4 ADD	X24, X4, X23

  (369) 0x423ee8 ADD	X23, X23, X1

  (369) 0x423eec MADD	X2, X2, X9, XZR

  (369) 0x423ef0 ADD	X26, X4, X22

  (369) 0x423ef4 ADD	X22, X22, X1

  (369) 0x423ef8 MADD	X25, X3, X13, X4

  (369) 0x423efc LDR	D30, [X6, X24,LSL #3]

  (369) 0x423f00 ADD	X27, X4, X21

  (369) 0x423f04 ADD	X21, X1, X21

  (369) 0x423f08 MADD	X24, X3, X30, X4

  (369) 0x423f0c ADD	X1, X1, X2

  (369) 0x423f10 ADD	X2, X4, X2

  (369) 0x423f14 LDR	D28, [X6, X23,LSL #3]

  (369) 0x423f18 MADD	X23, X17, X3, X4

  (369) 0x423f1c MADD	X3, X15, X3, X4

  (369) 0x423f20 LDR	D31, [X7, X26,LSL #3]

  (369) 0x423f24 FMUL	D27, D30, D30

  (369) 0x423f28 LDR	D29, [X6, X27,LSL #3]

  (369) 0x423f2c LDR	D30, [X7, X22,LSL #3]

  (369) 0x423f30 FMUL	D26, D28, D28

  (369) 0x423f34 LDR	D28, [X7, X2,LSL #3]

  (369) 0x423f38 FMADD	D31, D31, D31, D27

  (369) 0x423f3c LDR	D27, [X6, X21,LSL #3]

  (369) 0x423f40 FMUL	D25, D29, D29

  (369) 0x423f44 FMADD	D26, D30, D30, D26

  (369) 0x423f48 LDR	D24, [X12, X25,LSL #3]

  (369) 0x423f4c FMADD	D31, D31, D23, D21

  (369) 0x423f50 LDR	D30, [X18, X24,LSL #3]

  (369) 0x423f54 FMADD	D28, D28, D28, D25

  (369) 0x423f58 LDR	D29, [X7, X1,LSL #3]

  (369) 0x423f5c FMUL	D27, D27, D27

  (369) 0x423f60 LDR	D25, [X16, X23,LSL #3]

  (369) 0x423f64 FADD	D22, D22, D24

  (369) 0x423f68 FMADD	D31, D26, D23, D31

  (369) 0x423f6c FMUL	D30, D24, D30

  (369) 0x423f70 LDR	D26, [X14, X3,LSL #3]

  (369) 0x423f74 FMADD	D29, D29, D29, D27

  (369) 0x423f78 FMADD	D31, D28, D23, D31

  (369) 0x423f7c FMADD	D18, D30, D25, D18

  (369) 0x423f80 FMUL	D28, D30, D16

  (369) 0x423f84 FMADD	D20, D24, D26, D20

  (369) 0x423f88 FADD	D17, D17, D30

  (369) 0x423f8c FMADD	D31, D29, D23, D31

  (369) 0x423f90 FMADD	D19, D28, D31, D19

  (369) 0x423f94 CMP	W0, W5

  (369) 0x423f98 B.NE	423eac

(368) 0x423f9c ADD	X0, SP, #144

(368) 0x423fa0 PTRUE	P7.B, VL1

(368) 0x423fa4 STR	D20, [SP, #128]

(368) 0x423fa8 FMOV	D31, D21

(368) 0x423fac FMOV	D28, D21

(368) 0x423fb0 STR	D19, [SP, #144]

(368) 0x423fb4 STR	D18, [SP, #160]

(368) 0x423fb8 STR	D17, [SP, #176]

(368) 0x423fbc STR	D22, [SP, #192]

(368) 0x423fc0 LD1D	{Z29.D}, P7/Z, [X0, MUL VL]

(368) 0x423fc4 ADD	X0, SP, #160

(368) 0x423fc8 LD1D	{Z30.D}, P7/Z, [X0, MUL VL]

(368) 0x423fcc FADDA	D31, P7, D31, Z29.D

(368) 0x423fd0 ADD	X0, SP, #176

(368) 0x423fd4 FADDA	D28, P7, D28, Z30.D

(368) 0x423fd8 LD1D	{Z30.D}, P7/Z, [X0, MUL VL]

(368) 0x423fdc LDR	X27, [SP, #80]

(368) 0x423fe0 MOV	V28.D[1], V31.D[0]

(368) 0x423fe4 ADD	X0, SP, #192

(368) 0x423fe8 FMOV	D31, D21

(368) 0x423fec LD1D	{Z27.D}, P7/Z, [X0, MUL VL]

(368) 0x423ff0 FADDA	D31, P7, D31, Z30.D

(368) 0x423ff4 LDP	X25, X26, [SP, #64]

(368) 0x423ff8 FMOV	D30, D21

(368) 0x423ffc ADD	X0, SP, #128

(368) 0x424000 FADDA	D30, P7, D30, Z27.D

(368) 0x424004 LD1D	{Z29.D}, P7/Z, [X0, MUL VL]

(368) 0x424008 FADDA	D21, P7, D21, Z29.D

(368) 0x42400c FMOV	D15, D21

(368) 0x424010 STP	D30, D31, [SP, #112]

(368) 0x424014 B	424024

(368) 0x424018 MOVI	V28.2D, #0

(368) 0x42401c FMOV	D15, D28

(368) 0x424020 STR	Q28, [SP, #112]

(368) 0x424024 STR	Q28, [SP, #96]

(368) 0x424028 BL	403600

(368) 0x42402c LDUR	Q29, [X19, #8]

(368) 0x424030 LDR	Q28, [SP, #112]

(368) 0x424034 LDUR	Q30, [X19, #24]

(368) 0x424038 LDR	D31, [X19, #40]

(368) 0x42403c FADD	V29.2D, V29.2D, V28.2D

(368) 0x424040 LDR	Q28, [SP, #96]

(368) 0x424044 FADD	D31, D31, D15

(368) 0x424048 FADD	V30.2D, V30.2D, V28.2D

(368) 0x42404c STUR	Q29, [X19, #8]

(368) 0x424050 STR	D31, [X19, #40]

(368) 0x424054 STUR	Q30, [X19, #24]

(368) 0x424058 BL	4036d0

(368) 0x42405c LDR	D15, [SP, #88]

(368) 0x424060 LDP	X19, X20, [SP, #16]

(368) 0x424064 LDP	X21, X22, [SP, #32]

(368) 0x424068 LDP	X23, X24, [SP, #48]

(368) 0x42406c LDP	X29, X30, [SP], #208

(368) 0x424070 RET

(368) 0x424074 ADD	W1, W1, #1

(368) 0x424078 MOVZ	W0, #0

(368) 0x42407c B	423e38

Coverage (%)	Name	Source Location	Module
►98.97+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	field_summary.cpp:75-91
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75-91
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	2.33	2.33	2.50	2.50	3.00	2.33	0.50	0.50	0.00	0.00	2.50	2.50	2.00	2.00	2.00
cycles	1.50	1.50	2.33	2.33	2.50	2.50	3.00	2.33	0.50	0.50	0.00	0.00	2.50	2.50	2.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #816]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDP W21, W24, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W23, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, W21, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W0, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W20, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W21, W0, W21, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MSUB W0, W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W5, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 424074 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	field_summary.cpp:75-91
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75-91
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	2.33	2.33	2.50	2.50	3.00	2.33	0.50	0.50	0.00	0.00	2.50	2.50	2.00	2.00	2.00
cycles	1.50	1.50	2.33	2.33	2.50	2.50	3.00	2.33	0.50	0.50	0.00	0.00	2.50	2.50	2.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #816]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDP W21, W24, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W0, W23, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, W21, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W0, W0, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W20, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W21, W0, W21, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W1, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MSUB W0, W1, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W5, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 424074 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]–	0.32	0.25
▼Loop 368 - field_summary.cpp:75-91 - exec–	0.00	0.00
○Loop 369 - context.h:69-69 - exec	0.32	0.25

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code