OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.90% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x422000 STP	X29, X30, [SP, #800]!

0x422004 ADD	X29, SP, #0

0x422008 STP	X19, X20, [SP, #16]

0x42200c ORR	X20, XZR, X0

0x422010 STP	X21, X22, [SP, #32]

0x422014 STP	X23, X24, [SP, #48]

0x422018 STP	X25, X26, [SP, #64]

0x42201c LDP	W22, W24, [X0, #128]

0x422020 LDP	W25, W2, [X0, #120]

0x422024 ADD	W22, W22, #1

0x422028 ADD	W24, W24, #2

0x42202c CMP	W22, W24

0x422030 B.GE	4223e8

0x422034 ADD	W25, W25, #1

0x422038 ADD	W21, W2, #2

0x42203c SUB	W23, W24, W22

0x422040 CMP	W25, W21

0x422044 B.GE	4223e8

0x422048 SUB	W26, W21, W25

0x42204c STP	X27, X28, [SP, #80]

0x422050 MADD	W23, W23, W26, WZR

0x422054 BL	403aa0

0x422058 ORR	W19, WZR, W0

0x42205c BL	403980

0x422060 UDIV	W1, W23, W19

0x422064 MSUB	W2, W1, W19, W23

0x422068 CMP	W0, W2

0x42206c B.CC	4223dc

0x422070 MADD	W0, W1, W0, W2

0x422074 ADD	W27, W1, W0

0x422078 CMP	W0, W27

0x42207c B.CS	4221a8

0x422080 UDIV	W2, W0, W26

0x422084 MOVZ	X3, #32752

0x422088 ADRP	X4,

0x42208c STP	D14, D15, [SP, #144]

0x422090 STP	D8, D9, [SP, #96]

0x422094 FMOV	D31, X3

0x422098 ADRP	X3,

0x42209c LDR	D15, [X4, #3744]

0x4220a0 ADRP	X4,

0x4220a4 STP	D10, D11, [SP, #112]

0x4220a8 MOVI	D10, #0

0x4220ac LDR	D11, [X4, #3888]

0x4220b0 STP	D12, D13, [SP, #128]

0x4220b4 LDR	D9, [X3, #3872]

0x4220b8 LDP	D12, D25, [X20]

0x4220bc MSUB	W19, W2, W26, W0

0x4220c0 ADD	W2, W2, W22

0x4220c4 SBFM	X22, X2, #0, #31

0x4220c8 LDP	D26, D27, [X20, #16]

0x4220cc STR	D31, [SP, #208]

0x4220d0 ADD	W19, W19, W25

0x4220d4 SUB	W2, W21, W19

0x4220d8 HINT	#0

0x4220dc HINT	#0

  (355) 0x4220e0 CMP	W1, W2

  (355) 0x4220e4 CSEL	W1, W1, W2, #9

  (355) 0x4220e8 ADD	W28, W0, W1

  (355) 0x4220ec CMP	W0, W28

  (355) 0x4220f0 B.CS	42238c

  (353) 0x4220f4 FADD	D13, D25, D25

  (353) 0x4220f8 FADD	D14, D26, D26

  (353) 0x4220fc SBFM	X19, X19, #0, #31

  (353) 0x422100 SUB	W1, W1, #1

  (353) 0x422104 FMOV	D8, #-1.0000000

  (353) 0x422108 ADD	X21, X19, #1

  (353) 0x42210c UBFM	X5, X22, #61, #60

  (353) 0x422110 ADD	X23, X1, X21

  (353) 0x422114 HINT	#0

  (353) 0x422118 HINT	#0

  (353) 0x42211c HINT	#0

  (353) 0x422120 LDP	X3, X1, [X20, #72]

  (353) 0x422124 LDR	X2, [X20, #88]

  (353) 0x422128 LDR	X0, [X1]

  (353) 0x42212c LDR	X4, [X1, #16]

  (353) 0x422130 LDR	X1, [X3]

  (353) 0x422134 MADD	X0, X22, X0, X19

  (353) 0x422138 LDR	X3, [X3, #16]

  (353) 0x42213c LDR	D31, [X4, X0,LSL #3]

  (353) 0x422140 MADD	X1, X22, X1, X19

  (353) 0x422144 LDR	X0, [X2]

  (353) 0x422148 LDR	D30, [X3, X1,LSL #3]

  (353) 0x42214c FADD	D31, D31, D31

  (353) 0x422150 LDR	X3, [X2, #16]

  (353) 0x422154 MADD	X0, X22, X0, X19

  (353) 0x422158 LDP	X1, X2, [X20, #48]

  (353) 0x42215c LDR	D0, [X3, X0,LSL #3]

  (353) 0x422160 FDIV	D31, D31, D30

  (353) 0x422164 LDR	X1, [X1, #8]

  (353) 0x422168 LDR	X0, [X2, #8]

  (353) 0x42216c LDR	D24, [X1, X19,LSL #3]

  (353) 0x422170 LDR	D30, [X0, X5]

  (353) 0x422174 FMADD	D0, D0, D0, D31

  (353) 0x422178 FCMP	D0, #0

  (353) 0x42217c B.PL	4221f0

  (353) 0x422180 STP	D27, D26, [SP, #160]

  (353) 0x422184 STP	D25, D24, [SP, #176]

  (353) 0x422188 STR	D30, [SP, #192]

  (353) 0x42218c STR	X5, [SP, #200]

  (353) 0x422190 BL	403ad0

  (353) 0x422194 LDR	D30, [SP, #192]

  (353) 0x422198 LDR	X5, [SP, #200]

  (353) 0x42219c LDP	D27, D26, [SP, #160]

  (353) 0x4221a0 LDP	D25, D24, [SP, #176]

  (353) 0x4221a4 B	4221f4

0x4221a8 MOVZ	X0, #32752

0x4221ac LDP	X27, X28, [SP, #80]

0x4221b0 FMOV	D31, X0

(354) 0x4221b4 ADD	X20, X20, #112

(354) 0x4221b8 LDR	X0, [X20]

  (351) 0x4221bc FMOV	D30, X0

  (351) 0x4221c0 ORR	X1, XZR, X0

  (351) 0x4221c4 FMINNM	D30, D31, D30

  (351) 0x4221c8 FMOV	X2, D30

  (351) 0x4221cc CAS	X1, X2, [X20]

  (351) 0x4221d0 CMP	X0, X1

  (351) 0x4221d4 B.NE	4223f4

(354) 0x4221d8 LDP	X19, X20, [SP, #16]

(354) 0x4221dc LDP	X21, X22, [SP, #32]

(354) 0x4221e0 LDP	X23, X24, [SP, #48]

(354) 0x4221e4 LDP	X25, X26, [SP, #64]

(354) 0x4221e8 LDP	X29, X30, [SP], #224

(354) 0x4221ec RET

  (352) 0x4221f0 FSQRT	D0, D0

  (353) 0x4221f4 LDP	X1, X10, [X20, #96]

  (353) 0x4221f8 FMINNM	D24, D24, D30

  (353) 0x4221fc FMUL	D24, D12, D24

  (353) 0x422200 FMAXNM	D0, D0, D15

  (353) 0x422204 LDP	X3, X7, [X20, #32]

  (353) 0x422208 FDIV	D24, D24, D0

  (353) 0x42220c LDR	X0, [X1]

  (353) 0x422210 LDR	X6, [X1, #16]

  (353) 0x422214 LDR	X1, [X3]

  (353) 0x422218 MADD	X2, X0, X22, XZR

  (353) 0x42221c LDR	X4, [X10]

  (353) 0x422220 ADD	X0, X0, X2

  (353) 0x422224 ADD	X11, X2, X21

  (353) 0x422228 LDR	X8, [X3, #16]

  (353) 0x42222c ADD	X9, X0, X21

  (353) 0x422230 MADD	X1, X22, X1, XZR

  (353) 0x422234 ADD	X3, X2, X19

  (353) 0x422238 LDR	D28, [X6, X11,LSL #3]

  (353) 0x42223c ADD	X0, X0, X19

  (353) 0x422240 MADD	X2, X4, X22, XZR

  (353) 0x422244 LDR	D30, [X6, X9,LSL #3]

  (353) 0x422248 ADD	X12, X1, X21

  (353) 0x42224c ADD	X1, X1, X19

  (353) 0x422250 LDR	D31, [X6, X0,LSL #3]

  (353) 0x422254 ADD	X4, X4, X2

  (353) 0x422258 ADD	X9, X2, X19

  (353) 0x42225c ADD	X11, X4, X19

  (353) 0x422260 ADD	X4, X4, X21

  (353) 0x422264 LDR	D29, [X8, X12,LSL #3]

  (353) 0x422268 ADD	X2, X2, X21

  (353) 0x42226c FADD	D28, D28, D30

  (353) 0x422270 LDR	D30, [X6, X3,LSL #3]

  (353) 0x422274 LDR	X0, [X7]

  (353) 0x422278 LDR	X3, [X10, #16]

  (353) 0x42227c LDR	D21, [X8, X1,LSL #3]

  (353) 0x422280 FMUL	D28, D28, D29

  (353) 0x422284 FADD	D30, D30, D31

  (353) 0x422288 MADD	X1, X0, X22, XZR

  (353) 0x42228c LDR	X6, [X7, #16]

  (353) 0x422290 LDR	D22, [X3, X4,LSL #3]

  (353) 0x422294 ADD	X0, X0, X1

  (353) 0x422298 ADD	X1, X1, X19

  (353) 0x42229c ADD	X0, X0, X19

  (353) 0x4222a0 LDR	D29, [X3, X11,LSL #3]

  (353) 0x4222a4 FMUL	D30, D30, D21

  (353) 0x4222a8 FABS	D23, D28

  (353) 0x4222ac FADD	D31, D28, D10

  (353) 0x4222b0 LDR	X4, [X20, #64]

  (353) 0x4222b4 LDR	D21, [X6, X0,LSL #3]

  (353) 0x4222b8 LDR	D28, [X3, X9,LSL #3]

  (353) 0x4222bc FADD	D29, D29, D22

  (353) 0x4222c0 FSUB	D31, D31, S30

  (353) 0x4222c4 FABS	D30, D30

  (353) 0x4222c8 FMAXNM	D30, D30, D23

  (353) 0x4222cc LDR	D22, [X3, X2,LSL #3]

  (353) 0x4222d0 LDR	X0, [X4]

  (353) 0x4222d4 LDR	D23, [X6, X1,LSL #3]

  (353) 0x4222d8 FMUL	D29, D29, D21

  (353) 0x4222dc FADD	D28, D28, D22

  (353) 0x4222e0 LDR	X1, [X4, #16]

  (353) 0x4222e4 MADD	X0, X22, X0, X19

  (353) 0x4222e8 FADD	D31, D31, D29

  (353) 0x4222ec FABS	D22, D29

  (353) 0x4222f0 LDR	D29, [X1, X0,LSL #3]

  (353) 0x4222f4 FMUL	D28, D28, D23

  (353) 0x4222f8 FADD	D20, D29, D29

  (353) 0x4222fc FMUL	D23, D13, D29

  (353) 0x422300 FSUB	D31, D31, S28

  (353) 0x422304 FMUL	D21, D14, D29

  (353) 0x422308 FABS	D28, D28

  (353) 0x42230c FMUL	D29, D29, D15

  (353) 0x422310 FMAXNM	D28, D28, D22

  (353) 0x422314 FMAXNM	D30, D30, D29

  (353) 0x422318 FMAXNM	D29, D29, D28

  (353) 0x42231c FDIV	D23, D23, D30

  (353) 0x422320 FDIV	D31, D31, D20

  (353) 0x422324 FDIV	D21, D21, D29

  (353) 0x422328 FCMPE	D31, D11

  (353) 0x42232c B.MI	42235c

  (353) 0x422330 LDR	D31, [SP, #208]

  (353) 0x422334 FMINNM	D21, D21, D9

  (353) 0x422338 FMINNM	D23, D23, D21

  (353) 0x42233c FMINNM	D23, D24, D23

  (353) 0x422340 FMINNM	D23, D23, D31

  (353) 0x422344 STR	D23, [SP, #208]

  (353) 0x422348 CMP	X21, X23

  (353) 0x42234c B.EQ	422388

  (353) 0x422350 ORR	X19, XZR, X21

  (353) 0x422354 ADD	X21, X21, #1

  (353) 0x422358 B	422120

  (353) 0x42235c FDIV	D31, D8, D31

  (353) 0x422360 LDR	D30, [SP, #208]

  (353) 0x422364 FMUL	D31, D31, D27

  (353) 0x422368 FMINNM	D31, D31, D9

  (353) 0x42236c FMINNM	D21, D21, D31

  (353) 0x422370 FMINNM	D23, D23, D21

  (353) 0x422374 FMINNM	D23, D23, D24

  (353) 0x422378 FMINNM	D23, D23, D30

  (353) 0x42237c STR	D23, [SP, #208]

  (353) 0x422380 CMP	X21, X23

  (353) 0x422384 B.NE	422350

(354) 0x422388 ORR	W0, WZR, W28

  (355) 0x42238c ADD	X22, X22, #1

  (355) 0x422390 CMP	W24, W22

  (355) 0x422394 B.LE	4223a8

  (355) 0x422398 SUB	W1, W27, W0

  (355) 0x42239c ORR	W2, WZR, W26

  (355) 0x4223a0 ORR	W19, WZR, W25

  (355) 0x4223a4 B	4220e0

(354) 0x4223a8 PTRUE	P7.B, VL1

(354) 0x4223ac ADD	X0, SP, #208

(354) 0x4223b0 DUPM	Z31.D, #9218868437227405312

(354) 0x4223b4 LD1D	{Z30.D}, P7/Z, [X0, MUL VL]

(354) 0x4223b8 PTRUE	P6.B, ALL

(354) 0x4223bc FMINNM	Z31.D, P7/M, Z31.D, Z30.D

(354) 0x4223c0 LDP	D8, D9, [SP, #96]

(354) 0x4223c4 FMINNMV	D31, P6, Z31.D

(354) 0x4223c8 LDP	X27, X28, [SP, #80]

(354) 0x4223cc LDP	D10, D11, [SP, #112]

(354) 0x4223d0 LDP	D12, D13, [SP, #128]

(354) 0x4223d4 LDP	D14, D15, [SP, #144]

(354) 0x4223d8 B	4221b4

0x4223dc ADD	W1, W1, #1

0x4223e0 MOVZ	W2, #0

0x4223e4 B	422070

0x4223e8 MOVZ	X0, #32752

0x4223ec FMOV	D31, X0

0x4223f0 B	4221b4

  (351) 0x4223f4 ORR	X0, XZR, X1

  (351) 0x4223f8 B	4221bc

0x4223fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.05+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:83	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:80	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
36% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.83	5.83	5.83	5.83	6.00	5.67	2.50	2.50	2.00	2.00	6.50	6.17	6.33	3.00	3.00
cycles	4.00	4.00	5.83	5.83	5.83	5.83	6.00	5.67	2.50	2.50	2.00	2.00	6.50	6.17	6.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.88
Overall L1	10.00-25.00

Vectorization ratios

INT

all	14%
load	25%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	25%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

3% of peak load performance is reached (3.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W24, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W25, W2, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W24, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4223e8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W24, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4223e8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W26, W21, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MADD W23, W23, W26, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W2, W1, W19, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4223dc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W0, W1, W0, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W27, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 4221a8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W0, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MOVZ X3, #32752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X4, <43a088>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FMOV D31, X3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X3, <43a098>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [X4, #3744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X4, <43a0a0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVI D10, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D11, [X4, #3888]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D9, [X3, #3872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D12, D25, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MSUB W19, W2, W26, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W2, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X22, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDP D26, D27, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR D31, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD W19, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W21, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
MOVZ X0, #32752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FMOV D31, X0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 422070 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #32752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D31, X0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 4221b4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
36% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 1.00 cycles (25.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	5.83	5.83	5.83	5.83	6.00	5.67	2.50	2.50	2.00	2.00	6.50	6.17	6.33	3.00	3.00
cycles	4.00	4.00	5.83	5.83	5.83	5.83	6.00	5.67	2.50	2.50	2.00	2.00	6.50	6.17	6.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.88
Overall L1	10.00-25.00

Vectorization ratios

INT

all	14%
load	25%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	25%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

3% of peak load performance is reached (3.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W24, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP W25, W2, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W24, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4223e8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W25, W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W21, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W23, W24, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W25, W21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4223e8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W26, W21, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MADD W23, W23, W26, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
BL 403aa0 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403980 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W2, W1, W19, W23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 4223dc <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W0, W1, W0, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W27, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W0, W27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 4221a8 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W2, W0, W26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MOVZ X3, #32752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X4, <43a088>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FMOV D31, X3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X3, <43a098>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [X4, #3744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X4, <43a0a0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVI D10, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D11, [X4, #3888]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D9, [X3, #3872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D12, D25, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MSUB W19, W2, W26, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W2, W2, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X22, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDP D26, D27, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR D31, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD W19, W19, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W21, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
MOVZ X0, #32752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FMOV D31, X0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 422070 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #32752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D31, X0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 4221b4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.90	3.00
▼Loop 354 - calc_dt.cpp:49-75 - exec–	0.00	0.00
○Loop 353 - calc_dt.cpp:50-75 - exec	3.52	2.69
○Loop 352 - calc_dt.cpp:56-56 - exec	0.38	0.29
○Loop 355 - calc_dt.cpp:50-51 - exec	0.00	0.01
○Loop 351 - calc_dt.cpp:49-49 - exec	0.00	0.00

Report Configuration

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code