OV - exec - Loop 739

	Loop Id: 739	Module: exec	Source: viscosity.cpp:37-64 [...]	Coverage: 3.66%

0x43b740 MOVPRFX	Z23, Z26

0x43b744 SDIV	Z23.D, P0/M, Z23.D, Z1.D

0x43b748 SUB	X20, X29, #64

0x43b74c DECD	X6, ALL

0x43b750 LDR	Z0, [X20, #510, MUL VL]    [23]

0x43b754 ADD	Z27.D, Z0.D, Z23.D

0x43b758 LDR	Z0, [X20, #509, MUL VL]    [23]

0x43b75c MOVPRFX	Z28, Z26

0x43b760 MLS	Z28.D, P0/M, Z23.D, Z1.D

0x43b764 MOVPRFX	Z29, Z27

0x43b768 SXTW	Z29.D, P0/M, Z27.D

0x43b76c ADD	Z30.D, Z0.D, Z28.D

0x43b770 MUL	Z0.D, Z4.D, Z29.D

0x43b774 ADR	Z2.D, [Z19, Z0.D,LSL #3]    [27]

0x43b778 ORR	Z0.D, Z27.D, Z27.D

0x43b77c ADD	Z0.D, Z0.D, #1

0x43b780 ADR	Z9.D, [Z2, Z30.D,SXTW #3]    [18]

0x43b784 SXTW	Z0.D, P0/M, Z0.D

0x43b788 LD1D	{Z15.D}, P0/Z, [V9.D]    [9]

0x43b78c MUL	Z8.D, Z5.D, Z0.D

0x43b790 MUL	Z31.D, Z4.D, Z0.D

0x43b794 MUL	Z0.D, Z6.D, Z0.D

0x43b798 ADR	Z12.D, [Z20, Z8.D,LSL #3]    [3]

0x43b79c MUL	Z8.D, Z5.D, Z29.D

0x43b7a0 ADR	Z31.D, [Z19, Z31.D,LSL #3]    [27]

0x43b7a4 ADR	Z0.D, [Z21, Z0.D,LSL #3]    [5]

0x43b7a8 ADR	Z11.D, [Z31, Z30.D,SXTW #3]    [6]

0x43b7ac ADR	Z13.D, [Z12, Z30.D,SXTW #3]    [8]

0x43b7b0 ADR	Z0.D, [Z0, Z30.D,SXTW #3]    [2]

0x43b7b4 LD1D	{Z7.D}, P0/Z, [V11.D]    [4]

0x43b7b8 LD1D	{Z11.D}, P0/Z, [V13.D]    [10]

0x43b7bc ADR	Z14.D, [Z20, Z8.D,LSL #3]    [3]

0x43b7c0 ORR	Z8.D, Z30.D, Z30.D

0x43b7c4 ADD	Z8.D, Z8.D, #1

0x43b7c8 ADR	Z3.D, [Z14, Z30.D,SXTW #3]    [12]

0x43b7cc LD1D	{Z0.D}, P0/Z, [V0.D]    [1]

0x43b7d0 ADR	Z2.D, [Z2, Z8.D,SXTW #3]    [18]

0x43b7d4 ADR	Z12.D, [Z12, Z8.D,SXTW #3]    [8]

0x43b7d8 LD1D	{Z13.D}, P0/Z, [V3.D]    [32]

0x43b7dc ADR	Z3.D, [Z14, Z8.D,SXTW #3]    [12]

0x43b7e0 FADD	Z9.D, Z15.D, Z7.D

0x43b7e4 LD1D	{Z10.D}, P0/Z, [V2.D]    [17]

0x43b7e8 ADR	Z2.D, [Z31, Z8.D,SXTW #3]    [6]

0x43b7ec LD1D	{Z2.D}, P0/Z, [V2.D]    [16]

0x43b7f0 LD1D	{Z12.D}, P0/Z, [V12.D]    [7]

0x43b7f4 LD1D	{Z14.D}, P0/Z, [V3.D]    [21]

0x43b7f8 FADD	Z16.D, Z11.D, Z12.D

0x43b7fc FADD	Z3.D, Z13.D, Z14.D

0x43b800 FADD	Z31.D, Z10.D, Z2.D

0x43b804 FSUB	Z31.D, Z31.D, Z9.D

0x43b808 FSUB	Z9.D, Z16.D, Z3.D

0x43b80c LDR	Z3, [X20, #507, MUL VL]    [23]

0x43b810 MUL	Z16.D, Z6.D, Z29.D

0x43b814 ADR	Z16.D, [Z21, Z16.D,LSL #3]    [5]

0x43b818 ADD	Z3.D, Z3.D, Z23.D

0x43b81c SXTW	Z3.D, P0/M, Z3.D

0x43b820 MUL	Z3.D, Z6.D, Z3.D

0x43b824 ADR	Z3.D, [Z21, Z3.D,LSL #3]    [5]

0x43b828 ADR	Z23.D, [Z3, Z30.D,SXTW #3]    [20]

0x43b82c FADD	Z3.D, Z2.D, Z7.D

0x43b830 MUL	Z2.D, Z17.D, Z29.D

0x43b834 MUL	Z7.D, Z18.D, Z29.D

0x43b838 LDR	Z29, [X20, #508, MUL VL]    [23]

0x43b83c FSUB	Z3.D, Z3.D, Z15.D

0x43b840 LD1D	{Z23.D}, P0/Z, [V23.D]    [11]

0x43b844 FSUB	Z3.D, Z3.D, Z10.D

0x43b848 ADR	Z2.D, [Z24, Z2.D,LSL #3]    [13]

0x43b84c ADR	Z7.D, [Z25, Z7.D,LSL #3]    [22]

0x43b850 ADD	Z28.D, Z29.D, Z28.D

0x43b854 FADD	Z29.D, Z12.D, Z14.D

0x43b858 FMUL	Z3.D, P0/M, Z3.D, #0

0x43b85c ADR	Z2.D, [Z2, Z30.D,SXTW #3]    [15]

0x43b860 ADR	Z15.D, [Z7, Z30.D,SXTW #3]    [24]

0x43b864 LD1D	{Z7.D}, P0/Z, [X12, Z30.D,SXTW #3]    [25]

0x43b868 ADR	Z28.D, [Z16, Z28.D,SXTW #3]    [31]

0x43b86c ADR	Z16.D, [Z16, Z8.D,SXTW #3]    [31]

0x43b870 FSUB	Z29.D, Z29.D, Z13.D

0x43b874 LD1D	{Z30.D}, P0/Z, [X12, Z8.D,SXTW #3]    [25]

0x43b878 LD1D	{Z28.D}, P0/Z, [V28.D]    [26]

0x43b87c LD1D	{Z16.D}, P0/Z, [V16.D]    [30]

0x43b880 FSUB	Z29.D, Z29.D, Z11.D

0x43b884 FSUB	Z0.D, Z0.D, Z23.D

0x43b888 FMUL	Z29.D, P0/M, Z29.D, #0

0x43b88c FADD	Z30.D, Z7.D, Z30.D

0x43b890 FDIV	Z29.D, P0/M, Z29.D, Z7.D

0x43b894 FSUB	Z16.D, Z16.D, Z28.D

0x43b898 LD1D	{Z28.D}, P0/Z, [X13, Z27.D,SXTW #3]    [28]

0x43b89c LD1D	{Z27.D}, P0/Z, [X16, Z27.D,SXTW #3]    [29]

0x43b8a0 FDIV	Z16.D, P0/M, Z16.D, Z30.D

0x43b8a4 MOVPRFX	Z30, Z9

0x43b8a8 FMUL	Z30.D, P0/M, Z30.D, #0

0x43b8ac FADD	Z23.D, Z28.D, Z27.D

0x43b8b0 FDIV	Z3.D, P0/M, Z3.D, Z28.D

0x43b8b4 MOVPRFX	Z27, Z31

0x43b8b8 FMUL	Z27.D, P0/M, Z27.D, #0

0x43b8bc FDIV	Z30.D, P0/M, Z30.D, Z28.D

0x43b8c0 FDIV	Z0.D, P0/M, Z0.D, Z23.D

0x43b8c4 FDIV	Z27.D, P0/M, Z27.D, Z7.D

0x43b8c8 FCMLT	P2.D, P0/Z, Z16.D, #0

0x43b8cc FADD	Z3.D, Z3.D, Z29.D

0x43b8d0 FMUL	Z29.D, Z9.D, Z28.D

0x43b8d4 FMUL	Z23.D, Z0.D, Z0.D

0x43b8d8 FMUL	Z3.D, Z3.D, Z16.D

0x43b8dc FMLA	Z29.D, P0/M, Z7.D, Z31.D

0x43b8e0 FMUL	Z31.D, Z16.D, Z16.D

0x43b8e4 FABS	Z16.D, P0/M, Z16.D

0x43b8e8 FMUL	Z30.D, Z30.D, Z23.D

0x43b8ec FMAXNM	Z16.D, P0/M, Z16.D, Z22.D

0x43b8f0 FADD	Z23.D, Z31.D, Z23.D

0x43b8f4 FCMGE	P1.D, P0/Z, Z29.D, #0

0x43b8f8 FMAD	Z27.D, P0/M, Z31.D, Z30.D

0x43b8fc FMAXNM	Z23.D, P0/M, Z23.D, Z22.D

0x43b900 FMAD	Z3.D, P0/M, Z0.D, Z27.D

0x43b904 MOVPRFX	Z27, Z16

0x43b908 FNEG	Z27.D, P0/M, Z16.D

0x43b90c FABS	Z0.D, P0/M, Z0.D

0x43b910 SEL	Z16.D, P2, Z27.D, Z16.D

0x43b914 FMAXNM	Z0.D, P0/M, Z0.D, Z22.D

0x43b918 FCMLT	P2.D, P0/Z, Z16.D, #0

0x43b91c FDIV	Z3.D, P0/M, Z3.D, Z23.D

0x43b920 MOVPRFX	Z23, Z0

0x43b924 FNEG	Z23.D, P0/M, Z0.D

0x43b928 SEL	Z0.D, P2, Z23.D, Z0.D

0x43b92c FMUL	Z23.D, Z0.D, Z0.D

0x43b930 FMLA	Z23.D, P0/M, Z16.D, Z16.D

0x43b934 FSQRT	Z23.D, P0/M, Z23.D

0x43b938 FCMGT	P2.D, P0/Z, Z3.D, #0

0x43b93c EOR	P2.B, P0/Z, P2.B, P0.B

0x43b940 BIC	P1.B, P2/Z, P2.B, P1.B

0x43b944 LD1D	{Z2.D}, P1/Z, [V2.D]    [14]

0x43b948 FMUL	Z7.D, Z7.D, Z23.D

0x43b94c FADD	Z2.D, Z2.D, Z2.D

0x43b950 FDIV	Z7.D, P0/M, Z7.D, Z16.D

0x43b954 FMUL	Z16.D, Z28.D, Z23.D

0x43b958 FDIVR	Z0.D, P0/M, Z0.D, Z16.D

0x43b95c FABS	Z7.D, P0/M, Z7.D

0x43b960 FABS	Z0.D, P0/M, Z0.D

0x43b964 FMINNM	Z0.D, P0/M, Z0.D, Z7.D

0x43b968 FMUL	Z0.D, Z0.D, Z0.D

0x43b96c FMUL	Z0.D, Z0.D, Z2.D

0x43b970 DUP	Z2.D, #0

0x43b974 FMUL	Z0.D, Z3.D, Z0.D

0x43b978 FMUL	Z0.D, Z3.D, Z0.D

0x43b97c SEL	Z0.D, P1, Z0.D, Z2.D

0x43b980 ST1D	{Z0.D}, P0, [V15.D]    [19]

0x43b984 LDR	Z0, [X20, #511, MUL VL]    [23]

0x43b988 ADD	Z26.D, Z26.D, Z0.D

0x43b98c CBNZ	X6, 43b740

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 37 - 64

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26 - 3.10
Bottlenecks	P8, P10,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:69-69,viscosity.cpp:37-64
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	39.34 - 97.02
CQA cycles if no scalar integer	39.34 - 97.02
CQA cycles if FP arith vectorized	39.34 - 97.02
CQA cycles if fully vectorized	39.34 - 97.02
Front-end cycles	17.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	31.25
P9 cycles	31.25
P10 cycles	31.25
P11 cycles	31.25
P12 cycles	7.83
P13 cycles	7.50
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	39.34 - 97.02
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	148.00
Nb uops	139.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.69 - 1.09
Nb FLOP add-sub	38.00
Nb FLOP mul	32.00
Nb FLOP fma	8.00
Nb FLOP div	18.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.79 - 9.36
Bytes prefetched	0.00
Bytes loaded	352.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	20.00
Stride indirect	12.00
Vectorization ratio all	78.08
Vectorization ratio load	48.89
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.94
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	89.94
Vector-efficiency ratio load	74.44
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	76.47
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.60

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26 - 3.10
Bottlenecks	P8, P10,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:69-69,viscosity.cpp:37-64
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	39.34 - 97.02
CQA cycles if no scalar integer	39.34 - 97.02
CQA cycles if FP arith vectorized	39.34 - 97.02
CQA cycles if fully vectorized	39.34 - 97.02
Front-end cycles	17.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	31.25
P9 cycles	31.25
P10 cycles	31.25
P11 cycles	31.25
P12 cycles	7.83
P13 cycles	7.50
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	39.34 - 97.02
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	148.00
Nb uops	139.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.69 - 1.09
Nb FLOP add-sub	38.00
Nb FLOP mul	32.00
Nb FLOP fma	8.00
Nb FLOP div	18.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.79 - 9.36
Bytes prefetched	0.00
Bytes loaded	352.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	20.00
Stride indirect	12.00
Vectorization ratio all	78.08
Vectorization ratio load	48.89
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.94
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	89.94
Vector-efficiency ratio load	74.44
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	76.47
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.60

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37-64

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 89% of vector register length is used (average across all VPU instructions).

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 106 FP arithmetical operations:

46: addition or subtraction (8 inside FMA instructions)
40: multiply (8 inside FMA instructions)
18: divide
2: square root

The binary loop is loading 352 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	148
loop length	592
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	2.00	1.00	31.25	31.25	31.25	31.25	7.83	7.50	7.67	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	2.00	1.00	31.25	31.25	31.25	31.25	7.83	7.50	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	39.34-97.02
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.38
Data deps.	2.00
Overall L1	39.34-97.02

Vectorization ratios

INT

all	61%
load	48%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	78%
load	48%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 97.02 cycles. At this rate:

3% of peak load performance is reached (3.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43b740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z23, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z23.D, P0/M, Z23.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X20, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X6, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X20, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z27.D, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X20, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z28, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z28.D, P0/M, Z23.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z29.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z0.D, Z4.D, Z29.D																					vect (100.0%)
ADR Z2.D, [Z19, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR Z0.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z0.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z9.D, [Z2, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SXTW Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z15.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z8.D, Z5.D, Z0.D																					vect (100.0%)
MUL Z31.D, Z4.D, Z0.D																					vect (100.0%)
MUL Z0.D, Z6.D, Z0.D																					vect (100.0%)
ADR Z12.D, [Z20, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z8.D, Z5.D, Z29.D																					vect (100.0%)
ADR Z31.D, [Z19, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z21, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z11.D, [Z31, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z12, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z7.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z11.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z14.D, [Z20, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR Z8.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z8.D, Z8.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z3.D, [Z14, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z2.D, [Z2, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z13.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z3.D, [Z14, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z9.D, Z15.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z10.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z2.D, [Z31, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z16.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z3.D, Z13.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z31.D, Z10.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z31.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z9.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z3, [X20, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z16.D, Z6.D, Z29.D																					vect (100.0%)
ADR Z16.D, [Z21, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z3.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z3.D, P0/M, Z3.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z3.D, Z6.D, Z3.D																					vect (100.0%)
ADR Z3.D, [Z21, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z23.D, [Z3, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z3.D, Z2.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z2.D, Z17.D, Z29.D																					vect (100.0%)
MUL Z7.D, Z18.D, Z29.D																					vect (100.0%)
LDR Z29, [X20, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FSUB Z3.D, Z3.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z3.D, Z3.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z2.D, [Z24, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z7.D, [Z25, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z29.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z3.D, P0/M, Z3.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z2.D, [Z2, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z15.D, [Z7, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z7.D}, P0/Z, [X12, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z28.D, [Z16, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z16, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB Z29.D, Z29.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z30.D}, P0/Z, [X12, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V28.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z29.D, Z29.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z0.D, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z29.D, P0/M, Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z30.D, Z7.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV Z29.D, P0/M, Z29.D, Z7.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB Z16.D, Z16.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z28.D}, P0/Z, [X13, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z27.D}, P0/Z, [X16, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FDIV Z16.D, P0/M, Z16.D, Z30.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z30, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMUL Z30.D, P0/M, Z30.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z23.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z27, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMUL Z27.D, P0/M, Z27.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV Z30.D, P0/M, Z30.D, Z28.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z0.D, P0/M, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z27.D, P0/M, Z27.D, Z7.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FCMLT P2.D, P0/Z, Z16.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FADD Z3.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z29.D, Z9.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z23.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z3.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z29.D, P0/M, Z7.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z31.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FABS Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z30.D, Z30.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAXNM Z16.D, P0/M, Z16.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z23.D, Z31.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P0/Z, Z29.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FMAD Z27.D, P0/M, Z31.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMAXNM Z23.D, P0/M, Z23.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAD Z3.D, P0/M, Z0.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MOVPRFX Z27, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z27.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z16.D, P2, Z27.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM Z0.D, P0/M, Z0.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMLT P2.D, P0/Z, Z16.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z23.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z0.D, P2, Z23.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z23.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z23.D, P0/M, Z16.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FSQRT Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FCMGT P2.D, P0/Z, Z3.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
BIC P1.B, P2/Z, P2.B, P1.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z2.D}, P1/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z7.D, Z7.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV Z7.D, P0/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z16.D, Z28.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FABS Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
DUP Z2.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FMUL Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
SEL Z0.D, P1, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z0.D}, P0, [V15.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z26.D, Z26.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X6, 43b740 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37-64

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 89% of vector register length is used (average across all VPU instructions).

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 106 FP arithmetical operations:

46: addition or subtraction (8 inside FMA instructions)
40: multiply (8 inside FMA instructions)
18: divide
2: square root

The binary loop is loading 352 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	148
loop length	592
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	2.00	1.00	31.25	31.25	31.25	31.25	7.83	7.50	7.67	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	2.00	1.00	31.25	31.25	31.25	31.25	7.83	7.50	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	39.34-97.02
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.38
Data deps.	2.00
Overall L1	39.34-97.02

Vectorization ratios

INT

all	61%
load	48%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	78%
load	48%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 97.02 cycles. At this rate:

3% of peak load performance is reached (3.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43b740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z23, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z23.D, P0/M, Z23.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X20, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X6, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X20, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z27.D, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X20, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z28, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z28.D, P0/M, Z23.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z29.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z0.D, Z4.D, Z29.D																					vect (100.0%)
ADR Z2.D, [Z19, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR Z0.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z0.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z9.D, [Z2, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SXTW Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z15.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z8.D, Z5.D, Z0.D																					vect (100.0%)
MUL Z31.D, Z4.D, Z0.D																					vect (100.0%)
MUL Z0.D, Z6.D, Z0.D																					vect (100.0%)
ADR Z12.D, [Z20, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z8.D, Z5.D, Z29.D																					vect (100.0%)
ADR Z31.D, [Z19, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z21, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z11.D, [Z31, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z12, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z7.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z11.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z14.D, [Z20, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR Z8.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z8.D, Z8.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z3.D, [Z14, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z2.D, [Z2, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z13.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z3.D, [Z14, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z9.D, Z15.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z10.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z2.D, [Z31, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z16.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z3.D, Z13.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z31.D, Z10.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z31.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z9.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z3, [X20, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z16.D, Z6.D, Z29.D																					vect (100.0%)
ADR Z16.D, [Z21, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z3.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z3.D, P0/M, Z3.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z3.D, Z6.D, Z3.D																					vect (100.0%)
ADR Z3.D, [Z21, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z23.D, [Z3, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z3.D, Z2.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z2.D, Z17.D, Z29.D																					vect (100.0%)
MUL Z7.D, Z18.D, Z29.D																					vect (100.0%)
LDR Z29, [X20, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FSUB Z3.D, Z3.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z3.D, Z3.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z2.D, [Z24, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z7.D, [Z25, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z29.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z3.D, P0/M, Z3.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z2.D, [Z2, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z15.D, [Z7, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z7.D}, P0/Z, [X12, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z28.D, [Z16, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z16, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB Z29.D, Z29.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z30.D}, P0/Z, [X12, Z8.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V28.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z29.D, Z29.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z0.D, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z29.D, P0/M, Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z30.D, Z7.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV Z29.D, P0/M, Z29.D, Z7.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB Z16.D, Z16.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z28.D}, P0/Z, [X13, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z27.D}, P0/Z, [X16, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FDIV Z16.D, P0/M, Z16.D, Z30.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z30, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMUL Z30.D, P0/M, Z30.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z23.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z28.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z27, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMUL Z27.D, P0/M, Z27.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV Z30.D, P0/M, Z30.D, Z28.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z0.D, P0/M, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z27.D, P0/M, Z27.D, Z7.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FCMLT P2.D, P0/Z, Z16.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FADD Z3.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z29.D, Z9.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z23.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z3.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z29.D, P0/M, Z7.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z31.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FABS Z16.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z30.D, Z30.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAXNM Z16.D, P0/M, Z16.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z23.D, Z31.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P0/Z, Z29.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FMAD Z27.D, P0/M, Z31.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMAXNM Z23.D, P0/M, Z23.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAD Z3.D, P0/M, Z0.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MOVPRFX Z27, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z27.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z16.D, P2, Z27.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM Z0.D, P0/M, Z0.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMLT P2.D, P0/Z, Z16.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z23.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z0.D, P2, Z23.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z23.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z23.D, P0/M, Z16.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FSQRT Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FCMGT P2.D, P0/Z, Z3.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
BIC P1.B, P2/Z, P2.B, P1.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z2.D}, P1/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z7.D, Z7.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIV Z7.D, P0/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z16.D, Z28.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FABS Z7.D, P0/M, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABS Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
DUP Z2.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FMUL Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
SEL Z0.D, P1, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ST1D {Z0.D}, P0, [V15.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z26.D, Z26.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X6, 43b740 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code