OV - exec - Loop 309

	Loop Id: 309	Module: exec	Source: PdV.cpp:70-83 [...]	Coverage: 6.90%

0x4287ac MOVPRFX	Z0, Z14

0x4287b0 SDIV	Z0.D, P0/M, Z0.D, Z1.D

0x4287b4 SUB	X11, X29, #64

0x4287b8 DECD	X10, ALL

0x4287bc LDR	Z3, [X11, #510, MUL VL]    [33]

0x4287c0 LDR	Z4, [X11, #509, MUL VL]    [33]

0x4287c4 MOVPRFX	Z2, Z14

0x4287c8 MLS	Z2.D, P0/M, Z0.D, Z1.D

0x4287cc ADD	Z0.D, Z3.D, Z0.D

0x4287d0 MOVPRFX	Z15, Z0

0x4287d4 SXTW	Z15.D, P0/M, Z0.D

0x4287d8 ADD	Z0.D, Z0.D, #1

0x4287dc MUL	Z10.D, Z5.D, Z15.D

0x4287e0 MUL	Z3.D, Z6.D, Z15.D

0x4287e4 ADD	Z29.D, Z4.D, Z2.D

0x4287e8 ADR	Z2.D, [Z26, Z10.D,LSL #3]    [32]

0x4287ec ADR	Z3.D, [Z27, Z3.D,LSL #3]    [34]

0x4287f0 ADR	Z10.D, [Z2, Z29.D,SXTW #3]    [55]

0x4287f4 ADR	Z4.D, [Z3, Z29.D,SXTW #3]    [61]

0x4287f8 LD1D	{Z18.D}, P0/Z, [V10.D]    [7]

0x4287fc MOVPRFX	Z10, Z0

0x428800 SXTW	Z10.D, P0/M, Z0.D

0x428804 LD1D	{Z4.D}, P0/Z, [V4.D]    [4]

0x428808 MUL	Z0.D, Z5.D, Z10.D

0x42880c ADR	Z19.D, [Z26, Z0.D,LSL #3]    [32]

0x428810 ADR	Z0.D, [Z19, Z29.D,SXTW #3]    [50]

0x428814 LD1D	{Z20.D}, P0/Z, [V0.D]    [3]

0x428818 DUP	Z0.D, #8

0x42881c ADR	Z0.D, [Z0, Z29.D,SXTW #3]    [2]

0x428820 ADD	Z2.D, Z2.D, Z0.D

0x428824 ADD	Z19.D, Z19.D, Z0.D

0x428828 ADD	Z3.D, Z3.D, Z0.D

0x42882c LD1D	{Z21.D}, P0/Z, [V2.D]    [54]

0x428830 LD1D	{Z19.D}, P0/Z, [V19.D]    [49]

0x428834 LD1D	{Z3.D}, P0/Z, [V3.D]    [60]

0x428838 LDR	Z2, [X11, #508, MUL VL]    [33]

0x42883c FADD	Z18.D, Z18.D, Z20.D

0x428840 MUL	Z20.D, Z6.D, Z10.D

0x428844 FADD	Z4.D, Z18.D, Z4.D

0x428848 ADR	Z20.D, [Z27, Z20.D,LSL #3]    [34]

0x42884c MUL	Z2.D, Z2.D, Z15.D

0x428850 FADD	Z19.D, Z21.D, Z19.D

0x428854 ADR	Z21.D, [Z20, Z29.D,SXTW #3]    [10]

0x428858 FADD	Z3.D, Z19.D, Z3.D

0x42885c ADD	Z19.D, Z20.D, Z0.D

0x428860 MUL	Z20.D, Z16.D, Z15.D

0x428864 ADR	Z2.D, [Z25, Z2.D,LSL #3]    [27]

0x428868 LD1D	{Z21.D}, P0/Z, [V21.D]    [15]

0x42886c ADR	Z18.D, [Z2, Z29.D,SXTW #3]    [53]

0x428870 ADD	Z2.D, Z2.D, Z0.D

0x428874 LD1D	{Z19.D}, P0/Z, [V19.D]    [47]

0x428878 LD1D	{Z18.D}, P0/Z, [V18.D]    [36]

0x42887c LD1D	{Z2.D}, P0/Z, [V2.D]    [52]

0x428880 ADR	Z20.D, [Z31, Z20.D,LSL #3]    [16]

0x428884 FADD	Z4.D, Z4.D, Z21.D

0x428888 ADR	Z21.D, [Z20, Z29.D,SXTW #3]    [9]

0x42888c ADD	Z20.D, Z20.D, Z0.D

0x428890 FADD	Z3.D, Z3.D, Z19.D

0x428894 LD1D	{Z21.D}, P0/Z, [V21.D]    [14]

0x428898 LD1D	{Z20.D}, P0/Z, [V20.D]    [8]

0x42889c FMUL	Z4.D, Z18.D, Z4.D

0x4288a0 FMUL	Z2.D, Z2.D, Z3.D

0x4288a4 FMUL	Z3.D, Z4.D, Z28.D

0x4288a8 LD1RD	{Z4.D}, P0/Z, [X8]    [51]

0x4288ac FMUL	Z2.D, Z2.D, Z28.D

0x4288b0 FADD	Z20.D, Z21.D, Z20.D

0x4288b4 MUL	Z21.D, Z17.D, Z15.D

0x4288b8 FMUL	Z3.D, Z4.D, Z3.D

0x4288bc FMUL	Z2.D, Z4.D, Z2.D

0x4288c0 FSUB	Z2.D, Z2.D, Z3.D

0x4288c4 ADR	Z19.D, [Z8, Z21.D,LSL #3]    [17]

0x4288c8 ADR	Z21.D, [Z19, Z29.D,SXTW #3]    [45]

0x4288cc ADD	Z19.D, Z19.D, Z0.D

0x4288d0 LD1D	{Z21.D}, P0/Z, [V21.D]    [13]

0x4288d4 LD1D	{Z19.D}, P0/Z, [V19.D]    [44]

0x4288d8 FADD	Z20.D, Z20.D, Z21.D

0x4288dc MUL	Z21.D, Z7.D, Z15.D

0x4288e0 FADD	Z19.D, Z20.D, Z19.D

0x4288e4 MUL	Z20.D, Z16.D, Z10.D

0x4288e8 ADR	Z21.D, [Z30, Z21.D,LSL #3]    [11]

0x4288ec ADR	Z21.D, [Z21, Z29.D,SXTW #3]    [48]

0x4288f0 LD1D	{Z21.D}, P0/Z, [V21.D]    [46]

0x4288f4 FMUL	Z18.D, Z21.D, Z19.D

0x4288f8 ADR	Z19.D, [Z31, Z20.D,LSL #3]    [16]

0x4288fc MUL	Z21.D, Z17.D, Z10.D

0x428900 ADR	Z20.D, [Z19, Z29.D,SXTW #3]    [59]

0x428904 ADD	Z19.D, Z19.D, Z0.D

0x428908 FMUL	Z18.D, Z18.D, Z28.D

0x42890c FMUL	Z18.D, Z4.D, Z18.D

0x428910 LD1D	{Z20.D}, P0/Z, [V20.D]    [40]

0x428914 LD1D	{Z19.D}, P0/Z, [V19.D]    [58]

0x428918 FADD	Z19.D, Z20.D, Z19.D

0x42891c ADR	Z20.D, [Z8, Z21.D,LSL #3]    [17]

0x428920 ADR	Z21.D, [Z20, Z29.D,SXTW #3]    [39]

0x428924 ADD	Z0.D, Z20.D, Z0.D

0x428928 MUL	Z20.D, Z7.D, Z10.D

0x42892c LD1D	{Z21.D}, P0/Z, [V21.D]    [42]

0x428930 LD1D	{Z0.D}, P0/Z, [V0.D]    [1]

0x428934 ADR	Z20.D, [Z30, Z20.D,LSL #3]    [11]

0x428938 ADR	Z20.D, [Z20, Z29.D,SXTW #3]    [38]

0x42893c FADD	Z19.D, Z19.D, Z21.D

0x428940 FADD	Z0.D, Z19.D, Z0.D

0x428944 LDR	Z19, [X11, #506, MUL VL]    [33]

0x428948 LD1D	{Z20.D}, P0/Z, [V20.D]    [37]

0x42894c FMUL	Z0.D, Z20.D, Z0.D

0x428950 MUL	Z19.D, Z19.D, Z15.D

0x428954 FMUL	Z0.D, Z0.D, Z28.D

0x428958 FMUL	Z0.D, Z4.D, Z0.D

0x42895c LDR	Z4, [X11, #507, MUL VL]    [33]

0x428960 ADR	Z19.D, [Z11, Z19.D,LSL #3]    [12]

0x428964 ADR	Z3.D, [Z19, Z29.D,SXTW #3]    [57]

0x428968 LDR	Z19, [X11, #505, MUL VL]    [33]

0x42896c FADD	Z0.D, Z2.D, Z0.D

0x428970 FSUB	Z0.D, Z0.D, Z18.D

0x428974 LD1D	{Z3.D}, P0/Z, [V3.D]    [26]

0x428978 DUP	Z18.D, X15

0x42897c MUL	Z4.D, Z4.D, Z15.D

0x428980 MUL	Z19.D, Z19.D, Z15.D

0x428984 ADR	Z2.D, [Z9, Z4.D,LSL #3]    [19]

0x428988 LDR	Z4, [X11, #504, MUL VL]    [33]

0x42898c ADR	Z19.D, [Z12, Z19.D,LSL #3]    [18]

0x428990 ADR	Z2.D, [Z2, Z29.D,SXTW #3]    [24]

0x428994 ADR	Z19.D, [Z19, Z29.D,SXTW #3]    [43]

0x428998 LD1D	{Z2.D}, P0/Z, [V2.D]    [23]

0x42899c MUL	Z4.D, Z4.D, Z15.D

0x4289a0 LD1D	{Z20.D}, P0/Z, [V19.D]    [41]

0x4289a4 ADR	Z4.D, [Z13, Z4.D,LSL #3]    [20]

0x4289a8 ADR	Z4.D, [Z4, Z29.D,SXTW #3]    [31]

0x4289ac FDIV	Z3.D, P0/M, Z3.D, Z20.D

0x4289b0 LD1D	{Z4.D}, P0/Z, [V4.D]    [30]

0x4289b4 FDIV	Z4.D, P0/M, Z4.D, Z20.D

0x4289b8 FADD	Z3.D, Z3.D, Z4.D

0x4289bc MUL	Z4.D, Z22.D, Z15.D

0x4289c0 FMUL	Z3.D, Z0.D, Z3.D

0x4289c4 FADD	Z0.D, Z2.D, Z0.D

0x4289c8 FDIVR	Z0.D, P0/M, Z0.D, Z2.D

0x4289cc ADR	Z4.D, [Z18, Z4.D,LSL #3]    [35]

0x4289d0 FDUP	Z18.D, #112

0x4289d4 FDIV	Z18.D, P0/M, Z18.D, Z2.D

0x4289d8 ADR	Z4.D, [Z4, Z29.D,SXTW #3]    [29]

0x4289dc MUL	Z2.D, Z24.D, Z15.D

0x4289e0 LD1D	{Z4.D}, P0/Z, [V4.D]    [28]

0x4289e4 FMUL	Z3.D, Z18.D, Z3.D

0x4289e8 DUP	Z18.D, X12

0x4289ec FSUB	Z3.D, Z4.D, Z3.D

0x4289f0 MUL	Z4.D, Z23.D, Z15.D

0x4289f4 ADR	Z4.D, [Z18, Z4.D,LSL #3]    [56]

0x4289f8 ADR	Z4.D, [Z4, Z29.D,SXTW #3]    [6]

0x4289fc ST1D	{Z3.D}, P0, [V4.D]    [5]

0x428a00 LD1D	{Z3.D}, P0/Z, [V19.D]    [41]

0x428a04 FMUL	Z0.D, Z0.D, Z3.D

0x428a08 DUP	Z3.D, X16

0x428a0c ADR	Z2.D, [Z3, Z2.D,LSL #3]    [25]

0x428a10 ADR	Z2.D, [Z2, Z29.D,SXTW #3]    [22]

0x428a14 ST1D	{Z0.D}, P0, [V2.D]    [21]

0x428a18 LDR	Z0, [X11, #511, MUL VL]    [33]

0x428a1c ADD	Z14.D, Z14.D, Z0.D

0x428a20 CBNZ	X10, 4287ac

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 70 - 83

--------------------------------------------------------------------------------

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79 - 1.54
Bottlenecks	P8, P10,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.2]
Source	PdV.cpp:70-83,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	31.25 - 47.97
CQA cycles if no scalar integer	31.25 - 47.97
CQA cycles if FP arith vectorized	31.25 - 47.97
CQA cycles if fully vectorized	26.16 - 47.97
Front-end cycles	17.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	3.00
P7 cycles	1.00
P8 cycles	31.25
P9 cycles	31.25
P10 cycles	31.25
P11 cycles	31.25
P12 cycles	12.33
P13 cycles	12.33
P14 cycles	12.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	14.86 - 47.97
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	158.00
Nb uops	140.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.37 - 1.54
Nb FLOP add-sub	36.00
Nb FLOP mul	30.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.17 - 18.69
Bytes prefetched	0.00
Bytes loaded	552.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	41.00
Stride indirect	19.00
Vectorization ratio all	69.23
Vectorization ratio load	47.22
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	45.71
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	18.18
Vector-efficiency ratio all	85.34
Vector-efficiency ratio load	73.61
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	69.32

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79 - 1.54
Bottlenecks	P8, P10,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.2]
Source	PdV.cpp:70-83,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	31.25 - 47.97
CQA cycles if no scalar integer	31.25 - 47.97
CQA cycles if FP arith vectorized	31.25 - 47.97
CQA cycles if fully vectorized	26.16 - 47.97
Front-end cycles	17.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	3.00
P7 cycles	1.00
P8 cycles	31.25
P9 cycles	31.25
P10 cycles	31.25
P11 cycles	31.25
P12 cycles	12.33
P13 cycles	12.33
P14 cycles	12.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	14.86 - 47.97
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	158.00
Nb uops	140.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.37 - 1.54
Nb FLOP add-sub	36.00
Nb FLOP mul	30.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.17 - 18.69
Bytes prefetched	0.00
Bytes loaded	552.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	41.00
Stride indirect	19.00
Vectorization ratio all	69.23
Vectorization ratio load	47.22
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	45.71
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	18.18
Vector-efficiency ratio all	85.34
Vector-efficiency ratio load	73.61
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	69.32

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.2]
Source file and lines	PdV.cpp:70-83
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

47% of VPU loads are used in vector version.
45% of VPU addition or subtraction instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 74 FP arithmetical operations:

36: addition or subtraction
30: multiply
8: divide

The binary loop is loading 552 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	158
loop length	632
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	3.00	1.00	31.25	31.25	31.25	31.25	12.33	12.33	12.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	3.00	1.00	31.25	31.25	31.25	31.25	12.33	12.33	12.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-47.97
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.50
Data deps.	2.00
Overall L1	31.25-47.97

Vectorization ratios

INT

all	60%
load	47%
store	100%
mul	100%
add-sub	26%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	69%
load	47%
store	100%
mul	100%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.97 cycles. At this rate:

11% of peak load performance is reached (11.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4287ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z0, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z0.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X11, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X10, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z3, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z4, [X11, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z2, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z2.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z15, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z15.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z10.D, Z5.D, Z15.D																					vect (100.0%)
MUL Z3.D, Z6.D, Z15.D																					vect (100.0%)
ADD Z29.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z2.D, [Z26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z27, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z4.D, [Z3, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z18.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z10.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z0.D, Z5.D, Z10.D																					vect (100.0%)
ADR Z19.D, [Z26, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z20.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
DUP Z0.D, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
ADR Z0.D, [Z0, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z2.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LDR Z2, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z6.D, Z10.D																					vect (100.0%)
FADD Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z20.D, [Z27, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z2.D, Z2.D, Z15.D																					vect (100.0%)
FADD Z19.D, Z21.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z21.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z3.D, Z19.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z19.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z16.D, Z15.D																					vect (100.0%)
ADR Z2.D, [Z25, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z18.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z2.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z20.D, [Z31, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z4.D, Z4.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z21.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z20.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z3.D, Z3.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z3.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1RD {Z4.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL Z2.D, Z2.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z20.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z17.D, Z15.D																					vect (100.0%)
FMUL Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z19.D, [Z8, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z7.D, Z15.D																					vect (100.0%)
FADD Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z16.D, Z10.D																					vect (100.0%)
ADR Z21.D, [Z30, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z18.D, Z21.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z19.D, [Z31, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z21.D, Z17.D, Z10.D																					vect (100.0%)
ADR Z20.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z18.D, Z18.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z18.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z20.D, [Z8, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z0.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z7.D, Z10.D																					vect (100.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z20.D, [Z30, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z20.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z19.D, Z19.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z0.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z19, [X11, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z19.D, Z19.D, Z15.D																					vect (100.0%)
FMUL Z0.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR Z4, [X11, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z11, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z19, [X11, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z0.D, Z0.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
DUP Z18.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MUL Z4.D, Z4.D, Z15.D																					vect (100.0%)
MUL Z19.D, Z19.D, Z15.D																					vect (100.0%)
ADR Z2.D, [Z9, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z4, [X11, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z12, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z19.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z4.D, Z4.D, Z15.D																					vect (100.0%)
LD1D {Z20.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z4.D, [Z13, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z4.D, [Z4, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV Z3.D, P0/M, Z3.D, Z20.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z20.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z4.D, Z22.D, Z15.D																					vect (100.0%)
FMUL Z3.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ADR Z4.D, [Z18, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDUP Z18.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ADR Z4.D, [Z4, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z2.D, Z24.D, Z15.D																					vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z3.D, Z18.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
DUP Z18.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
FSUB Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z4.D, Z23.D, Z15.D																					vect (100.0%)
ADR Z4.D, [Z18, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z4.D, [Z4, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z3.D}, P0, [V4.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
DUP Z3.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ADR Z2.D, [Z3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z14.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X10, 4287ac <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.2]
Source file and lines	PdV.cpp:70-83
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

47% of VPU loads are used in vector version.
45% of VPU addition or subtraction instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 74 FP arithmetical operations:

36: addition or subtraction
30: multiply
8: divide

The binary loop is loading 552 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	158
loop length	632
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	3.00	1.00	31.25	31.25	31.25	31.25	12.33	12.33	12.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	3.00	1.00	31.25	31.25	31.25	31.25	12.33	12.33	12.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-47.97
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.50
Data deps.	2.00
Overall L1	31.25-47.97

Vectorization ratios

INT

all	60%
load	47%
store	100%
mul	100%
add-sub	26%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	69%
load	47%
store	100%
mul	100%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.97 cycles. At this rate:

11% of peak load performance is reached (11.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4287ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z0, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z0.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X11, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X10, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z3, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z4, [X11, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z2, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z2.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z15, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z15.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z10.D, Z5.D, Z15.D																					vect (100.0%)
MUL Z3.D, Z6.D, Z15.D																					vect (100.0%)
ADD Z29.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z2.D, [Z26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z27, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z4.D, [Z3, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z18.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z10.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z0.D, Z5.D, Z10.D																					vect (100.0%)
ADR Z19.D, [Z26, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z20.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
DUP Z0.D, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
ADR Z0.D, [Z0, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z2.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LDR Z2, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z6.D, Z10.D																					vect (100.0%)
FADD Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z20.D, [Z27, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z2.D, Z2.D, Z15.D																					vect (100.0%)
FADD Z19.D, Z21.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z21.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z3.D, Z19.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z19.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z16.D, Z15.D																					vect (100.0%)
ADR Z2.D, [Z25, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z18.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z2.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z20.D, [Z31, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z4.D, Z4.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z21.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z20.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z3.D, Z3.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z3.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1RD {Z4.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL Z2.D, Z2.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z20.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z17.D, Z15.D																					vect (100.0%)
FMUL Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z19.D, [Z8, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z7.D, Z15.D																					vect (100.0%)
FADD Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z16.D, Z10.D																					vect (100.0%)
ADR Z21.D, [Z30, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z18.D, Z21.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z19.D, [Z31, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z21.D, Z17.D, Z10.D																					vect (100.0%)
ADR Z20.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z18.D, Z18.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z18.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z20.D, [Z8, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z0.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z20.D, Z7.D, Z10.D																					vect (100.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z20.D, [Z30, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z20.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z19.D, Z19.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z0.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z19, [X11, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z20.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z19.D, Z19.D, Z15.D																					vect (100.0%)
FMUL Z0.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR Z4, [X11, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z11, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z19, [X11, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z0.D, Z0.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
DUP Z18.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
MUL Z4.D, Z4.D, Z15.D																					vect (100.0%)
MUL Z19.D, Z19.D, Z15.D																					vect (100.0%)
ADR Z2.D, [Z9, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z4, [X11, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z12, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z19.D, [Z19, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z4.D, Z4.D, Z15.D																					vect (100.0%)
LD1D {Z20.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z4.D, [Z13, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z4.D, [Z4, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV Z3.D, P0/M, Z3.D, Z20.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z20.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z4.D, Z22.D, Z15.D																					vect (100.0%)
FMUL Z3.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ADR Z4.D, [Z18, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDUP Z18.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ADR Z4.D, [Z4, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z2.D, Z24.D, Z15.D																					vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z3.D, Z18.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
DUP Z18.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
FSUB Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z4.D, Z23.D, Z15.D																					vect (100.0%)
ADR Z4.D, [Z18, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z4.D, [Z4, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z3.D}, P0, [V4.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
DUP Z3.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ADR Z2.D, [Z3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z14.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X10, 4287ac <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code