OV - exec - Loop 307

	Loop Id: 307	Module: exec	Source: PdV.cpp:49-63 [...]	Coverage: 5.42%

0x4280c0 MOVPRFX	Z26, Z13

0x4280c4 SDIV	Z26.D, P0/M, Z26.D, Z1.D

0x4280c8 SUB	X20, X29, #64

0x4280cc DECD	X30, ALL

0x4280d0 LDR	Z0, [X20, #510, MUL VL]    [27]

0x4280d4 LDR	Z2, [X20, #509, MUL VL]    [27]

0x4280d8 ADD	Z30.D, Z0.D, Z26.D

0x4280dc LDR	Z0, [X20, #508, MUL VL]    [27]

0x4280e0 MSB	Z26.D, P0/M, Z1.D, Z13.D

0x4280e4 MOVPRFX	Z15, Z30

0x4280e8 SXTW	Z15.D, P0/M, Z30.D

0x4280ec ADD	Z30.D, Z30.D, #1

0x4280f0 MUL	Z18.D, Z6.D, Z15.D

0x4280f4 ADD	Z14.D, Z2.D, Z26.D

0x4280f8 MUL	Z0.D, Z0.D, Z15.D

0x4280fc ADR	Z18.D, [Z27, Z18.D,LSL #3]    [32]

0x428100 ADR	Z0.D, [Z23, Z0.D,LSL #3]    [12]

0x428104 ADR	Z18.D, [Z18, Z14.D,SXTW #3]    [38]

0x428108 ADR	Z26.D, [Z0, Z14.D,SXTW #3]    [14]

0x42810c LD1D	{Z18.D}, P0/Z, [V18.D]    [37]

0x428110 LD1D	{Z2.D}, P0/Z, [V26.D]    [26]

0x428114 MUL	Z26.D, Z5.D, Z15.D

0x428118 ADR	Z3.D, [Z24, Z26.D,LSL #3]    [15]

0x42811c ADR	Z26.D, [Z3, Z14.D,SXTW #3]    [47]

0x428120 LD1D	{Z4.D}, P0/Z, [V26.D]    [25]

0x428124 MOVPRFX	Z26, Z30

0x428128 SXTW	Z26.D, P0/M, Z30.D

0x42812c MUL	Z30.D, Z5.D, Z26.D

0x428130 ADR	Z30.D, [Z24, Z30.D,LSL #3]    [15]

0x428134 ADR	Z16.D, [Z30, Z14.D,SXTW #3]    [6]

0x428138 LD1D	{Z16.D}, P0/Z, [V16.D]    [24]

0x42813c FADD	Z17.D, Z4.D, Z16.D

0x428140 FADD	Z4.D, Z4.D, Z17.D

0x428144 DUP	Z17.D, #8

0x428148 ADR	Z17.D, [Z17, Z14.D,SXTW #3]    [31]

0x42814c FADD	Z4.D, Z16.D, Z4.D

0x428150 ADD	Z3.D, Z3.D, Z17.D

0x428154 ADD	Z30.D, Z30.D, Z17.D

0x428158 FMUL	Z2.D, Z2.D, Z4.D

0x42815c MUL	Z4.D, Z7.D, Z15.D

0x428160 ADD	Z0.D, Z0.D, Z17.D

0x428164 LD1D	{Z3.D}, P0/Z, [V3.D]    [46]

0x428168 LD1D	{Z16.D}, P0/Z, [V30.D]    [5]

0x42816c LD1D	{Z0.D}, P0/Z, [V0.D]    [13]

0x428170 FMUL	Z2.D, Z2.D, Z25.D

0x428174 ADR	Z4.D, [Z28, Z4.D,LSL #3]    [39]

0x428178 FADD	Z30.D, Z3.D, Z16.D

0x42817c FADD	Z3.D, Z3.D, Z30.D

0x428180 ADR	Z30.D, [Z4, Z14.D,SXTW #3]    [2]

0x428184 ADD	Z4.D, Z4.D, Z17.D

0x428188 LD1D	{Z30.D}, P0/Z, [V30.D]    [4]

0x42818c LD1D	{Z4.D}, P0/Z, [V4.D]    [1]

0x428190 FADD	Z3.D, Z16.D, Z3.D

0x428194 FMUL	Z0.D, Z0.D, Z3.D

0x428198 FMUL	Z0.D, Z0.D, Z25.D

0x42819c FADD	Z16.D, Z30.D, Z4.D

0x4281a0 FADD	Z16.D, Z30.D, Z16.D

0x4281a4 FADD	Z4.D, Z4.D, Z16.D

0x4281a8 MUL	Z16.D, Z7.D, Z26.D

0x4281ac FMUL	Z4.D, Z18.D, Z4.D

0x4281b0 ADR	Z16.D, [Z28, Z16.D,LSL #3]    [39]

0x4281b4 FMUL	Z4.D, Z4.D, Z25.D

0x4281b8 ADD	Z17.D, Z16.D, Z17.D

0x4281bc ADR	Z16.D, [Z16, Z14.D,SXTW #3]    [23]

0x4281c0 LD1D	{Z16.D}, P0/Z, [V16.D]    [22]

0x4281c4 LD1D	{Z3.D}, P0/Z, [V17.D]    [30]

0x4281c8 FADD	Z17.D, Z16.D, Z3.D

0x4281cc FADD	Z16.D, Z16.D, Z17.D

0x4281d0 MUL	Z17.D, Z6.D, Z26.D

0x4281d4 FADD	Z3.D, Z3.D, Z16.D

0x4281d8 LD1RD	{Z16.D}, P0/Z, [X8]    [41]

0x4281dc ADR	Z17.D, [Z27, Z17.D,LSL #3]    [32]

0x4281e0 ADR	Z17.D, [Z17, Z14.D,SXTW #3]    [29]

0x4281e4 FMUL	Z2.D, Z16.D, Z2.D

0x4281e8 FMUL	Z0.D, Z16.D, Z0.D

0x4281ec FMUL	Z4.D, Z16.D, Z4.D

0x4281f0 LD1D	{Z17.D}, P0/Z, [V17.D]    [28]

0x4281f4 FMUL	Z2.D, P0/M, Z2.D, #0

0x4281f8 FMUL	Z0.D, P0/M, Z0.D, #0

0x4281fc FMUL	Z4.D, P0/M, Z4.D, #0

0x428200 FSUB	Z0.D, Z0.D, Z2.D

0x428204 LDR	Z2, [X20, #507, MUL VL]    [27]

0x428208 FMUL	Z3.D, Z17.D, Z3.D

0x42820c MUL	Z17.D, Z19.D, Z15.D

0x428210 MUL	Z2.D, Z2.D, Z15.D

0x428214 FMUL	Z3.D, Z3.D, Z25.D

0x428218 ADR	Z17.D, [Z9, Z17.D,LSL #3]    [11]

0x42821c FMUL	Z3.D, Z16.D, Z3.D

0x428220 LDR	Z16, [X20, #505, MUL VL]    [27]

0x428224 ADR	Z17.D, [Z17, Z14.D,SXTW #3]    [44]

0x428228 ADR	Z2.D, [Z29, Z2.D,LSL #3]    [40]

0x42822c FMUL	Z3.D, P0/M, Z3.D, #0

0x428230 LD1D	{Z17.D}, P0/Z, [V17.D]    [43]

0x428234 ADR	Z2.D, [Z2, Z14.D,SXTW #3]    [45]

0x428238 FADD	Z0.D, Z0.D, Z3.D

0x42823c LDR	Z3, [X20, #506, MUL VL]    [27]

0x428240 MUL	Z16.D, Z16.D, Z15.D

0x428244 LD1D	{Z2.D}, P0/Z, [V2.D]    [18]

0x428248 FSUB	Z0.D, Z0.D, Z4.D

0x42824c ADR	Z16.D, [Z8, Z16.D,LSL #3]    [9]

0x428250 MUL	Z3.D, Z3.D, Z15.D

0x428254 ADR	Z4.D, [Z16, Z14.D,SXTW #3]    [42]

0x428258 LD1D	{Z16.D}, P0/Z, [V4.D]    [21]

0x42825c ADR	Z3.D, [Z31, Z3.D,LSL #3]    [8]

0x428260 ADR	Z3.D, [Z3, Z14.D,SXTW #3]    [20]

0x428264 LD1D	{Z3.D}, P0/Z, [V3.D]    [19]

0x428268 FDIV	Z3.D, P0/M, Z3.D, Z16.D

0x42826c FDIVR	Z16.D, P0/M, Z16.D, Z17.D

0x428270 FADD	Z3.D, Z3.D, Z16.D

0x428274 FDUP	Z16.D, #112

0x428278 FDIV	Z16.D, P0/M, Z16.D, Z2.D

0x42827c FMUL	Z3.D, Z0.D, Z3.D

0x428280 FADD	Z0.D, Z2.D, Z0.D

0x428284 FDIVR	Z0.D, P0/M, Z0.D, Z2.D

0x428288 FMUL	Z3.D, Z16.D, Z3.D

0x42828c MUL	Z16.D, Z20.D, Z15.D

0x428290 ADR	Z16.D, [Z10, Z16.D,LSL #3]    [3]

0x428294 ADR	Z16.D, [Z16, Z14.D,SXTW #3]    [36]

0x428298 LD1D	{Z16.D}, P0/Z, [V16.D]    [35]

0x42829c FSUB	Z3.D, Z16.D, Z3.D

0x4282a0 MUL	Z16.D, Z21.D, Z15.D

0x4282a4 ADR	Z16.D, [Z11, Z16.D,LSL #3]    [7]

0x4282a8 ADR	Z16.D, [Z16, Z14.D,SXTW #3]    [34]

0x4282ac ST1D	{Z3.D}, P0, [V16.D]    [33]

0x4282b0 LD1D	{Z2.D}, P0/Z, [V4.D]    [21]

0x4282b4 FMUL	Z0.D, Z0.D, Z2.D

0x4282b8 MUL	Z2.D, Z22.D, Z15.D

0x4282bc ADR	Z2.D, [Z12, Z2.D,LSL #3]    [10]

0x4282c0 ADR	Z2.D, [Z2, Z14.D,SXTW #3]    [17]

0x4282c4 ST1D	{Z0.D}, P0, [V2.D]    [16]

0x4282c8 LDR	Z0, [X20, #511, MUL VL]    [27]

0x4282cc ADD	Z13.D, Z13.D, Z0.D

0x4282d0 CBNZ	X30, 4280c0

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 49 - 63

--------------------------------------------------------------------------------

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.82 - 1.78
Bottlenecks	P8, P10,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	PdV.cpp:49-63,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	27.00 - 47.97
CQA cycles if no scalar integer	27.00 - 47.97
CQA cycles if FP arith vectorized	27.00 - 47.97
CQA cycles if fully vectorized	22.91 - 47.97
Front-end cycles	14.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	27.00
P9 cycles	27.00
P10 cycles	27.00
P11 cycles	27.00
P12 cycles	9.33
P13 cycles	9.33
P14 cycles	9.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	14.86 - 47.97
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	133.00
Nb uops	119.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.04 - 1.71
Nb FLOP add-sub	36.00
Nb FLOP mul	38.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.17 - 16.30
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	31.00
Stride indirect	15.00
Vectorization ratio all	72.52
Vectorization ratio load	45.45
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	47.37
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	86.74
Vector-efficiency ratio load	72.73
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	73.68
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.21

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.82 - 1.78
Bottlenecks	P8, P10,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	PdV.cpp:49-63,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	27.00 - 47.97
CQA cycles if no scalar integer	27.00 - 47.97
CQA cycles if FP arith vectorized	27.00 - 47.97
CQA cycles if fully vectorized	22.91 - 47.97
Front-end cycles	14.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	27.00
P9 cycles	27.00
P10 cycles	27.00
P11 cycles	27.00
P12 cycles	9.33
P13 cycles	9.33
P14 cycles	9.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	14.86 - 47.97
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	133.00
Nb uops	119.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.04 - 1.71
Nb FLOP add-sub	36.00
Nb FLOP mul	38.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.17 - 16.30
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	31.00
Stride indirect	15.00
Vectorization ratio all	72.52
Vectorization ratio load	45.45
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	47.37
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	86.74
Vector-efficiency ratio load	72.73
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	73.68
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	73.21

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	PdV.cpp:49-63
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 86% of vector register length is used (average across all VPU instructions).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
47% of VPU addition or subtraction instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 82 FP arithmetical operations:

36: addition or subtraction
38: multiply
8: divide

The binary loop is loading 408 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	133
loop length	532
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	0.50	0.50	27.00	27.00	27.00	27.00	9.33	9.33	9.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	0.50	0.50	27.00	27.00	27.00	27.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-47.97
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.88
Data deps.	2.00
Overall L1	27.00-47.97

Vectorization ratios

INT

all	60%
load	45%
store	100%
mul	100%
add-sub	23%
fma	100%
other	42%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	72%
load	45%
store	100%
mul	100%
add-sub	47%
fma	100%
div/sqrt	100%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.97 cycles. At this rate:

8% of peak load performance is reached (8.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4280c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z26, Z13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z26.D, P0/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X20, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X30, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X20, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z2, [X20, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z30.D, Z0.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X20, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MSB Z26.D, P0/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z15, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z15.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z18.D, Z6.D, Z15.D																					vect (100.0%)
ADD Z14.D, Z2.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z0.D, Z0.D, Z15.D																					vect (100.0%)
ADR Z18.D, [Z27, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z23, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z18.D, [Z18, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z0, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z26.D, Z5.D, Z15.D																					vect (100.0%)
ADR Z3.D, [Z24, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z3, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z4.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z26, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z26.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z30.D, Z5.D, Z26.D																					vect (100.0%)
ADR Z30.D, [Z24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z30, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z17.D, Z4.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z17.D, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
ADR Z17.D, [Z17, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z4.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z3.D, Z3.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z30.D, Z30.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z4.D, Z7.D, Z15.D																					vect (100.0%)
ADD Z0.D, Z0.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z2.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z4.D, [Z28, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z30.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z3.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z30.D, [Z4, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z16.D, Z30.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z16.D, Z30.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z4.D, Z4.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z16.D, Z7.D, Z26.D																					vect (100.0%)
FMUL Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z16.D, [Z28, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z4.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADD Z17.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z16.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z17.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z17.D, Z6.D, Z26.D																					vect (100.0%)
FADD Z3.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1RD {Z16.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADR Z17.D, [Z27, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z17.D, [Z17, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z2.D, Z16.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z16.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z4.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z2.D, P0/M, Z2.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, P0/M, Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z4.D, P0/M, Z4.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z2, [X20, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z3.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z17.D, Z19.D, Z15.D																					vect (100.0%)
MUL Z2.D, Z2.D, Z15.D																					vect (100.0%)
FMUL Z3.D, Z3.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z17.D, [Z9, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR Z16, [X20, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z17.D, [Z17, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z29, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z3.D, P0/M, Z3.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z2.D, [Z2, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z3, [X20, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z16.D, Z16.D, Z15.D																					vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z16.D, [Z8, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z3.D, Z3.D, Z15.D																					vect (100.0%)
ADR Z4.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z3.D, [Z31, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z3, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIVR Z16.D, P0/M, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z3.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z16.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDIV Z16.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z3.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z16.D, Z20.D, Z15.D																					vect (100.0%)
ADR Z16.D, [Z10, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z16.D, Z21.D, Z15.D																					vect (100.0%)
ADR Z16.D, [Z11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z3.D}, P0, [V16.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z2.D, Z22.D, Z15.D																					vect (100.0%)
ADR Z2.D, [Z12, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z13.D, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X30, 4280c0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	PdV.cpp:49-63
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 86% of vector register length is used (average across all VPU instructions).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
47% of VPU addition or subtraction instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 82 FP arithmetical operations:

36: addition or subtraction
38: multiply
8: divide

The binary loop is loading 408 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	133
loop length	532
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	0.50	0.50	27.00	27.00	27.00	27.00	9.33	9.33	9.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	0.50	0.50	27.00	27.00	27.00	27.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-47.97
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.88
Data deps.	2.00
Overall L1	27.00-47.97

Vectorization ratios

INT

all	60%
load	45%
store	100%
mul	100%
add-sub	23%
fma	100%
other	42%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	72%
load	45%
store	100%
mul	100%
add-sub	47%
fma	100%
div/sqrt	100%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.97 cycles. At this rate:

8% of peak load performance is reached (8.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4280c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z26, Z13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z26.D, P0/M, Z26.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X20, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X30, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X20, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z2, [X20, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z30.D, Z0.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X20, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MSB Z26.D, P0/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z15, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z15.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z18.D, Z6.D, Z15.D																					vect (100.0%)
ADD Z14.D, Z2.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z0.D, Z0.D, Z15.D																					vect (100.0%)
ADR Z18.D, [Z27, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z23, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z18.D, [Z18, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z0, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MUL Z26.D, Z5.D, Z15.D																					vect (100.0%)
ADR Z3.D, [Z24, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z3, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z4.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z26, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z26.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z30.D, Z5.D, Z26.D																					vect (100.0%)
ADR Z30.D, [Z24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z30, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z17.D, Z4.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z17.D, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
ADR Z17.D, [Z17, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z4.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z3.D, Z3.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z30.D, Z30.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z4.D, Z7.D, Z15.D																					vect (100.0%)
ADD Z0.D, Z0.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z2.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z4.D, [Z28, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z30.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z3.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z30.D, [Z4, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z16.D, Z30.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z16.D, Z30.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z4.D, Z4.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z16.D, Z7.D, Z26.D																					vect (100.0%)
FMUL Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z16.D, [Z28, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z4.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADD Z17.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z16.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z17.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z17.D, Z6.D, Z26.D																					vect (100.0%)
FADD Z3.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1RD {Z16.D}, P0/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADR Z17.D, [Z27, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z17.D, [Z17, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z2.D, Z16.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, Z16.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z4.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z2.D, P0/M, Z2.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z0.D, P0/M, Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z4.D, P0/M, Z4.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z2, [X20, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z3.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z17.D, Z19.D, Z15.D																					vect (100.0%)
MUL Z2.D, Z2.D, Z15.D																					vect (100.0%)
FMUL Z3.D, Z3.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z17.D, [Z9, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR Z16, [X20, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z17.D, [Z17, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z29, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z3.D, P0/M, Z3.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z2.D, [Z2, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z3, [X20, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z16.D, Z16.D, Z15.D																					vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z16.D, [Z8, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z3.D, Z3.D, Z15.D																					vect (100.0%)
ADR Z4.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z3.D, [Z31, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z3, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIVR Z16.D, P0/M, Z16.D, Z17.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z3.D, Z3.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDUP Z16.D, #112	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FDIV Z16.D, P0/M, Z16.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z3.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z16.D, Z20.D, Z15.D																					vect (100.0%)
ADR Z16.D, [Z10, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z3.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z16.D, Z21.D, Z15.D																					vect (100.0%)
ADR Z16.D, [Z11, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z16.D, [Z16, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z3.D}, P0, [V16.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z2.D, Z22.D, Z15.D																					vect (100.0%)
ADR Z2.D, [Z12, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z13.D, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X30, 4280c0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code