OV - exec - Loop 262

	Loop Id: 262	Module: exec	Source: initialise_chunk.cpp:78-82 [...]	Coverage: 0.02%

0x424740 MOVPRFX	Z17, Z16

0x424744 SDIV	Z17.D, P0/M, Z17.D, Z1.D

0x424748 LDR	D19, [X20]    [7]

0x42474c LDR	D20, [X19]    [13]

0x424750 DECD	X2, ALL

0x424754 FMUL	D19, D19, D20

0x424758 DUP	Z19.D, Z19.D[0]

0x42475c MOVPRFX	Z20, Z17

0x424760 SXTW	Z20.D, P0/M, Z17.D

0x424764 MOVPRFX	Z18, Z16

0x424768 MLS	Z18.D, P0/M, Z17.D, Z1.D

0x42476c ADD	Z16.D, Z16.D, Z0.D

0x424770 MUL	Z21.D, Z2.D, Z20.D

0x424774 ADR	Z21.D, [Z5, Z21.D,LSL #3]    [1]

0x424778 ADR	Z21.D, [Z21, Z18.D,SXTW #3]    [5]

0x42477c ST1D	{Z19.D}, P0, [V21.D]    [4]

0x424780 MUL	Z19.D, Z3.D, Z20.D

0x424784 LD1D	{Z17.D}, P0/Z, [X10, Z17.D,SXTW #3]    [6]

0x424788 ADR	Z19.D, [Z6, Z19.D,LSL #3]    [2]

0x42478c ADR	Z19.D, [Z19, Z18.D,SXTW #3]    [11]

0x424790 ST1D	{Z17.D}, P0, [V19.D]    [10]

0x424794 MUL	Z19.D, Z4.D, Z20.D

0x424798 LD1D	{Z17.D}, P0/Z, [X13, Z18.D,SXTW #3]    [12]

0x42479c ADR	Z19.D, [Z7, Z19.D,LSL #3]    [3]

0x4247a0 ADR	Z18.D, [Z19, Z18.D,SXTW #3]    [9]

0x4247a4 ST1D	{Z17.D}, P0, [V18.D]    [8]

0x4247a8 CBNZ	X2, 424740

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 78 - 82

--------------------------------------------------------------------------------

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.06 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.24 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50 - 4.44
Bottlenecks	P8, P10,
Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source	initialise_chunk.cpp:78-82,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	4.50 - 20.00
CQA cycles if no scalar integer	4.25 - 20.00
CQA cycles if FP arith vectorized	3.00 - 20.00
CQA cycles if fully vectorized	3.63 - 20.00
Front-end cycles	3.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	2.50
P13 cycles	2.17
P14 cycles	2.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	24.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.22 - 0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80 - 21.33
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	4.00
Vectorization ratio all	50.00
Vectorization ratio load	20.00
Vectorization ratio store	100.00
Vectorization ratio mul	75.00
Vectorization ratio add_sub	22.22
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	40.00
Vector-efficiency ratio all	80.77
Vector-efficiency ratio load	60.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	87.50
Vector-efficiency ratio add_sub	61.11
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.06 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.24 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50 - 4.44
Bottlenecks	P8, P10,
Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source	initialise_chunk.cpp:78-82,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	4.50 - 20.00
CQA cycles if no scalar integer	4.25 - 20.00
CQA cycles if FP arith vectorized	3.00 - 20.00
CQA cycles if fully vectorized	3.63 - 20.00
Front-end cycles	3.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	2.50
P13 cycles	2.17
P14 cycles	2.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	24.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.22 - 0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80 - 21.33
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	48.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	4.00
Vectorization ratio all	50.00
Vectorization ratio load	20.00
Vectorization ratio store	100.00
Vectorization ratio mul	75.00
Vectorization ratio add_sub	22.22
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	40.00
Vector-efficiency ratio all	80.77
Vector-efficiency ratio load	60.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	87.50
Vector-efficiency ratio add_sub	61.11
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source file and lines	initialise_chunk.cpp:78-82
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:78-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 80% of vector register length is used (average across all VPU instructions).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
22% of VPU addition or subtraction instructions are used in vector version.
75% of VPU multiply instructions are used in vector version.
40% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 48 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	4.50	4.50	4.50	4.50	2.50	2.17	2.33	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	4.50	4.50	4.50	4.50	2.50	2.17	2.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	4.50-20.00

Vectorization ratios

INT

all	52%
load	20%
store	100%
mul	100%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	20%
store	100%
mul	75%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z17, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z17.D, P0/M, Z17.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
LDR D19, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D20, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DECD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
FMUL D19, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
DUP Z19.D, Z19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z20, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z20.D, P0/M, Z17.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z18.D, P0/M, Z17.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z16.D, Z16.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z2.D, Z20.D																					vect (100.0%)
ADR Z21.D, [Z5, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V21.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z19.D, Z3.D, Z20.D																					vect (100.0%)
LD1D {Z17.D}, P0/Z, [X10, Z17.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z6, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z19.D, [Z19, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z17.D}, P0, [V19.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z19.D, Z4.D, Z20.D																					vect (100.0%)
LD1D {Z17.D}, P0/Z, [X13, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z7, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z18.D, [Z19, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z17.D}, P0, [V18.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X2, 424740 <_Z16initialise_chunkiR16global_variables.omp_outlined.8+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	initialise_chunk(int, global_variables&) [clone .omp_outlined.8]
Source file and lines	initialise_chunk.cpp:78-82
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:78-82
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 80% of vector register length is used (average across all VPU instructions).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
22% of VPU addition or subtraction instructions are used in vector version.
75% of VPU multiply instructions are used in vector version.
40% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 48 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	4.50	4.50	4.50	4.50	2.50	2.17	2.33	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	4.50	4.50	4.50	4.50	2.50	2.17	2.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	4.50-20.00

Vectorization ratios

INT

all	52%
load	20%
store	100%
mul	100%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	20%
store	100%
mul	75%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z17, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z17.D, P0/M, Z17.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
LDR D19, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D20, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DECD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
FMUL D19, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
DUP Z19.D, Z19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z20, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z20.D, P0/M, Z17.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z18.D, P0/M, Z17.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z16.D, Z16.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z2.D, Z20.D																					vect (100.0%)
ADR Z21.D, [Z5, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V21.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z19.D, Z3.D, Z20.D																					vect (100.0%)
LD1D {Z17.D}, P0/Z, [X10, Z17.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z6, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z19.D, [Z19, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z17.D}, P0, [V19.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z19.D, Z4.D, Z20.D																					vect (100.0%)
LD1D {Z17.D}, P0/Z, [X13, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z19.D, [Z7, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z18.D, [Z19, Z18.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z17.D}, P0, [V18.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X2, 424740 <_Z16initialise_chunkiR16global_variables.omp_outlined.8+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code