OV - exec - Loop 254

	Loop Id: 254	Module: exec	Source: ideal_gas.cpp:38-45 [...]	Coverage: 4.43%

0x423d4c MOVPRFX	Z23, Z22

0x423d50 SDIV	Z23.D, P0/M, Z23.D, Z1.D

0x423d54 DECD	X2, ALL

0x423d58 ADD	Z24.D, Z2.D, Z23.D

0x423d5c MSB	Z23.D, P0/M, Z1.D, Z22.D

0x423d60 ADD	Z22.D, Z22.D, Z0.D

0x423d64 SXTW	Z24.D, P0/M, Z24.D

0x423d68 MUL	Z25.D, Z4.D, Z24.D

0x423d6c MUL	Z27.D, Z5.D, Z24.D

0x423d70 ADD	Z23.D, Z3.D, Z23.D

0x423d74 ADR	Z25.D, [Z16, Z25.D,LSL #3]    [7]

0x423d78 ADR	Z27.D, [Z19, Z27.D,LSL #3]    [12]

0x423d7c ADR	Z25.D, [Z25, Z23.D,SXTW #3]    [6]

0x423d80 ADR	Z27.D, [Z27, Z23.D,SXTW #3]    [11]

0x423d84 LD1D	{Z26.D}, P0/Z, [V25.D]    [5]

0x423d88 LD1D	{Z27.D}, P0/Z, [V27.D]    [10]

0x423d8c MOVPRFX	Z28, Z17

0x423d90 FDIV	Z28.D, P0/M, Z28.D, Z26.D

0x423d94 FMUL	Z26.D, Z26.D, Z18.D

0x423d98 FMUL	Z26.D, Z26.D, Z27.D

0x423d9c MUL	Z27.D, Z6.D, Z24.D

0x423da0 ADR	Z27.D, [Z20, Z27.D,LSL #3]    [1]

0x423da4 MUL	Z24.D, Z7.D, Z24.D

0x423da8 ADR	Z24.D, [Z21, Z24.D,LSL #3]    [2]

0x423dac ADR	Z27.D, [Z27, Z23.D,SXTW #3]    [9]

0x423db0 ADR	Z23.D, [Z24, Z23.D,SXTW #3]    [4]

0x423db4 ST1D	{Z26.D}, P0, [V27.D]    [8]

0x423db8 LD1D	{Z25.D}, P0/Z, [V25.D]    [5]

0x423dbc FMUL	Z28.D, Z28.D, Z28.D

0x423dc0 FMUL	Z27.D, Z25.D, Z18.D

0x423dc4 FMUL	Z25.D, Z26.D, Z25.D

0x423dc8 FMLA	Z25.D, P0/M, Z26.D, Z27.D

0x423dcc FMUL	Z25.D, Z28.D, Z25.D

0x423dd0 FSQRT	Z25.D, P0/M, Z25.D

0x423dd4 ST1D	{Z25.D}, P0, [V23.D]    [3]

0x423dd8 CBNZ	X2, 423d4c

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 38 - 45

--------------------------------------------------------------------------------

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52 - 5.48
Bottlenecks	P8, P10,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	ideal_gas.cpp:38-45,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	11.36 - 41.08
CQA cycles if no scalar integer	11.36 - 41.08
CQA cycles if FP arith vectorized	11.36 - 41.08
CQA cycles if fully vectorized	11.36 - 41.08
Front-end cycles	4.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	1.67
P13 cycles	1.67
P14 cycles	1.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	11.36 - 41.08
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	32.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.76 - 0.49
Nb FLOP add-sub	0.00
Nb FLOP mul	12.00
Nb FLOP fma	2.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.95 - 7.04
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	4.00
Vectorization ratio all	68.57
Vectorization ratio load	27.27
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	25.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	87.14
Vector-efficiency ratio load	63.64
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52 - 5.48
Bottlenecks	P8, P10,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	ideal_gas.cpp:38-45,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	11.36 - 41.08
CQA cycles if no scalar integer	11.36 - 41.08
CQA cycles if FP arith vectorized	11.36 - 41.08
CQA cycles if fully vectorized	11.36 - 41.08
Front-end cycles	4.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	1.67
P13 cycles	1.67
P14 cycles	1.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	11.36 - 41.08
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	32.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.76 - 0.49
Nb FLOP add-sub	0.00
Nb FLOP mul	12.00
Nb FLOP fma	2.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.95 - 7.04
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	4.00
Vectorization ratio all	68.57
Vectorization ratio load	27.27
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	25.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	87.14
Vector-efficiency ratio load	63.64
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

27% of VPU loads are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

2: addition or subtraction (all inside FMA instructions)
14: multiply (2 inside FMA instructions)
2: divide
2: square root

The binary loop is loading 48 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	11.36-41.08
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.00
Data deps.	2.00
Overall L1	11.36-41.08

Vectorization ratios

INT

all	57%
load	27%
store	100%
mul	100%
add-sub	25%
fma	100%
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	27%
store	100%
mul	100%
add-sub	25%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 41.08 cycles. At this rate:

1% of peak load performance is reached (1.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423d4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z23.D, P0/M, Z23.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z24.D, Z2.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z23.D, P0/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z22.D, Z22.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z25.D, Z4.D, Z24.D																					vect (100.0%)
MUL Z27.D, Z5.D, Z24.D																					vect (100.0%)
ADD Z23.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z25.D, [Z16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z19, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z26.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z28, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FDIV Z28.D, P0/M, Z28.D, Z26.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z26.D, Z26.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z27.D, Z6.D, Z24.D																					vect (100.0%)
ADR Z27.D, [Z20, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z24.D, Z7.D, Z24.D																					vect (100.0%)
ADR Z24.D, [Z21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z23.D, [Z24, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z26.D}, P0, [V27.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z28.D, Z28.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z27.D, Z25.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z25.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z25.D, P0/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z25.D, Z28.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSQRT Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
ST1D {Z25.D}, P0, [V23.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X2, 423d4c <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.omp_outlined+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

27% of VPU loads are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

2: addition or subtraction (all inside FMA instructions)
14: multiply (2 inside FMA instructions)
2: divide
2: square root

The binary loop is loading 48 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	11.36-41.08
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.00
Data deps.	2.00
Overall L1	11.36-41.08

Vectorization ratios

INT

all	57%
load	27%
store	100%
mul	100%
add-sub	25%
fma	100%
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	27%
store	100%
mul	100%
add-sub	25%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 41.08 cycles. At this rate:

1% of peak load performance is reached (1.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423d4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z23, Z22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z23.D, P0/M, Z23.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z24.D, Z2.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z23.D, P0/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z22.D, Z22.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z25.D, Z4.D, Z24.D																					vect (100.0%)
MUL Z27.D, Z5.D, Z24.D																					vect (100.0%)
ADD Z23.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z25.D, [Z16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z19, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z26.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z28, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FDIV Z28.D, P0/M, Z28.D, Z26.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMUL Z26.D, Z26.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z27.D, Z6.D, Z24.D																					vect (100.0%)
ADR Z27.D, [Z20, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z24.D, Z7.D, Z24.D																					vect (100.0%)
ADR Z24.D, [Z21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z23.D, [Z24, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z26.D}, P0, [V27.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z28.D, Z28.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z27.D, Z25.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMUL Z25.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z25.D, P0/M, Z26.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z25.D, Z28.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSQRT Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
ST1D {Z25.D}, P0, [V23.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X2, 423d4c <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.omp_outlined+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code