OV - exec - Loop 248

	Loop Id: 248	Module: exec	Source: generate_chunk.cpp:85-98 [...]	Coverage: 0.04%

0x423900 MOVPRFX	Z23, Z0

0x423904 SDIV	Z23.D, P0/M, Z23.D, Z2.D

0x423908 ADD	X12, X9, X8,LSL #3

0x42390c LDR	D26, [X10]    [16]

0x423910 DECD	X7, ALL

0x423914 LD1RD	{Z25.D}, P0/Z, [X12]    [14]

0x423918 DUP	Z26.D, Z26.D[0]

0x42391c MUL	Z24.D, Z23.D, Z2.D

0x423920 LSL	Z28.D, Z23.D, #32

0x423924 SUB	Z24.D, Z0.D, Z24.D

0x423928 ADD	Z0.D, Z0.D, Z1.D

0x42392c LSL	Z27.D, Z24.D, #32

0x423930 ADD	Z27.D, Z27.D, Z7.D

0x423934 ASR	Z27.D, Z27.D, #-31

0x423938 LD1D	{Z27.D}, P0/Z, [X4, Z27.D]    [31]

0x42393c FCMGE	P1.D, P0/Z, Z27.D, Z25.D

0x423940 LD1D	{Z25.D}, P1/Z, [X4, Z24.D,SXTW #3]    [31]

0x423944 LD1D	{Z27.D}, P1/Z, [X20, Z17.D,LSL #3]    [17]

0x423948 FCMGT	P1.D, P1/Z, Z27.D, Z25.D

0x42394c ADD	Z25.D, Z28.D, Z7.D

0x423950 MOVPRFX	Z27, Z23

0x423954 SXTW	Z27.D, P0/M, Z23.D

0x423958 ASR	Z25.D, Z25.D, #-31

0x42395c MUL	Z28.D, Z6.D, Z27.D

0x423960 LD1D	{Z25.D}, P1/Z, [X5, Z25.D]    [7]

0x423964 ADR	Z28.D, [Z22, Z28.D,LSL #3]    [24]

0x423968 FCMGE	P1.D, P1/Z, Z25.D, Z26.D

0x42396c LD1D	{Z25.D}, P1/Z, [X5, Z23.D,SXTW #3]    [7]

0x423970 MUL	Z23.D, Z2.D, Z23.D

0x423974 LD1D	{Z26.D}, P1/Z, [X21, Z17.D,LSL #3]    [19]

0x423978 SUB	Z23.D, Z21.D, Z23.D

0x42397c ADD	Z21.D, Z21.D, Z1.D

0x423980 FCMGT	P1.D, P1/Z, Z26.D, Z25.D

0x423984 MUL	Z26.D, Z3.D, Z27.D

0x423988 LD1D	{Z25.D}, P1/Z, [X11, Z17.D,LSL #3]    [18]

0x42398c ADR	Z26.D, [Z18, Z26.D,LSL #3]    [20]

0x423990 ADR	Z26.D, [Z26, Z24.D,SXTW #3]    [13]

0x423994 ST1D	{Z25.D}, P1, [V26.D]    [12]

0x423998 MUL	Z26.D, Z4.D, Z27.D

0x42399c LD1D	{Z25.D}, P1/Z, [X14, Z17.D,LSL #3]    [27]

0x4239a0 ADR	Z26.D, [Z19, Z26.D,LSL #3]    [23]

0x4239a4 ADR	Z26.D, [Z26, Z24.D,SXTW #3]    [11]

0x4239a8 SXTW	Z24.D, P0/M, Z24.D

0x4239ac ST1D	{Z25.D}, P1, [V26.D]    [10]

0x4239b0 MUL	Z25.D, Z5.D, Z27.D

0x4239b4 ADD	Z27.D, Z27.D, #1

0x4239b8 LD1D	{Z26.D}, P1/Z, [X17, Z17.D,LSL #3]    [30]

0x4239bc ADR	Z25.D, [Z20, Z25.D,LSL #3]    [8]

0x4239c0 ADR	Z29.D, [Z25, Z23.D,SXTW #3]    [6]

0x4239c4 ST1D	{Z26.D}, P1, [V29.D]    [26]

0x4239c8 ADR	Z29.D, [Z28, Z23.D,SXTW #3]    [22]

0x4239cc LD1D	{Z26.D}, P1/Z, [X1, Z17.D,LSL #3]    [29]

0x4239d0 ST1D	{Z26.D}, P1, [V29.D]    [25]

0x4239d4 MOVPRFX	Z26, Z23

0x4239d8 SXTW	Z26.D, P0/M, Z23.D

0x4239dc CMPGE	P2.D, P1/Z, Z24.D, Z26.D

0x4239e0 ADR	Z26.D, [Z16, Z23.D,SXTW #3]    [15]

0x4239e4 ADD	Z25.D, Z25.D, Z26.D

0x4239e8 LD1D	{Z24.D}, P2/Z, [X17, Z17.D,LSL #3]    [30]

0x4239ec ST1D	{Z24.D}, P2, [V25.D]    [5]

0x4239f0 ADD	Z25.D, Z28.D, Z26.D

0x4239f4 LD1D	{Z24.D}, P2/Z, [X1, Z17.D,LSL #3]    [29]

0x4239f8 ST1D	{Z24.D}, P2, [V25.D]    [4]

0x4239fc MUL	Z25.D, Z5.D, Z27.D

0x423a00 MUL	Z27.D, Z6.D, Z27.D

0x423a04 ADR	Z25.D, [Z20, Z25.D,LSL #3]    [8]

0x423a08 ADR	Z27.D, [Z22, Z27.D,LSL #3]    [24]

0x423a0c ADR	Z28.D, [Z25, Z23.D,SXTW #3]    [3]

0x423a10 LD1D	{Z24.D}, P1/Z, [X17, Z17.D,LSL #3]    [30]

0x423a14 ADR	Z23.D, [Z27, Z23.D,SXTW #3]    [28]

0x423a18 ST1D	{Z24.D}, P1, [V28.D]    [21]

0x423a1c LD1D	{Z24.D}, P1/Z, [X1, Z17.D,LSL #3]    [29]

0x423a20 ST1D	{Z24.D}, P1, [V23.D]    [9]

0x423a24 ADD	Z24.D, Z25.D, Z26.D

0x423a28 LD1D	{Z23.D}, P2/Z, [X17, Z17.D,LSL #3]    [30]

0x423a2c ST1D	{Z23.D}, P2, [V24.D]    [2]

0x423a30 ADD	Z24.D, Z27.D, Z26.D

0x423a34 LD1D	{Z23.D}, P2/Z, [X1, Z17.D,LSL #3]    [29]

0x423a38 ST1D	{Z23.D}, P2, [V24.D]    [1]

0x423a3c CBNZ	X7, 423900

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 85 - 98

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.15 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37 - 1.57
Bottlenecks	P8, P10,
Function	generate_chunk(int, global_variables&) [clone .omp_outlined.2]
Source	generate_chunk.cpp:85-98,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.75 - 20.00
CQA cycles if no scalar integer	12.75 - 20.00
CQA cycles if FP arith vectorized	12.75 - 20.00
CQA cycles if fully vectorized	11.13 - 20.00
Front-end cycles	9.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	12.75
P9 cycles	12.75
P10 cycles	12.75
P11 cycles	12.75
P12 cycles	9.33
P13 cycles	9.33
P14 cycles	9.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	72.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.60 - 33.88
Bytes prefetched	0.00
Bytes loaded	272.00
Bytes stored	160.00
Stride 0	7.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	2.00
Vectorization ratio all	75.64
Vectorization ratio load	51.61
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	44.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	89.74
Vector-efficiency ratio load	75.81
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.15 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37 - 1.57
Bottlenecks	P8, P10,
Function	generate_chunk(int, global_variables&) [clone .omp_outlined.2]
Source	generate_chunk.cpp:85-98,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.75 - 20.00
CQA cycles if no scalar integer	12.75 - 20.00
CQA cycles if FP arith vectorized	12.75 - 20.00
CQA cycles if fully vectorized	11.13 - 20.00
Front-end cycles	9.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	12.75
P9 cycles	12.75
P10 cycles	12.75
P11 cycles	12.75
P12 cycles	9.33
P13 cycles	9.33
P14 cycles	9.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	72.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.60 - 33.88
Bytes prefetched	0.00
Bytes loaded	272.00
Bytes stored	160.00
Stride 0	7.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	2.00
Vectorization ratio all	75.64
Vectorization ratio load	51.61
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	44.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	89.74
Vector-efficiency ratio load	75.81
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk(int, global_variables&) [clone .omp_outlined.2]
Source file and lines	generate_chunk.cpp:85-98
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 89% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

51% of VPU loads are used in vector version.
44% of VPU addition or subtraction instructions are used in vector version.
81% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 272 bytes. The binary loop is storing 160 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	1.00	1.00	12.75	12.75	12.75	12.75	9.33	9.33	9.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	1.00	1.00	12.75	12.75	12.75	12.75	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Data deps.	2.00
Overall L1	12.75-20.00

Vectorization ratios

INT

all	74%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	76%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	81%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

14% of peak load performance is reached (13.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD X12, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LD1RD {Z25.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z26.D, Z26.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z24.D, Z23.D, Z2.D																					vect (100.0%)
LSL Z28.D, Z23.D, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SUB Z24.D, Z0.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LSL Z27.D, Z24.D, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z27.D, Z27.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ASR Z27.D, Z27.D, #-31	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [X4, Z27.D]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMGE P1.D, P0/Z, Z27.D, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X4, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X20, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMGT P1.D, P1/Z, Z27.D, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
ADD Z25.D, Z28.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z27, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z27.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ASR Z25.D, Z25.D, #-31	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z28.D, Z6.D, Z27.D																					vect (100.0%)
LD1D {Z25.D}, P1/Z, [X5, Z25.D]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z28.D, [Z22, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMGE P1.D, P1/Z, Z25.D, Z26.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X5, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z23.D, Z2.D, Z23.D																					vect (100.0%)
LD1D {Z26.D}, P1/Z, [X21, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
SUB Z23.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z21.D, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGT P1.D, P1/Z, Z26.D, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MUL Z26.D, Z3.D, Z27.D																					vect (100.0%)
LD1D {Z25.D}, P1/Z, [X11, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z26.D, [Z18, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z25.D}, P1, [V26.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z26.D, Z4.D, Z27.D																					vect (100.0%)
LD1D {Z25.D}, P1/Z, [X14, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z26.D, [Z19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z25.D}, P1, [V26.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z25.D, Z5.D, Z27.D																					vect (100.0%)
ADD Z27.D, Z27.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z25.D, [Z20, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z29.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z26.D}, P1, [V29.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADR Z29.D, [Z28, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z26.D}, P1/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z26.D}, P1, [V29.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MOVPRFX Z26, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z26.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CMPGE P2.D, P1/Z, Z24.D, Z26.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
ADR Z26.D, [Z16, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z25.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADD Z25.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z25.D, Z5.D, Z27.D																					vect (100.0%)
MUL Z27.D, Z6.D, Z27.D																					vect (100.0%)
ADR Z25.D, [Z20, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z22, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z24.D}, P1/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z23.D, [Z27, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z24.D}, P1, [V28.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z24.D}, P1, [V23.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADD Z24.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z23.D}, P2, [V24.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADD Z24.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z23.D}, P2, [V24.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X7, 423900 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	generate_chunk(int, global_variables&) [clone .omp_outlined.2]
Source file and lines	generate_chunk.cpp:85-98
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 89% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

51% of VPU loads are used in vector version.
44% of VPU addition or subtraction instructions are used in vector version.
81% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 272 bytes. The binary loop is storing 160 bytes.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	1.00	1.00	12.75	12.75	12.75	12.75	9.33	9.33	9.33	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	1.00	1.00	12.75	12.75	12.75	12.75	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Data deps.	2.00
Overall L1	12.75-20.00

Vectorization ratios

INT

all	74%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	76%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	75%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	81%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

14% of peak load performance is reached (13.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD X12, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LD1RD {Z25.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DUP Z26.D, Z26.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z24.D, Z23.D, Z2.D																					vect (100.0%)
LSL Z28.D, Z23.D, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SUB Z24.D, Z0.D, Z24.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LSL Z27.D, Z24.D, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z27.D, Z27.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ASR Z27.D, Z27.D, #-31	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [X4, Z27.D]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMGE P1.D, P0/Z, Z27.D, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X4, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X20, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMGT P1.D, P1/Z, Z27.D, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
ADD Z25.D, Z28.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z27, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z27.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ASR Z25.D, Z25.D, #-31	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z28.D, Z6.D, Z27.D																					vect (100.0%)
LD1D {Z25.D}, P1/Z, [X5, Z25.D]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z28.D, [Z22, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMGE P1.D, P1/Z, Z25.D, Z26.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X5, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z23.D, Z2.D, Z23.D																					vect (100.0%)
LD1D {Z26.D}, P1/Z, [X21, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
SUB Z23.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z21.D, Z21.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGT P1.D, P1/Z, Z26.D, Z25.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MUL Z26.D, Z3.D, Z27.D																					vect (100.0%)
LD1D {Z25.D}, P1/Z, [X11, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z26.D, [Z18, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z25.D}, P1, [V26.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z26.D, Z4.D, Z27.D																					vect (100.0%)
LD1D {Z25.D}, P1/Z, [X14, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z26.D, [Z19, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z25.D}, P1, [V26.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z25.D, Z5.D, Z27.D																					vect (100.0%)
ADD Z27.D, Z27.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z25.D, [Z20, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z29.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z26.D}, P1, [V29.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADR Z29.D, [Z28, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z26.D}, P1/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z26.D}, P1, [V29.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MOVPRFX Z26, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z26.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CMPGE P2.D, P1/Z, Z24.D, Z26.D	1	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
ADR Z26.D, [Z16, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z25.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADD Z25.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z25.D, Z5.D, Z27.D																					vect (100.0%)
MUL Z27.D, Z6.D, Z27.D																					vect (100.0%)
ADR Z25.D, [Z20, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z22, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z24.D}, P1/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z23.D, [Z27, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z24.D}, P1, [V28.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z24.D}, P1, [V23.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADD Z24.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X17, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z23.D}, P2, [V24.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ADD Z24.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P2/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ST1D {Z23.D}, P2, [V24.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X7, 423900 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0x720>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code