OV - exec - Loop 240

	Loop Id: 240	Module: exec	Source: flux_calc.cpp:37-40 [...]	Coverage: 4.08%

0x4228e0 MOVPRFX	Z31, Z30

0x4228e4 SDIV	Z31.D, P0/M, Z31.D, Z1.D

0x4228e8 LDR	D11, [X19]    [32]

0x4228ec DECD	X25, ALL

0x4228f0 FMUL	D11, D11, D20

0x4228f4 DUP	Z11.D, Z11.D[0]

0x4228f8 ADD	Z9.D, Z2.D, Z31.D

0x4228fc MSB	Z31.D, P0/M, Z1.D, Z30.D

0x422900 ADD	Z30.D, Z30.D, Z0.D

0x422904 MOVPRFX	Z8, Z9

0x422908 SXTW	Z8.D, P0/M, Z9.D

0x42290c ADD	Z9.D, Z9.D, #1

0x422910 SXTW	Z9.D, P0/M, Z9.D

0x422914 MUL	Z10.D, Z4.D, Z8.D

0x422918 MUL	Z12.D, Z5.D, Z8.D

0x42291c ADD	Z31.D, Z3.D, Z31.D

0x422920 MUL	Z14.D, Z6.D, Z8.D

0x422924 MUL	Z13.D, Z5.D, Z9.D

0x422928 MUL	Z9.D, Z6.D, Z9.D

0x42292c ADR	Z10.D, [Z21, Z10.D,LSL #3]    [8]

0x422930 ADR	Z12.D, [Z22, Z12.D,LSL #3]    [14]

0x422934 ADR	Z14.D, [Z23, Z14.D,LSL #3]    [20]

0x422938 ADR	Z13.D, [Z22, Z13.D,LSL #3]    [14]

0x42293c ADR	Z10.D, [Z10, Z31.D,SXTW #3]    [5]

0x422940 ADR	Z12.D, [Z12, Z31.D,SXTW #3]    [13]

0x422944 ADR	Z14.D, [Z14, Z31.D,SXTW #3]    [24]

0x422948 ADR	Z9.D, [Z23, Z9.D,LSL #3]    [20]

0x42294c ADR	Z13.D, [Z13, Z31.D,SXTW #3]    [19]

0x422950 ADR	Z9.D, [Z9, Z31.D,SXTW #3]    [16]

0x422954 LD1D	{Z10.D}, P0/Z, [V10.D]    [4]

0x422958 LD1D	{Z12.D}, P0/Z, [V12.D]    [12]

0x42295c LD1D	{Z14.D}, P0/Z, [V14.D]    [23]

0x422960 FMUL	Z10.D, Z11.D, Z10.D

0x422964 LD1D	{Z13.D}, P0/Z, [V13.D]    [18]

0x422968 LD1D	{Z9.D}, P0/Z, [V9.D]    [15]

0x42296c FADD	Z11.D, Z12.D, Z13.D

0x422970 ADR	Z13.D, [Z27, Z31.D,SXTW #3]    [28]

0x422974 FADD	Z11.D, Z11.D, Z14.D

0x422978 MUL	Z14.D, Z18.D, Z8.D

0x42297c FADD	Z9.D, Z11.D, Z9.D

0x422980 MUL	Z11.D, Z7.D, Z8.D

0x422984 FMUL	Z9.D, Z10.D, Z9.D

0x422988 ADR	Z14.D, [Z28, Z14.D,LSL #3]    [29]

0x42298c ADR	Z10.D, [Z24, Z11.D,LSL #3]    [25]

0x422990 MUL	Z11.D, Z17.D, Z8.D

0x422994 ADR	Z10.D, [Z10, Z31.D,SXTW #3]    [3]

0x422998 ST1D	{Z9.D}, P0, [V10.D]    [2]

0x42299c MUL	Z10.D, Z16.D, Z8.D

0x4229a0 MUL	Z8.D, Z19.D, Z8.D

0x4229a4 ADR	Z11.D, [Z26, Z11.D,LSL #3]    [27]

0x4229a8 LDR	D9, [X19]    [32]

0x4229ac ADR	Z12.D, [Z11, Z31.D,SXTW #3]    [7]

0x4229b0 ADD	Z11.D, Z11.D, Z13.D

0x4229b4 ADD	Z13.D, Z14.D, Z13.D

0x4229b8 ADR	Z14.D, [Z14, Z31.D,SXTW #3]    [22]

0x4229bc ADR	Z10.D, [Z25, Z10.D,LSL #3]    [26]

0x4229c0 LD1D	{Z12.D}, P0/Z, [V12.D]    [11]

0x4229c4 ADR	Z8.D, [Z29, Z8.D,LSL #3]    [30]

0x4229c8 ADR	Z10.D, [Z10, Z31.D,SXTW #3]    [1]

0x4229cc FMUL	D9, D9, D20

0x4229d0 ADR	Z31.D, [Z8, Z31.D,SXTW #3]    [10]

0x4229d4 LD1D	{Z11.D}, P0/Z, [V11.D]    [6]

0x4229d8 LD1D	{Z14.D}, P0/Z, [V14.D]    [21]

0x4229dc LD1D	{Z13.D}, P0/Z, [V13.D]    [17]

0x4229e0 DUP	Z9.D, Z9.D[0]

0x4229e4 LD1D	{Z10.D}, P0/Z, [V10.D]    [31]

0x4229e8 FMUL	Z9.D, Z9.D, Z10.D

0x4229ec FADD	Z10.D, Z12.D, Z11.D

0x4229f0 FADD	Z10.D, Z10.D, Z14.D

0x4229f4 FADD	Z10.D, Z10.D, Z13.D

0x4229f8 FMUL	Z9.D, Z9.D, Z10.D

0x4229fc ST1D	{Z9.D}, P0, [V31.D]    [9]

0x422a00 CBNZ	X25, 4228e0

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp: 37 - 40

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.04 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.24 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.87 - 1.36
Bottlenecks	P8, P10,
Function	flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	flux_calc.cpp:37-40,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	14.75 - 20.00
CQA cycles if no scalar integer	14.25 - 20.00
CQA cycles if FP arith vectorized	14.50 - 20.00
CQA cycles if fully vectorized	11.88 - 20.00
Front-end cycles	7.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	14.75
P9 cycles	14.75
P10 cycles	14.75
P11 cycles	14.75
P12 cycles	4.67
P13 cycles	4.67
P14 cycles	4.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	63.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.49 - 1.10
Nb FLOP add-sub	12.00
Nb FLOP mul	10.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.40 - 14.10
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	20.00
Stride indirect	11.00
Vectorization ratio all	61.11
Vectorization ratio load	30.30
Vectorization ratio store	100.00
Vectorization ratio mul	87.50
Vectorization ratio add_sub	35.29
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	81.94
Vector-efficiency ratio load	65.15
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	93.75
Vector-efficiency ratio add_sub	67.65
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.04 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.24 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.87 - 1.36
Bottlenecks	P8, P10,
Function	flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	flux_calc.cpp:37-40,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	14.75 - 20.00
CQA cycles if no scalar integer	14.25 - 20.00
CQA cycles if FP arith vectorized	14.50 - 20.00
CQA cycles if fully vectorized	11.88 - 20.00
Front-end cycles	7.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	14.75
P9 cycles	14.75
P10 cycles	14.75
P11 cycles	14.75
P12 cycles	4.67
P13 cycles	4.67
P14 cycles	4.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	63.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.49 - 1.10
Nb FLOP add-sub	12.00
Nb FLOP mul	10.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.40 - 14.10
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	20.00
Stride indirect	11.00
Vectorization ratio all	61.11
Vectorization ratio load	30.30
Vectorization ratio store	100.00
Vectorization ratio mul	87.50
Vectorization ratio add_sub	35.29
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	81.94
Vector-efficiency ratio load	65.15
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	93.75
Vector-efficiency ratio add_sub	67.65
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	flux_calc.cpp:37-40
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37-40
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all VPU instructions).

Details

61% of VPU instructions are used in vector version (process two or more data elements in vector registers):

30% of VPU loads are used in vector version.
35% of VPU addition or subtraction instructions are used in vector version.
87% of VPU multiply instructions are used in vector version.
66% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

12: addition or subtraction
10: multiply

The binary loop is loading 176 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	73
loop length	292
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	14.75	14.75	14.75	14.75	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	14.75	14.75	14.75	14.75	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.88
Data deps.	2.00
Overall L1	14.75-20.00

Vectorization ratios

INT

all	56%
load	30%
store	100%
mul	100%
add-sub	21%
fma	100%
other	71%

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	61%
load	30%
store	100%
mul	87%
add-sub	35%
fma	100%
div/sqrt	100%
other	66%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

9% of peak load performance is reached (8.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4228e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z31.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
LDR D11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DECD X25, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
FMUL D11, D11, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
DUP Z11.D, Z11.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z9.D, Z2.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z31.D, P0/M, Z1.D, Z30.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z30.D, Z30.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z8.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z9.D, Z9.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z10.D, Z4.D, Z8.D																					vect (100.0%)
MUL Z12.D, Z5.D, Z8.D																					vect (100.0%)
ADD Z31.D, Z3.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z14.D, Z6.D, Z8.D																					vect (100.0%)
MUL Z13.D, Z5.D, Z9.D																					vect (100.0%)
MUL Z9.D, Z6.D, Z9.D																					vect (100.0%)
ADR Z10.D, [Z21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z22, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z23, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z22, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z14, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z13, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z10.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z11.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z13.D, [Z27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z11.D, Z11.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z14.D, Z18.D, Z8.D																					vect (100.0%)
FADD Z9.D, Z11.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z11.D, Z7.D, Z8.D																					vect (100.0%)
FMUL Z9.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z14.D, [Z28, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z24, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z11.D, Z17.D, Z8.D																					vect (100.0%)
ADR Z10.D, [Z10, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z9.D}, P0, [V10.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z10.D, Z16.D, Z8.D																					vect (100.0%)
MUL Z8.D, Z19.D, Z8.D																					vect (100.0%)
ADR Z11.D, [Z26, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADR Z12.D, [Z11, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z11.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z13.D, Z14.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z14.D, [Z14, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z25, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z8.D, [Z29, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D9, D9, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
ADR Z31.D, [Z8, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
DUP Z9.D, Z9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z9.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z10.D, Z12.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z10.D, Z10.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z10.D, Z10.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z9.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z9.D}, P0, [V31.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X25, 4228e0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	flux_calc.cpp:37-40
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37-40
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all VPU instructions).

Details

61% of VPU instructions are used in vector version (process two or more data elements in vector registers):

30% of VPU loads are used in vector version.
35% of VPU addition or subtraction instructions are used in vector version.
87% of VPU multiply instructions are used in vector version.
66% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

12: addition or subtraction
10: multiply

The binary loop is loading 176 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	73
loop length	292
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	14.75	14.75	14.75	14.75	4.67	4.67	4.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	14.75	14.75	14.75	14.75	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.88
Data deps.	2.00
Overall L1	14.75-20.00

Vectorization ratios

INT

all	56%
load	30%
store	100%
mul	100%
add-sub	21%
fma	100%
other	71%

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	61%
load	30%
store	100%
mul	87%
add-sub	35%
fma	100%
div/sqrt	100%
other	66%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

9% of peak load performance is reached (8.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4228e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z31.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
LDR D11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
DECD X25, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
FMUL D11, D11, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
DUP Z11.D, Z11.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z9.D, Z2.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z31.D, P0/M, Z1.D, Z30.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z30.D, Z30.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z8.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z9.D, Z9.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z10.D, Z4.D, Z8.D																					vect (100.0%)
MUL Z12.D, Z5.D, Z8.D																					vect (100.0%)
ADD Z31.D, Z3.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z14.D, Z6.D, Z8.D																					vect (100.0%)
MUL Z13.D, Z5.D, Z9.D																					vect (100.0%)
MUL Z9.D, Z6.D, Z9.D																					vect (100.0%)
ADR Z10.D, [Z21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z22, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z23, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z22, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z14, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z13, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z10.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z11.D, Z12.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z13.D, [Z27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD Z11.D, Z11.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z14.D, Z18.D, Z8.D																					vect (100.0%)
FADD Z9.D, Z11.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z11.D, Z7.D, Z8.D																					vect (100.0%)
FMUL Z9.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ADR Z14.D, [Z28, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z24, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z11.D, Z17.D, Z8.D																					vect (100.0%)
ADR Z10.D, [Z10, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z9.D}, P0, [V10.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z10.D, Z16.D, Z8.D																					vect (100.0%)
MUL Z8.D, Z19.D, Z8.D																					vect (100.0%)
ADR Z11.D, [Z26, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADR Z12.D, [Z11, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z11.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z13.D, Z14.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z14.D, [Z14, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z25, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z8.D, [Z29, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D9, D9, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
ADR Z31.D, [Z8, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
DUP Z9.D, Z9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z9.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z10.D, Z12.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z10.D, Z10.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z10.D, Z10.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z9.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z9.D}, P0, [V31.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X25, 4228e0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code