OV - exec - Loop 238

	Loop Id: 238	Module: exec	Source: field_summary.cpp:77-91 [...]	Coverage: 0.30%

0x422248 MOVPRFX	Z11, Z10

0x42224c SXTW	Z11.D, P0/M, Z10.D

0x422250 DUP	Z25.D, #8

0x422254 DUP	Z29.D, #0

0x422258 DECD	X7, ALL

0x42225c MOVPRFX	Z12, Z11

0x422260 SDIV	Z12.D, P0/M, Z12.D, Z22.D

0x422264 MOVPRFX	Z11, Z10

0x422268 MLS	Z11.D, P0/M, Z12.D, Z2.D

0x42226c ADD	Z12.D, Z4.D, Z12.D

0x422270 ADD	Z10.D, Z10.D, Z1.D

0x422274 SXTW	Z12.D, P0/M, Z12.D

0x422278 MUL	Z15.D, Z6.D, Z12.D

0x42227c MUL	Z13.D, Z5.D, Z12.D

0x422280 ADD	Z11.D, Z3.D, Z11.D

0x422284 ADR	Z25.D, [Z25, Z11.D,SXTW #3]    [22]

0x422288 ADR	Z15.D, [Z26, Z15.D,LSL #3]    [23]

0x42228c ADR	Z13.D, [Z24, Z13.D,LSL #3]    [15]

0x422290 ADR	Z0.D, [Z15, Z11.D,SXTW #3]    [18]

0x422294 ADR	Z14.D, [Z13, Z11.D,SXTW #3]    [8]

0x422298 ADD	Z13.D, Z13.D, Z25.D

0x42229c LD1D	{Z0.D}, P0/Z, [V0.D]    [27]

0x4222a0 LD1D	{Z14.D}, P0/Z, [V14.D]    [12]

0x4222a4 FMUL	Z0.D, Z0.D, Z0.D

0x4222a8 FMLA	Z0.D, P0/M, Z14.D, Z14.D

0x4222ac ADD	Z14.D, Z15.D, Z25.D

0x4222b0 LD1D	{Z13.D}, P0/Z, [V13.D]    [6]

0x4222b4 ORR	Z15.D, Z12.D, Z12.D

0x4222b8 LD1D	{Z14.D}, P0/Z, [V14.D]    [11]

0x4222bc FMAD	Z0.D, P0/M, Z28.D, Z29.D

0x4222c0 ADD	Z15.D, Z15.D, #1

0x4222c4 FMUL	Z14.D, Z14.D, Z14.D

0x4222c8 FMAD	Z13.D, P0/M, Z13.D, Z14.D

0x4222cc MUL	Z14.D, Z7.D, Z12.D

0x4222d0 FMLA	Z0.D, P0/M, Z13.D, Z28.D

0x4222d4 MUL	Z13.D, Z5.D, Z15.D

0x4222d8 MUL	Z15.D, Z6.D, Z15.D

0x4222dc ADR	Z14.D, [Z30, Z14.D,LSL #3]    [1]

0x4222e0 ADR	Z14.D, [Z14, Z11.D,SXTW #3]    [10]

0x4222e4 ADR	Z13.D, [Z24, Z13.D,LSL #3]    [15]

0x4222e8 ADR	Z15.D, [Z26, Z15.D,LSL #3]    [23]

0x4222ec LD1D	{Z14.D}, P0/Z, [V14.D]    [9]

0x4222f0 ADR	Z29.D, [Z13, Z11.D,SXTW #3]    [5]

0x4222f4 ADD	Z13.D, Z13.D, Z25.D

0x4222f8 ADD	Z25.D, Z15.D, Z25.D

0x4222fc ADR	Z15.D, [Z15, Z11.D,SXTW #3]    [17]

0x422300 LD1D	{Z15.D}, P0/Z, [V15.D]    [16]

0x422304 LD1D	{Z29.D}, P0/Z, [V29.D]    [26]

0x422308 FADD	Z19.D, Z14.D, Z19.D

0x42230c FMUL	Z15.D, Z15.D, Z15.D

0x422310 LD1D	{Z25.D}, P0/Z, [V25.D]    [21]

0x422314 LD1D	{Z13.D}, P0/Z, [V13.D]    [4]

0x422318 FMUL	Z25.D, Z25.D, Z25.D

0x42231c FMAD	Z29.D, P0/M, Z29.D, Z15.D

0x422320 FMLA	Z25.D, P0/M, Z13.D, Z13.D

0x422324 MUL	Z13.D, Z21.D, Z12.D

0x422328 FMLA	Z0.D, P0/M, Z29.D, Z28.D

0x42232c MUL	Z29.D, Z16.D, Z12.D

0x422330 FMLA	Z0.D, P0/M, Z25.D, Z28.D

0x422334 ADR	Z25.D, [Z31, Z29.D,LSL #3]    [2]

0x422338 ADR	Z29.D, [Z9, Z13.D,LSL #3]    [7]

0x42233c ADR	Z25.D, [Z25, Z11.D,SXTW #3]    [20]

0x422340 ADR	Z29.D, [Z29, Z11.D,SXTW #3]    [25]

0x422344 LD1D	{Z25.D}, P0/Z, [V25.D]    [19]

0x422348 FMUL	Z25.D, Z14.D, Z25.D

0x42234c MOVPRFX	Z13, Z25

0x422350 FMUL	Z13.D, P0/M, Z13.D, #0

0x422354 FADD	Z20.D, Z25.D, Z20.D

0x422358 FMLA	Z27.D, P0/M, Z13.D, Z0.D

0x42235c MUL	Z0.D, Z17.D, Z12.D

0x422360 LD1D	{Z29.D}, P0/Z, [V29.D]    [24]

0x422364 FMLA	Z18.D, P0/M, Z14.D, Z29.D

0x422368 ADR	Z0.D, [Z8, Z0.D,LSL #3]    [3]

0x42236c ADR	Z0.D, [Z0, Z11.D,SXTW #3]    [14]

0x422370 LD1D	{Z0.D}, P0/Z, [V0.D]    [13]

0x422374 FMLA	Z23.D, P0/M, Z25.D, Z0.D

0x422378 CBNZ	W7, 422248

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 77 - 91

--------------------------------------------------------------------------------

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.94 - 1.19
Bottlenecks	P8, P10,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	field_summary.cpp:77-91,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	16.75 - 20.00
CQA cycles if no scalar integer	16.75 - 20.00
CQA cycles if FP arith vectorized	16.75 - 20.00
CQA cycles if fully vectorized	14.16 - 20.00
Front-end cycles	8.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	16.75
P9 cycles	16.75
P10 cycles	16.75
P11 cycles	16.75
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	69.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.58 - 3.00
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	22.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60 - 11.46
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	18.00
Stride indirect	9.00
Vectorization ratio all	68.42
Vectorization ratio load	41.38
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	37.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	85.69
Vector-efficiency ratio load	70.69
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	68.97
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	79.17

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.94 - 1.19
Bottlenecks	P8, P10,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	field_summary.cpp:77-91,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	16.75 - 20.00
CQA cycles if no scalar integer	16.75 - 20.00
CQA cycles if FP arith vectorized	16.75 - 20.00
CQA cycles if fully vectorized	14.16 - 20.00
Front-end cycles	8.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	16.75
P9 cycles	16.75
P10 cycles	16.75
P11 cycles	16.75
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	4.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	69.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.58 - 3.00
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	22.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60 - 11.46
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	18.00
Stride indirect	9.00
Vectorization ratio all	68.42
Vectorization ratio load	41.38
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	37.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	85.69
Vector-efficiency ratio load	70.69
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	68.97
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	79.17

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:77-91
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77-91
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
37% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 22 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (22 inside FMA instructions)
34: multiply (22 inside FMA instructions)

The binary loop is loading 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	77
loop length	308
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	16.75	16.75	16.75	16.75	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	16.75	16.75	16.75	16.75	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.63
Data deps.	2.00
Overall L1	16.75-20.00

Vectorization ratios

INT

all	57%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422248

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z11.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z25.D, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z12.D, P0/M, Z12.D, Z22.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z11.D, P0/M, Z12.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z12.D, Z4.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z10.D, Z10.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z12.D, P0/M, Z12.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z15.D, Z6.D, Z12.D																					vect (100.0%)
MUL Z13.D, Z5.D, Z12.D																					vect (100.0%)
ADD Z11.D, Z3.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z25.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z15.D, [Z26, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z15, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z13.D, Z13.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z0.D, P0/M, Z14.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADD Z14.D, Z15.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ORR Z15.D, Z12.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMAD Z0.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADD Z15.D, Z15.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z14.D, Z14.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAD Z13.D, P0/M, Z13.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z14.D, Z7.D, Z12.D																					vect (100.0%)
FMLA Z0.D, P0/M, Z13.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z13.D, Z5.D, Z15.D																					vect (100.0%)
MUL Z15.D, Z6.D, Z15.D																					vect (100.0%)
ADR Z14.D, [Z30, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z14, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z15.D, [Z26, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z29.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z13.D, Z13.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z25.D, Z15.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z15.D, [Z15, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z29.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z19.D, Z14.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z15.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAD Z29.D, P0/M, Z29.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMLA Z25.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z13.D, Z21.D, Z12.D																					vect (100.0%)
FMLA Z0.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z29.D, Z16.D, Z12.D																					vect (100.0%)
FMLA Z0.D, P0/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADR Z25.D, [Z31, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z29.D, [Z9, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z29.D, [Z29, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z25.D, Z14.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z13, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMUL Z13.D, P0/M, Z13.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z20.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMLA Z27.D, P0/M, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z0.D, Z17.D, Z12.D																					vect (100.0%)
LD1D {Z29.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMLA Z18.D, P0/M, Z14.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADR Z0.D, [Z8, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMLA Z23.D, P0/M, Z25.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
CBNZ W7, 422248 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:77-91
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77-91
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
37% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 22 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (22 inside FMA instructions)
34: multiply (22 inside FMA instructions)

The binary loop is loading 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	77
loop length	308
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	16.75	16.75	16.75	16.75	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	16.75	16.75	16.75	16.75	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.63
Data deps.	2.00
Overall L1	16.75-20.00

Vectorization ratios

INT

all	57%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	68%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422248

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z11.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z25.D, #8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z29.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z12.D, P0/M, Z12.D, Z22.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z11.D, P0/M, Z12.D, Z2.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z12.D, Z4.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z10.D, Z10.D, Z1.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z12.D, P0/M, Z12.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z15.D, Z6.D, Z12.D																					vect (100.0%)
MUL Z13.D, Z5.D, Z12.D																					vect (100.0%)
ADD Z11.D, Z3.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z25.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z15.D, [Z26, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z15, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z13.D, Z13.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z0.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z0.D, P0/M, Z14.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADD Z14.D, Z15.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ORR Z15.D, Z12.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMAD Z0.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADD Z15.D, Z15.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z14.D, Z14.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAD Z13.D, P0/M, Z13.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z14.D, Z7.D, Z12.D																					vect (100.0%)
FMLA Z0.D, P0/M, Z13.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z13.D, Z5.D, Z15.D																					vect (100.0%)
MUL Z15.D, Z6.D, Z15.D																					vect (100.0%)
ADR Z14.D, [Z30, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z14, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z15.D, [Z26, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z29.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z13.D, Z13.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z25.D, Z15.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z15.D, [Z15, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z29.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z19.D, Z14.D, Z19.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z15.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAD Z29.D, P0/M, Z29.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMLA Z25.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z13.D, Z21.D, Z12.D																					vect (100.0%)
FMLA Z0.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z29.D, Z16.D, Z12.D																					vect (100.0%)
FMLA Z0.D, P0/M, Z25.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADR Z25.D, [Z31, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z29.D, [Z9, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z29.D, [Z29, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z25.D, Z14.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z13, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMUL Z13.D, P0/M, Z13.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FADD Z20.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMLA Z27.D, P0/M, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MUL Z0.D, Z17.D, Z12.D																					vect (100.0%)
LD1D {Z29.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMLA Z18.D, P0/M, Z14.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
ADR Z0.D, [Z8, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMLA Z23.D, P0/M, Z25.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
CBNZ W7, 422248 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code