OV - exec - Loop 206

	Loop Id: 206	Module: exec	Source: build_field.cpp:119-128 [...]	Coverage: 0.02%

0x41f7e0 MOVPRFX	Z28, Z27

0x41f7e4 SDIV	Z28.D, P0/M, Z28.D, Z1.D

0x41f7e8 DECD	X23, ALL

0x41f7ec MOVPRFX	Z29, Z27

0x41f7f0 MLS	Z29.D, P0/M, Z28.D, Z1.D

0x41f7f4 SXTW	Z28.D, P0/M, Z28.D

0x41f7f8 ADD	Z27.D, Z27.D, Z0.D

0x41f7fc MUL	Z30.D, Z2.D, Z28.D

0x41f800 ADR	Z30.D, [Z18, Z30.D,LSL #3]    [22]

0x41f804 ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [9]

0x41f808 ST1D	{Z19.D}, P0, [V30.D]    [8]

0x41f80c MUL	Z30.D, Z3.D, Z28.D

0x41f810 ADR	Z30.D, [Z20, Z30.D,LSL #3]    [3]

0x41f814 ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [7]

0x41f818 ST1D	{Z19.D}, P0, [V30.D]    [6]

0x41f81c MUL	Z30.D, Z4.D, Z28.D

0x41f820 ADR	Z30.D, [Z21, Z30.D,LSL #3]    [10]

0x41f824 ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [5]

0x41f828 ST1D	{Z19.D}, P0, [V30.D]    [4]

0x41f82c MUL	Z30.D, Z5.D, Z28.D

0x41f830 ADR	Z30.D, [Z22, Z30.D,LSL #3]    [11]

0x41f834 ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [20]

0x41f838 ST1D	{Z19.D}, P0, [V30.D]    [18]

0x41f83c MUL	Z30.D, Z6.D, Z28.D

0x41f840 ADR	Z30.D, [Z23, Z30.D,LSL #3]    [12]

0x41f844 ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [17]

0x41f848 ST1D	{Z19.D}, P0, [V30.D]    [16]

0x41f84c MUL	Z30.D, Z7.D, Z28.D

0x41f850 ADR	Z30.D, [Z24, Z30.D,LSL #3]    [13]

0x41f854 ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [15]

0x41f858 ST1D	{Z19.D}, P0, [V30.D]    [14]

0x41f85c MUL	Z30.D, Z16.D, Z28.D

0x41f860 MUL	Z28.D, Z17.D, Z28.D

0x41f864 ADR	Z30.D, [Z25, Z30.D,LSL #3]    [19]

0x41f868 ADR	Z28.D, [Z26, Z28.D,LSL #3]    [21]

0x41f86c ADR	Z30.D, [Z30, Z29.D,SXTW #3]    [2]

0x41f870 ADR	Z28.D, [Z28, Z29.D,SXTW #3]    [24]

0x41f874 ST1D	{Z19.D}, P0, [V30.D]    [1]

0x41f878 ST1D	{Z19.D}, P0, [V28.D]    [23]

0x41f87c CBNZ	X23, 41f7e0

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 119 - 128

--------------------------------------------------------------------------------

119:     for (int j = (0); j < (yrange); j++) {

120:       for (int i = (0); i < (xrange); i++) {

121:         field.density0(i, j) = 0.0;

122:         field.density1(i, j) = 0.0;

123:         field.energy0(i, j) = 0.0;

124:         field.energy1(i, j) = 0.0;

125:         field.pressure(i, j) = 0.0;

126:         field.viscosity(i, j) = 0.0;

127:         field.soundspeed(i, j) = 0.0;

128:         field.volume(i, j) = 0.0;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.36 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88 - 2.67
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined.2]
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	7.50 - 20.00
CQA cycles if no scalar integer	7.50 - 20.00
CQA cycles if FP arith vectorized	7.50 - 20.00
CQA cycles if fully vectorized	5.50 - 20.00
Front-end cycles	4.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	32.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40 - 17.07
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	8.00
Vectorization ratio all	51.28
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	10.53
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	78.21
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	55.26
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.36 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88 - 2.67
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined.2]
Source	build_field.cpp:119-128,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	7.50 - 20.00
CQA cycles if no scalar integer	7.50 - 20.00
CQA cycles if FP arith vectorized	7.50 - 20.00
CQA cycles if fully vectorized	5.50 - 20.00
Front-end cycles	4.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	32.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40 - 17.07
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	8.00
Vectorization ratio all	51.28
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	10.53
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	78.21
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	55.26
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .omp_outlined.2]
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-128
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 78% of vector register length is used (average across all VPU instructions).

Details

51% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
10% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 128 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.00
Data deps.	2.00
Overall L1	7.50-20.00

Vectorization ratios

all	51%
load	0%
store	100%
mul	100%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z28, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z28.D, P0/M, Z28.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X23, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z29.D, P0/M, Z28.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z27.D, Z27.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z30.D, Z2.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z18, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z3.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z20, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z4.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z21, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z5.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z6.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z23, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z7.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z16.D, Z28.D																					vect (100.0%)
MUL Z28.D, Z17.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z26, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z28, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ST1D {Z19.D}, P0, [V28.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X23, 41f7e0 <_Z11build_fieldR16global_variables.omp_outlined.2+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field(global_variables&) [clone .omp_outlined.2]
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-128
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 78% of vector register length is used (average across all VPU instructions).

Details

51% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
10% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 128 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.50	7.50	7.50	7.50	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.00
Data deps.	2.00
Overall L1	7.50-20.00

Vectorization ratios

all	51%
load	0%
store	100%
mul	100%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z28, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z28.D, P0/M, Z28.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X23, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z29.D, P0/M, Z28.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z27.D, Z27.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z30.D, Z2.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z18, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z3.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z20, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z4.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z21, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z5.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z6.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z23, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z7.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z30.D, Z16.D, Z28.D																					vect (100.0%)
MUL Z28.D, Z17.D, Z28.D																					vect (100.0%)
ADR Z30.D, [Z25, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z26, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z28, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z19.D}, P0, [V30.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ST1D {Z19.D}, P0, [V28.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X23, 41f7e0 <_Z11build_fieldR16global_variables.omp_outlined.2+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code