OV - exec - Loop 204

	Loop Id: 204	Module: exec	Source: build_field.cpp:101-113 [...]	Coverage: 0.02%

0x41f480 MOVPRFX	Z10, Z9

0x41f484 SDIV	Z10.D, P0/M, Z10.D, Z1.D

0x41f488 DECD	X30, ALL

0x41f48c MOVPRFX	Z11, Z9

0x41f490 MLS	Z11.D, P0/M, Z10.D, Z1.D

0x41f494 SXTW	Z10.D, P0/M, Z10.D

0x41f498 ADD	Z9.D, Z9.D, Z0.D

0x41f49c MUL	Z12.D, Z2.D, Z10.D

0x41f4a0 ADR	Z12.D, [Z21, Z12.D,LSL #3]    [5]

0x41f4a4 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [13]

0x41f4a8 ST1D	{Z22.D}, P0, [V12.D]    [11]

0x41f4ac MUL	Z12.D, Z3.D, Z10.D

0x41f4b0 ADR	Z12.D, [Z23, Z12.D,LSL #3]    [14]

0x41f4b4 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [10]

0x41f4b8 ST1D	{Z22.D}, P0, [V12.D]    [9]

0x41f4bc MUL	Z12.D, Z4.D, Z10.D

0x41f4c0 ADR	Z12.D, [Z24, Z12.D,LSL #3]    [15]

0x41f4c4 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [7]

0x41f4c8 ST1D	{Z22.D}, P0, [V12.D]    [6]

0x41f4cc MUL	Z12.D, Z5.D, Z10.D

0x41f4d0 ADR	Z12.D, [Z25, Z12.D,LSL #3]    [16]

0x41f4d4 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [33]

0x41f4d8 ST1D	{Z22.D}, P0, [V12.D]    [32]

0x41f4dc MUL	Z12.D, Z6.D, Z10.D

0x41f4e0 ADR	Z12.D, [Z26, Z12.D,LSL #3]    [24]

0x41f4e4 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [31]

0x41f4e8 ST1D	{Z22.D}, P0, [V12.D]    [30]

0x41f4ec MUL	Z12.D, Z7.D, Z10.D

0x41f4f0 ADR	Z12.D, [Z27, Z12.D,LSL #3]    [25]

0x41f4f4 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [29]

0x41f4f8 ST1D	{Z22.D}, P0, [V12.D]    [28]

0x41f4fc MUL	Z12.D, Z16.D, Z10.D

0x41f500 ADR	Z12.D, [Z28, Z12.D,LSL #3]    [26]

0x41f504 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [23]

0x41f508 ST1D	{Z22.D}, P0, [V12.D]    [22]

0x41f50c MUL	Z12.D, Z17.D, Z10.D

0x41f510 ADR	Z12.D, [Z29, Z12.D,LSL #3]    [27]

0x41f514 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [21]

0x41f518 ST1D	{Z22.D}, P0, [V12.D]    [20]

0x41f51c MUL	Z12.D, Z18.D, Z10.D

0x41f520 ADR	Z12.D, [Z30, Z12.D,LSL #3]    [4]

0x41f524 ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [19]

0x41f528 ST1D	{Z22.D}, P0, [V12.D]    [18]

0x41f52c MUL	Z12.D, Z19.D, Z10.D

0x41f530 ADR	Z12.D, [Z31, Z12.D,LSL #3]    [8]

0x41f534 MUL	Z10.D, Z20.D, Z10.D

0x41f538 ADR	Z10.D, [Z8, Z10.D,LSL #3]    [12]

0x41f53c ADR	Z12.D, [Z12, Z11.D,SXTW #3]    [17]

0x41f540 ADR	Z10.D, [Z10, Z11.D,SXTW #3]    [3]

0x41f544 ST1D	{Z22.D}, P0, [V12.D]    [1]

0x41f548 ST1D	{Z22.D}, P0, [V10.D]    [2]

0x41f54c CBNZ	X30, 41f480

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 101 - 113

--------------------------------------------------------------------------------

101:     for (int j = (0); j < (yrange + 1); j++) {

102:       for (int i = (0); i < (xrange + 1); i++) {

103:         field.work_array1(i, j) = 0.0;

104:         field.work_array2(i, j) = 0.0;

105:         field.work_array3(i, j) = 0.0;

106:         field.work_array4(i, j) = 0.0;

107:         field.work_array5(i, j) = 0.0;

108:         field.work_array6(i, j) = 0.0;

109:         field.work_array7(i, j) = 0.0;

110:         field.xvel0(i, j) = 0.0;

111:         field.xvel1(i, j) = 0.0;

112:         field.yvel0(i, j) = 0.0;

113:         field.yvel1(i, j) = 0.0;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.39 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.77 - 2.05
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined]
Source	build_field.cpp:101-113,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	9.75 - 20.00
CQA cycles if no scalar integer	9.75 - 20.00
CQA cycles if FP arith vectorized	9.75 - 20.00
CQA cycles if fully vectorized	7.00 - 20.00
Front-end cycles	5.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	9.75
P11 cycles	9.75
P12 cycles	5.50
P13 cycles	5.50
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	41.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.80 - 18.05
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	176.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	11.00
Vectorization ratio all	50.98
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	8.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	77.45
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	54.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.39 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.77 - 2.05
Bottlenecks	P8, P10,
Function	build_field(global_variables&) [clone .omp_outlined]
Source	build_field.cpp:101-113,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	9.75 - 20.00
CQA cycles if no scalar integer	9.75 - 20.00
CQA cycles if FP arith vectorized	9.75 - 20.00
CQA cycles if fully vectorized	7.00 - 20.00
Front-end cycles	5.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	9.75
P11 cycles	9.75
P12 cycles	5.50
P13 cycles	5.50
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	41.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.80 - 18.05
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	176.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	22.00
Stride indirect	11.00
Vectorization ratio all	50.98
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	8.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	77.45
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	54.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .omp_outlined]
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:101-113
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 77% of vector register length is used (average across all VPU instructions).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
8% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 176 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	9.75	9.75	9.75	9.75	5.50	5.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	9.75	9.75	9.75	9.75	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.13
Data deps.	2.00
Overall L1	9.75-20.00

Vectorization ratios

all	50%
load	0%
store	100%
mul	100%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

18% of peak store performance is reached (8.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z10.D, P0/M, Z10.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X30, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
MOVPRFX Z11, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z11.D, P0/M, Z10.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
SXTW Z10.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z9.D, Z9.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z12.D, Z2.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z21, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z3.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z23, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z4.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z24, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z5.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z6.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z26, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z7.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z27, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z16.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z28, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z17.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z29, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z18.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z30, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z19.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z31, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z10.D, Z20.D, Z10.D																					vect (100.0%)
ADR Z10.D, [Z8, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ST1D {Z22.D}, P0, [V10.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X30, 41f480 <_Z11build_fieldR16global_variables.omp_outlined+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field(global_variables&) [clone .omp_outlined]
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:101-113
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 77% of vector register length is used (average across all VPU instructions).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
8% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 176 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	9.75	9.75	9.75	9.75	5.50	5.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	9.75	9.75	9.75	9.75	5.50	5.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.13
Data deps.	2.00
Overall L1	9.75-20.00

Vectorization ratios

all	50%
load	0%
store	100%
mul	100%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

18% of peak store performance is reached (8.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z10.D, P0/M, Z10.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X30, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
MOVPRFX Z11, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z11.D, P0/M, Z10.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
SXTW Z10.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z9.D, Z9.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z12.D, Z2.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z21, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z3.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z23, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z4.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z24, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z5.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z6.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z26, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z7.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z27, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z16.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z28, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z17.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z29, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z18.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z30, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z12.D, Z19.D, Z10.D																					vect (100.0%)
ADR Z12.D, [Z31, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z10.D, Z20.D, Z10.D																					vect (100.0%)
ADR Z10.D, [Z8, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z12.D, [Z12, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z22.D}, P0, [V12.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ST1D {Z22.D}, P0, [V10.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X30, 41f480 <_Z11build_fieldR16global_variables.omp_outlined+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code