OV - exec - Loop 189

	Loop Id: 189	Module: exec	Source: advec_mom.cpp:109-139 [...]	Coverage: 4.53%

0x41df00 MOVPRFX	Z25, Z24

0x41df04 SDIV	Z25.D, P0/M, Z25.D, Z1.D

0x41df08 DECD	X2, ALL

0x41df0c ADD	Z26.D, Z2.D, Z25.D

0x41df10 MSB	Z25.D, P0/M, Z1.D, Z24.D

0x41df14 ADD	Z24.D, Z24.D, Z0.D

0x41df18 SXTW	Z26.D, P0/M, Z26.D

0x41df1c MUL	Z27.D, Z4.D, Z26.D

0x41df20 MUL	Z8.D, Z5.D, Z26.D

0x41df24 MUL	Z10.D, Z6.D, Z26.D

0x41df28 MUL	Z26.D, Z7.D, Z26.D

0x41df2c ADD	Z25.D, Z3.D, Z25.D

0x41df30 ORR	Z29.D, Z25.D, Z25.D

0x41df34 MOVPRFX	Z28, Z25

0x41df38 SXTW	Z28.D, P0/M, Z25.D

0x41df3c ORR	Z11.D, Z25.D, Z25.D

0x41df40 ADD	Z31.D, Z25.D, Z18.D

0x41df44 ADR	Z27.D, [Z16, Z27.D,LSL #3]    [9]

0x41df48 ADD	Z29.D, Z29.D, #1

0x41df4c ADR	Z8.D, [Z19, Z8.D,LSL #3]    [14]

0x41df50 ADD	Z11.D, Z11.D, #2

0x41df54 ADR	Z10.D, [Z20, Z10.D,LSL #3]    [2]

0x41df58 ADR	Z26.D, [Z23, Z26.D,LSL #3]    [7]

0x41df5c ADR	Z27.D, [Z27, Z25.D,SXTW #3]    [12]

0x41df60 MOVPRFX	Z30, Z29

0x41df64 SXTW	Z30.D, P0/M, Z29.D

0x41df68 LD1D	{Z27.D}, P0/Z, [V27.D]    [11]

0x41df6c FCMLT	P1.D, P0/Z, Z27.D, #0

0x41df70 SEL	Z9.D, P1, Z30.D, Z28.D

0x41df74 SEL	Z28.D, P1, Z28.D, Z30.D

0x41df78 SEL	Z30.D, P1, Z11.D, Z31.D

0x41df7c SEL	Z29.D, P1, Z29.D, Z31.D

0x41df80 MOVPRFX	Z31, Z27

0x41df84 FABS	Z31.D, P0/M, Z27.D

0x41df88 ADR	Z8.D, [Z8, Z9.D,LSL #3]    [5]

0x41df8c ADR	Z9.D, [Z10, Z9.D,LSL #3]    [1]

0x41df90 ADR	Z30.D, [Z10, Z30.D,SXTW #3]    [1]

0x41df94 ADR	Z28.D, [Z10, Z28.D,LSL #3]    [1]

0x41df98 LD1D	{Z8.D}, P0/Z, [V8.D]    [4]

0x41df9c FDIV	Z31.D, P0/M, Z31.D, Z8.D

0x41dfa0 LD1D	{Z9.D}, P0/Z, [V9.D]    [6]

0x41dfa4 LD1D	{Z30.D}, P0/Z, [V30.D]    [3]

0x41dfa8 LD1D	{Z28.D}, P0/Z, [V28.D]    [13]

0x41dfac FSUB	Z8.D, Z9.D, Z30.D

0x41dfb0 FSUB	Z10.D, Z28.D, Z9.D

0x41dfb4 FABD	Z30.D, P0/M, Z30.D, Z9.D

0x41dfb8 FABD	Z28.D, P0/M, Z28.D, Z9.D

0x41dfbc FMUL	Z8.D, Z8.D, Z10.D

0x41dfc0 FCMLE	P2.D, P0/Z, Z10.D, #0

0x41dfc4 EOR	P2.B, P0/Z, P2.B, P0.B

0x41dfc8 FCMGT	P1.D, P0/Z, Z8.D, #0

0x41dfcc LD1D	{Z8.D}, P1/Z, [X14, Z25.D,SXTW #3]    [15]

0x41dfd0 ADR	Z25.D, [Z26, Z25.D,SXTW #3]    [10]

0x41dfd4 FSUB	Z10.D, Z21.D, Z31.D

0x41dfd8 MOVPRFX	Z11, Z31

0x41dfdc FADD	Z11.D, P0/M, Z11.D, #1

0x41dfe0 FMUL	Z10.D, Z10.D, Z28.D

0x41dfe4 LD1D	{Z29.D}, P1/Z, [X14, Z29.D,SXTW #3]    [15]

0x41dfe8 FMUL	Z11.D, Z11.D, Z30.D

0x41dfec FDIV	Z10.D, P0/M, Z10.D, Z8.D

0x41dff0 FDIVR	Z29.D, P0/M, Z29.D, Z11.D

0x41dff4 FADD	Z29.D, Z10.D, Z29.D

0x41dff8 FMUL	Z29.D, Z8.D, Z29.D

0x41dffc FDIV	Z29.D, P0/M, Z29.D, Z22.D

0x41e000 FMINNM	Z29.D, P0/M, Z29.D, Z30.D

0x41e004 FMINNM	Z28.D, P0/M, Z28.D, Z29.D

0x41e008 MOVPRFX	Z29, Z28

0x41e00c FNEG	Z29.D, P0/M, Z28.D

0x41e010 SEL	Z28.D, P2, Z28.D, Z29.D

0x41e014 MOVPRFX	Z29, Z31

0x41e018 FSUBR	Z29.D, P0/M, Z29.D, #1

0x41e01c SEL	Z28.D, P1, Z28.D, Z17.D

0x41e020 FMAD	Z28.D, P0/M, Z29.D, Z9.D

0x41e024 FMUL	Z27.D, Z27.D, Z28.D

0x41e028 ST1D	{Z27.D}, P0, [V25.D]    [8]

0x41e02c CBNZ	X2, 41df00

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 109 - 139

--------------------------------------------------------------------------------

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.08 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.86
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source	advec_mom.cpp:109-139,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.75 - 47.97
CQA cycles if no scalar integer	16.75 - 47.97
CQA cycles if FP arith vectorized	16.75 - 47.97
CQA cycles if fully vectorized	15.50 - 47.97
Front-end cycles	9.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	16.75
P9 cycles	16.75
P10 cycles	16.75
P11 cycles	16.75
P12 cycles	2.83
P13 cycles	2.50
P14 cycles	2.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	14.86 - 47.97
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	72.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.03 - 0.71
Nb FLOP add-sub	12.00
Nb FLOP mul	10.00
Nb FLOP fma	2.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67 - 7.64
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	5.00
Vectorization ratio all	76.00
Vectorization ratio load	41.18
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.17
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	91.50
Vector-efficiency ratio load	70.59
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	76.09
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.08 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.86
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source	advec_mom.cpp:109-139,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.75 - 47.97
CQA cycles if no scalar integer	16.75 - 47.97
CQA cycles if FP arith vectorized	16.75 - 47.97
CQA cycles if fully vectorized	15.50 - 47.97
Front-end cycles	9.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	16.75
P9 cycles	16.75
P10 cycles	16.75
P11 cycles	16.75
P12 cycles	2.83
P13 cycles	2.50
P14 cycles	2.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	14.86 - 47.97
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	72.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.03 - 0.71
Nb FLOP add-sub	12.00
Nb FLOP mul	10.00
Nb FLOP fma	2.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67 - 7.64
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	5.00
Vectorization ratio all	76.00
Vectorization ratio load	41.18
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.17
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	91.50
Vector-efficiency ratio load	70.59
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	76.09
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 91% of vector register length is used (average across all VPU instructions).

Details

76% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 34 FP arithmetical operations:

14: addition or subtraction (2 inside FMA instructions)
12: multiply (2 inside FMA instructions)
8: divide

The binary loop is loading 112 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	76
loop length	304
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	1.00	1.00	16.75	16.75	16.75	16.75	2.83	2.50	2.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	1.00	1.00	16.75	16.75	16.75	16.75	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-47.97
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Data deps.	2.00
Overall L1	16.75-47.97

Vectorization ratios

INT

all	64%
load	41%
store	100%
mul	100%
add-sub	35%
fma	100%
other	65%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	76%
load	41%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.97 cycles. At this rate:

2% of peak load performance is reached (2.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41df00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z25.D, P0/M, Z25.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z26.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z25.D, P0/M, Z1.D, Z24.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z24.D, Z24.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z27.D, Z4.D, Z26.D																					vect (100.0%)
MUL Z8.D, Z5.D, Z26.D																					vect (100.0%)
MUL Z10.D, Z6.D, Z26.D																					vect (100.0%)
MUL Z26.D, Z7.D, Z26.D																					vect (100.0%)
ADD Z25.D, Z3.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z29.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z28, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z28.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z11.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z31.D, Z25.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z27.D, [Z16, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z29.D, Z29.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z8.D, [Z19, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z11.D, Z11.D, #2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z10.D, [Z20, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z30.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z9.D, P1, Z30.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z30.D, P1, Z11.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z29.D, P1, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z31, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z31.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z8.D, [Z8, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z10, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z10, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z10, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z31.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V28.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z8.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z10.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z30.D, P0/M, Z30.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z8.D, Z8.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z10.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P1.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z8.D}, P1/Z, [X14, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z25.D, [Z26, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB Z10.D, Z21.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z11, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z11.D, P0/M, Z11.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z10.D, Z10.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z29.D}, P1/Z, [X14, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z11.D, Z11.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV Z10.D, P0/M, Z10.D, Z8.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIVR Z29.D, P0/M, Z29.D, Z11.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z29.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z29.D, Z8.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV Z29.D, P0/M, Z29.D, Z22.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMINNM Z29.D, P0/M, Z29.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM Z28.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z28.D, P2, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z29, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FSUBR Z29.D, P0/M, Z29.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z28.D, P1, Z28.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAD Z28.D, P0/M, Z29.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z27.D, Z27.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z27.D}, P0, [V25.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X2, 41df00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 91% of vector register length is used (average across all VPU instructions).

Details

76% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 34 FP arithmetical operations:

14: addition or subtraction (2 inside FMA instructions)
12: multiply (2 inside FMA instructions)
8: divide

The binary loop is loading 112 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	76
loop length	304
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	1.00	1.00	16.75	16.75	16.75	16.75	2.83	2.50	2.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	1.00	1.00	16.75	16.75	16.75	16.75	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-47.97
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Data deps.	2.00
Overall L1	16.75-47.97

Vectorization ratios

INT

all	64%
load	41%
store	100%
mul	100%
add-sub	35%
fma	100%
other	65%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	76%
load	41%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 47.97 cycles. At this rate:

2% of peak load performance is reached (2.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41df00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z25.D, P0/M, Z25.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z26.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z25.D, P0/M, Z1.D, Z24.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z24.D, Z24.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z27.D, Z4.D, Z26.D																					vect (100.0%)
MUL Z8.D, Z5.D, Z26.D																					vect (100.0%)
MUL Z10.D, Z6.D, Z26.D																					vect (100.0%)
MUL Z26.D, Z7.D, Z26.D																					vect (100.0%)
ADD Z25.D, Z3.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z29.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z28, Z25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z28.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z11.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z31.D, Z25.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z27.D, [Z16, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z29.D, Z29.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z8.D, [Z19, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD Z11.D, Z11.D, #2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z10.D, [Z20, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z30.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z9.D, P1, Z30.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z30.D, P1, Z11.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z29.D, P1, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z31, Z27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z31.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z8.D, [Z8, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z10, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z10, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z10, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z31.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V28.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z8.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z10.D, Z28.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z30.D, P0/M, Z30.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z8.D, Z8.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z10.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P1.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z8.D}, P1/Z, [X14, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z25.D, [Z26, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB Z10.D, Z21.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z11, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z11.D, P0/M, Z11.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z10.D, Z10.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z29.D}, P1/Z, [X14, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL Z11.D, Z11.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV Z10.D, P0/M, Z10.D, Z8.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIVR Z29.D, P0/M, Z29.D, Z11.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FADD Z29.D, Z10.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z29.D, Z8.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIV Z29.D, P0/M, Z29.D, Z22.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMINNM Z29.D, P0/M, Z29.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM Z28.D, P0/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z28.D, P2, Z28.D, Z29.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z29, Z31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FSUBR Z29.D, P0/M, Z29.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z28.D, P1, Z28.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAD Z28.D, P0/M, Z29.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z27.D, Z27.D, Z28.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z27.D}, P0, [V25.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X2, 41df00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code