OV - exec - Loop 184

	Loop Id: 184	Module: exec	Source: advec_mom.cpp:86-88 [...]	Coverage: 1.05%

0x41d8e8 MOVPRFX	Z20, Z19

0x41d8ec SDIV	Z20.D, P0/M, Z20.D, Z1.D

0x41d8f0 DECD	X16, ALL

0x41d8f4 ADD	Z21.D, Z2.D, Z20.D

0x41d8f8 MOVPRFX	Z22, Z19

0x41d8fc MLS	Z22.D, P0/M, Z20.D, Z1.D

0x41d900 ADD	Z20.D, Z4.D, Z20.D

0x41d904 ADD	Z19.D, Z19.D, Z0.D

0x41d908 SXTW	Z20.D, P0/M, Z20.D

0x41d90c SXTW	Z21.D, P0/M, Z21.D

0x41d910 MUL	Z20.D, Z5.D, Z20.D

0x41d914 MUL	Z25.D, Z5.D, Z21.D

0x41d918 MUL	Z21.D, Z7.D, Z21.D

0x41d91c ADD	Z23.D, Z3.D, Z22.D

0x41d920 ADD	Z22.D, Z6.D, Z22.D

0x41d924 ADR	Z20.D, [Z16, Z20.D,LSL #3]    [8]

0x41d928 ADR	Z25.D, [Z16, Z25.D,LSL #3]    [8]

0x41d92c ADR	Z21.D, [Z18, Z21.D,LSL #3]    [10]

0x41d930 ADR	Z24.D, [Z20, Z23.D,SXTW #3]    [2]

0x41d934 ADR	Z26.D, [Z25, Z23.D,SXTW #3]    [7]

0x41d938 ADR	Z20.D, [Z20, Z22.D,SXTW #3]    [2]

0x41d93c ADR	Z22.D, [Z25, Z22.D,SXTW #3]    [7]

0x41d940 ADR	Z21.D, [Z21, Z23.D,SXTW #3]    [4]

0x41d944 LD1D	{Z24.D}, P0/Z, [V24.D]    [6]

0x41d948 LD1D	{Z26.D}, P0/Z, [V26.D]    [9]

0x41d94c LD1D	{Z20.D}, P0/Z, [V20.D]    [1]

0x41d950 LD1D	{Z22.D}, P0/Z, [V22.D]    [5]

0x41d954 FADD	Z24.D, Z24.D, Z26.D

0x41d958 FADD	Z20.D, Z24.D, Z20.D

0x41d95c FADD	Z20.D, Z20.D, Z22.D

0x41d960 FMUL	Z20.D, Z20.D, Z17.D

0x41d964 ST1D	{Z20.D}, P0, [V21.D]    [3]

0x41d968 CBNZ	X16, 41d8e8

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 86 - 88

--------------------------------------------------------------------------------

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.87 - 2.86
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.8]
Source	advec_mom.cpp:86-88,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	7.00 - 20.00
CQA cycles if no scalar integer	7.00 - 20.00
CQA cycles if FP arith vectorized	7.00 - 20.00
CQA cycles if fully vectorized	6.00 - 20.00
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	1.83
P13 cycles	1.50
P14 cycles	1.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.14 - 0.40
Nb FLOP add-sub	6.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00 - 11.43
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	3.00
Vectorization ratio all	65.63
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	85.94
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.87 - 2.86
Bottlenecks	P8, P10,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.8]
Source	advec_mom.cpp:86-88,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	7.00 - 20.00
CQA cycles if no scalar integer	7.00 - 20.00
CQA cycles if FP arith vectorized	7.00 - 20.00
CQA cycles if fully vectorized	6.00 - 20.00
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	1.83
P13 cycles	1.50
P14 cycles	1.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.14 - 0.40
Nb FLOP add-sub	6.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00 - 11.43
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	3.00
Vectorization ratio all	65.63
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	85.94
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.8]
Source file and lines	advec_mom.cpp:86-88
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:86-88
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: addition or subtraction
2: multiply

The binary loop is loading 64 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.00	7.00	7.00	7.00	1.83	1.50	1.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.00	7.00	7.00	7.00	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	7.00-20.00

Vectorization ratios

INT

all	60%
load	33%
store	100%
mul	100%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	65%
load	33%
store	100%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d8e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z20, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z20.D, P0/M, Z20.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X16, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z21.D, Z2.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z22, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z22.D, P0/M, Z20.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z20.D, Z5.D, Z20.D																					vect (100.0%)
MUL Z25.D, Z5.D, Z21.D																					vect (100.0%)
MUL Z21.D, Z7.D, Z21.D																					vect (100.0%)
ADD Z23.D, Z3.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z22.D, Z6.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z20.D, [Z16, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z18, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z24.D, [Z20, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z20.D, [Z20, Z22.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z22.D, [Z25, Z22.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z24.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z22.D}, P0/Z, [V22.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z20.D, Z24.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z20.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z20.D}, P0, [V21.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X16, 41d8e8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.8+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.8]
Source file and lines	advec_mom.cpp:86-88
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:86-88
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: addition or subtraction
2: multiply

The binary loop is loading 64 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.00	7.00	7.00	7.00	1.83	1.50	1.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	7.00	7.00	7.00	7.00	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.75
Data deps.	2.00
Overall L1	7.00-20.00

Vectorization ratios

INT

all	60%
load	33%
store	100%
mul	100%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	65%
load	33%
store	100%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d8e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z20, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z20.D, P0/M, Z20.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X16, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z21.D, Z2.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z22, Z19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z22.D, P0/M, Z20.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z20.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z19.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z20.D, Z5.D, Z20.D																					vect (100.0%)
MUL Z25.D, Z5.D, Z21.D																					vect (100.0%)
MUL Z21.D, Z7.D, Z21.D																					vect (100.0%)
ADD Z23.D, Z3.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z22.D, Z6.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z20.D, [Z16, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z18, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z24.D, [Z20, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z25, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z20.D, [Z20, Z22.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z22.D, [Z25, Z22.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z23.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z24.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z22.D}, P0/Z, [V22.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z20.D, Z24.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z20.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z20.D}, P0, [V21.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X16, 41d8e8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.8+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code