OV - exec - Loop 174

	Loop Id: 174	Module: exec	Source: advec_cell.cpp:209-216 [...]	Coverage: 3.86%

0x41c7a4 MOVPRFX	Z25, Z24

0x41c7a8 SDIV	Z25.D, P0/M, Z25.D, Z1.D

0x41c7ac DECD	X5, ALL

0x41c7b0 ADD	Z26.D, Z2.D, Z25.D

0x41c7b4 MSB	Z25.D, P0/M, Z1.D, Z24.D

0x41c7b8 ADD	Z24.D, Z24.D, Z0.D

0x41c7bc MOVPRFX	Z27, Z26

0x41c7c0 SXTW	Z27.D, P0/M, Z26.D

0x41c7c4 ADD	Z26.D, Z26.D, #1

0x41c7c8 MUL	Z28.D, Z4.D, Z27.D

0x41c7cc MUL	Z30.D, Z5.D, Z27.D

0x41c7d0 SXTW	Z26.D, P0/M, Z26.D

0x41c7d4 MUL	Z9.D, Z7.D, Z27.D

0x41c7d8 MUL	Z10.D, Z16.D, Z27.D

0x41c7dc MUL	Z31.D, Z6.D, Z27.D

0x41c7e0 MUL	Z27.D, Z17.D, Z27.D

0x41c7e4 ADD	Z25.D, Z3.D, Z25.D

0x41c7e8 MUL	Z8.D, Z6.D, Z26.D

0x41c7ec MUL	Z11.D, Z16.D, Z26.D

0x41c7f0 MUL	Z26.D, Z17.D, Z26.D

0x41c7f4 ADR	Z28.D, [Z18, Z28.D,LSL #3]    [21]

0x41c7f8 ADR	Z30.D, [Z19, Z30.D,LSL #3]    [24]

0x41c7fc ADR	Z9.D, [Z21, Z9.D,LSL #3]    [8]

0x41c800 ADR	Z10.D, [Z22, Z10.D,LSL #3]    [13]

0x41c804 ADR	Z31.D, [Z20, Z31.D,LSL #3]    [3]

0x41c808 ADR	Z27.D, [Z23, Z27.D,LSL #3]    [16]

0x41c80c ADR	Z28.D, [Z28, Z25.D,SXTW #3]    [23]

0x41c810 ADR	Z30.D, [Z30, Z25.D,SXTW #3]    [5]

0x41c814 ADR	Z8.D, [Z20, Z8.D,LSL #3]    [3]

0x41c818 ADR	Z9.D, [Z9, Z25.D,SXTW #3]    [15]

0x41c81c ADR	Z10.D, [Z10, Z25.D,SXTW #3]    [2]

0x41c820 ADR	Z11.D, [Z22, Z11.D,LSL #3]    [13]

0x41c824 ADR	Z26.D, [Z23, Z26.D,LSL #3]    [16]

0x41c828 ADR	Z31.D, [Z31, Z25.D,SXTW #3]    [10]

0x41c82c ADR	Z27.D, [Z27, Z25.D,SXTW #3]    [20]

0x41c830 LD1D	{Z29.D}, P0/Z, [V28.D]    [22]

0x41c834 ADR	Z8.D, [Z8, Z25.D,SXTW #3]    [12]

0x41c838 LD1D	{Z30.D}, P0/Z, [V30.D]    [4]

0x41c83c ADR	Z11.D, [Z11, Z25.D,SXTW #3]    [7]

0x41c840 ADR	Z25.D, [Z26, Z25.D,SXTW #3]    [18]

0x41c844 LD1D	{Z26.D}, P0/Z, [V9.D]    [14]

0x41c848 FMUL	Z29.D, Z29.D, Z30.D

0x41c84c LD1D	{Z10.D}, P0/Z, [V10.D]    [1]

0x41c850 LD1D	{Z31.D}, P0/Z, [V31.D]    [9]

0x41c854 LD1D	{Z27.D}, P0/Z, [V27.D]    [19]

0x41c858 FADD	Z27.D, Z30.D, Z27.D

0x41c85c LD1D	{Z8.D}, P0/Z, [V8.D]    [11]

0x41c860 LD1D	{Z11.D}, P0/Z, [V11.D]    [6]

0x41c864 LD1D	{Z25.D}, P0/Z, [V25.D]    [17]

0x41c868 FSUB	Z25.D, Z27.D, Z25.D

0x41c86c FMAD	Z26.D, P0/M, Z29.D, Z10.D

0x41c870 FADD	Z31.D, Z29.D, Z31.D

0x41c874 FSUB	Z31.D, Z31.D, Z8.D

0x41c878 FSUB	Z26.D, Z26.D, Z11.D

0x41c87c FDIVR	Z25.D, P0/M, Z25.D, Z31.D

0x41c880 FDIV	Z26.D, P0/M, Z26.D, Z31.D

0x41c884 ST1D	{Z25.D}, P0, [V28.D]    [22]

0x41c888 ST1D	{Z26.D}, P0, [V9.D]    [14]

0x41c88c CBNZ	X5, 41c7a4

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 209 - 216

--------------------------------------------------------------------------------

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.23 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.83
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.14]
Source	advec_cell.cpp:209-216,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.00 - 33.99
CQA cycles if no scalar integer	12.00 - 33.99
CQA cycles if FP arith vectorized	12.00 - 33.99
CQA cycles if fully vectorized	9.75 - 33.99
Front-end cycles	6.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	3.67
P13 cycles	3.67
P14 cycles	3.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	7.87 - 33.99
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	50.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.67 - 0.59
Nb FLOP add-sub	10.00
Nb FLOP mul	2.00
Nb FLOP fma	2.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.18 - 14.67
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	15.00
Stride indirect	9.00
Vectorization ratio all	63.79
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	32.14
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	83.62
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	66.07
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.23 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.83
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.14]
Source	advec_cell.cpp:209-216,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.00 - 33.99
CQA cycles if no scalar integer	12.00 - 33.99
CQA cycles if FP arith vectorized	12.00 - 33.99
CQA cycles if fully vectorized	9.75 - 33.99
Front-end cycles	6.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	3.67
P13 cycles	3.67
P14 cycles	3.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	7.87 - 33.99
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	50.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.67 - 0.59
Nb FLOP add-sub	10.00
Nb FLOP mul	2.00
Nb FLOP fma	2.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.18 - 14.67
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	15.00
Stride indirect	9.00
Vectorization ratio all	63.79
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	32.14
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	83.62
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	66.07
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.14]
Source file and lines	advec_cell.cpp:209-216
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209-216
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 83% of vector register length is used (average across all VPU instructions).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
32% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

12: addition or subtraction (2 inside FMA instructions)
4: multiply (2 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	12.00	12.00	12.00	12.00	3.67	3.67	3.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	12.00	12.00	12.00	12.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	7.87-33.99
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.25
Data deps.	2.00
Overall L1	12.00-33.99

Vectorization ratios

INT

all	57%
load	33%
store	100%
mul	100%
add-sub	17%
fma	100%
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	63%
load	33%
store	100%
mul	100%
add-sub	32%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 33.99 cycles. At this rate:

4% of peak load performance is reached (4.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c7a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z25.D, P0/M, Z25.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X5, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z26.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z25.D, P0/M, Z1.D, Z24.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z24.D, Z24.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z27, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z27.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z26.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z28.D, Z4.D, Z27.D																					vect (100.0%)
MUL Z30.D, Z5.D, Z27.D																					vect (100.0%)
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z9.D, Z7.D, Z27.D																					vect (100.0%)
MUL Z10.D, Z16.D, Z27.D																					vect (100.0%)
MUL Z31.D, Z6.D, Z27.D																					vect (100.0%)
MUL Z27.D, Z17.D, Z27.D																					vect (100.0%)
ADD Z25.D, Z3.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z8.D, Z6.D, Z26.D																					vect (100.0%)
MUL Z11.D, Z16.D, Z26.D																					vect (100.0%)
MUL Z26.D, Z17.D, Z26.D																					vect (100.0%)
ADR Z28.D, [Z18, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z19, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z21, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z22, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z31.D, [Z20, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z28, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z8.D, [Z20, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z11.D, [Z22, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z31.D, [Z31, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z29.D}, P0/Z, [V28.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z8.D, [Z8, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z11.D, [Z11, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z26, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z26.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z29.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z31.D}, P0/Z, [V31.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z27.D, Z30.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z25.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAD Z26.D, P0/M, Z29.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FADD Z31.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z31.D, Z31.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z26.D, Z26.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z25.D, P0/M, Z25.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z26.D, P0/M, Z26.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ST1D {Z25.D}, P0, [V28.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ST1D {Z26.D}, P0, [V9.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X5, 41c7a4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.14]
Source file and lines	advec_cell.cpp:209-216
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209-216
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 83% of vector register length is used (average across all VPU instructions).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
32% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

12: addition or subtraction (2 inside FMA instructions)
4: multiply (2 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	12.00	12.00	12.00	12.00	3.67	3.67	3.67	0.00	0.00
cycles	0.50	0.50	0.00	0.00	0.00	0.00	0.50	0.50	12.00	12.00	12.00	12.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	7.87-33.99
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.25
Data deps.	2.00
Overall L1	12.00-33.99

Vectorization ratios

INT

all	57%
load	33%
store	100%
mul	100%
add-sub	17%
fma	100%
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	63%
load	33%
store	100%
mul	100%
add-sub	32%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 33.99 cycles. At this rate:

4% of peak load performance is reached (4.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c7a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z25.D, P0/M, Z25.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DECD X5, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD Z26.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MSB Z25.D, P0/M, Z1.D, Z24.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
ADD Z24.D, Z24.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z27, Z26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z27.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z26.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z28.D, Z4.D, Z27.D																					vect (100.0%)
MUL Z30.D, Z5.D, Z27.D																					vect (100.0%)
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z9.D, Z7.D, Z27.D																					vect (100.0%)
MUL Z10.D, Z16.D, Z27.D																					vect (100.0%)
MUL Z31.D, Z6.D, Z27.D																					vect (100.0%)
MUL Z27.D, Z17.D, Z27.D																					vect (100.0%)
ADD Z25.D, Z3.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z8.D, Z6.D, Z26.D																					vect (100.0%)
MUL Z11.D, Z16.D, Z26.D																					vect (100.0%)
MUL Z26.D, Z17.D, Z26.D																					vect (100.0%)
ADR Z28.D, [Z18, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z19, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z21, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z22, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z31.D, [Z20, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z28.D, [Z28, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z30.D, [Z30, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z8.D, [Z20, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z11.D, [Z22, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z26.D, [Z23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z31.D, [Z31, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z27.D, [Z27, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z29.D}, P0/Z, [V28.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z8.D, [Z8, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z30.D}, P0/Z, [V30.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z11.D, [Z11, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z25.D, [Z26, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z26.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z29.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z31.D}, P0/Z, [V31.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FADD Z27.D, Z30.D, Z27.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z25.D}, P0/Z, [V25.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z25.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAD Z26.D, P0/M, Z29.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FADD Z31.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z31.D, Z31.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z26.D, Z26.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z25.D, P0/M, Z25.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FDIV Z26.D, P0/M, Z26.D, Z31.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ST1D {Z25.D}, P0, [V28.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
ST1D {Z26.D}, P0, [V9.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CBNZ X5, 41c7a4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code