OV - exec - Loop 171

	Loop Id: 171	Module: exec	Source: advec_cell.cpp:158-202 [...]	Coverage: 3.75%

0x41c240 MOVPRFX	Z9, Z29

0x41c244 SDIV	Z9.D, P0/M, Z9.D, Z1.D

0x41c248 SUB	X19, X29, #64

0x41c24c DECD	X7, ALL

0x41c250 LDR	Z0, [X19, #510, MUL VL]    [11]

0x41c254 ADD	Z10.D, Z0.D, Z9.D

0x41c258 LDR	Z0, [X19, #509, MUL VL]    [11]

0x41c25c MOVPRFX	Z30, Z29

0x41c260 MLS	Z30.D, P0/M, Z9.D, Z1.D

0x41c264 MOVPRFX	Z31, Z10

0x41c268 SXTW	Z31.D, P0/M, Z10.D

0x41c26c LD1D	{Z13.D}, P0/Z, [X13, Z10.D,SXTW #3]    [25]

0x41c270 MUL	Z8.D, Z4.D, Z31.D

0x41c274 ADD	Z30.D, Z0.D, Z30.D

0x41c278 DUPM	Z0.D, #4294967294

0x41c27c ADD	Z12.D, Z10.D, Z0.D

0x41c280 ADD	Z10.D, Z10.D, #1

0x41c284 ADR	Z8.D, [Z19, Z8.D,LSL #3]    [26]

0x41c288 SXTW	Z10.D, P0/M, Z10.D

0x41c28c ADR	Z8.D, [Z8, Z30.D,SXTW #3]    [9]

0x41c290 MOVPRFX	Z14, Z20

0x41c294 SMIN	Z14.D, P0/M, Z14.D, Z10.D

0x41c298 ADD	Z10.D, Z5.D, Z9.D

0x41c29c LD1D	{Z8.D}, P0/Z, [V8.D]    [8]

0x41c2a0 MOVPRFX	Z11, Z10

0x41c2a4 SXTW	Z11.D, P0/M, Z10.D

0x41c2a8 FCMGT	P1.D, P0/Z, Z8.D, #0

0x41c2ac SEL	Z15.D, P1, Z11.D, Z31.D

0x41c2b0 SEL	Z10.D, P1, Z10.D, Z14.D

0x41c2b4 SEL	Z12.D, P1, Z12.D, Z14.D

0x41c2b8 SEL	Z11.D, P1, Z31.D, Z11.D

0x41c2bc MOVPRFX	Z14, Z8

0x41c2c0 FABS	Z14.D, P0/M, Z8.D

0x41c2c4 MUL	Z9.D, Z6.D, Z15.D

0x41c2c8 LD1D	{Z23.D}, P0/Z, [X13, Z10.D,SXTW #3]    [25]

0x41c2cc SXTW	Z12.D, P0/M, Z12.D

0x41c2d0 MUL	Z10.D, Z7.D, Z15.D

0x41c2d4 ADR	Z9.D, [Z22, Z9.D,LSL #3]    [10]

0x41c2d8 ADR	Z10.D, [Z24, Z10.D,LSL #3]    [18]

0x41c2dc ADR	Z9.D, [Z9, Z30.D,SXTW #3]    [13]

0x41c2e0 ADR	Z10.D, [Z10, Z30.D,SXTW #3]    [3]

0x41c2e4 LD1D	{Z21.D}, P0/Z, [V9.D]    [12]

0x41c2e8 LD1D	{Z0.D}, P0/Z, [V10.D]    [2]

0x41c2ec FDIVR	Z23.D, P0/M, Z23.D, Z13.D

0x41c2f0 MUL	Z13.D, Z7.D, Z12.D

0x41c2f4 ADR	Z13.D, [Z24, Z13.D,LSL #3]    [18]

0x41c2f8 ADR	Z13.D, [Z13, Z30.D,SXTW #3]    [15]

0x41c2fc FDIVR	Z21.D, P0/M, Z21.D, Z14.D

0x41c300 MUL	Z14.D, Z7.D, Z11.D

0x41c304 LD1D	{Z13.D}, P0/Z, [V13.D]    [14]

0x41c308 ADR	Z14.D, [Z24, Z14.D,LSL #3]    [18]

0x41c30c ADR	Z14.D, [Z14, Z30.D,SXTW #3]    [17]

0x41c310 LD1D	{Z14.D}, P0/Z, [V14.D]    [16]

0x41c314 FSUB	Z2.D, Z0.D, Z13.D

0x41c318 FSUB	Z3.D, Z14.D, Z0.D

0x41c31c FMUL	Z2.D, Z2.D, Z3.D

0x41c320 FCMLE	P2.D, P0/Z, Z3.D, #0

0x41c324 FDUP	Z3.D, #0

0x41c328 FSUB	Z3.D, Z3.D, Z21.D

0x41c32c EOR	P2.B, P0/Z, P2.B, P0.B

0x41c330 FCMGT	P1.D, P0/Z, Z2.D, #0

0x41c334 MOVPRFX	Z2, Z21

0x41c338 FADD	Z2.D, P0/M, Z2.D, #1

0x41c33c FSUBR	Z21.D, P0/M, Z21.D, #1

0x41c340 FMUL	Z2.D, Z2.D, Z23.D

0x41c344 MOVPRFX	Z23, Z21

0x41c348 FNEG	Z23.D, P0/M, Z21.D

0x41c34c EOR	P1.B, P0/Z, P1.B, P0.B

0x41c350 SEL	Z21.D, P2, Z21.D, Z23.D

0x41c354 MOVPRFX	Z23, Z0

0x41c358 FABD	Z23.D, P0/M, Z23.D, Z13.D

0x41c35c MOVPRFX	Z13, Z14

0x41c360 FABD	Z13.D, P0/M, Z13.D, Z0.D

0x41c364 MOVPRFX	Z14, Z23

0x41c368 FMINNM	Z14.D, P0/M, Z14.D, Z13.D

0x41c36c FMUL	Z13.D, Z3.D, Z13.D

0x41c370 FMAD	Z23.D, P0/M, Z2.D, Z13.D

0x41c374 FMUL	Z23.D, Z23.D, Z25.D

0x41c378 FMINNM	Z23.D, P0/M, Z23.D, Z14.D

0x41c37c FMUL	Z21.D, Z21.D, Z23.D

0x41c380 MUL	Z23.D, Z17.D, Z12.D

0x41c384 CPY	Z21.D, P1/M, #0

0x41c388 FADD	Z0.D, Z0.D, Z21.D

0x41c38c MUL	Z21.D, Z16.D, Z31.D

0x41c390 ADR	Z23.D, [Z27, Z23.D,LSL #3]    [21]

0x41c394 FMUL	Z0.D, Z8.D, Z0.D

0x41c398 MUL	Z8.D, Z17.D, Z11.D

0x41c39c ADR	Z23.D, [Z23, Z30.D,SXTW #3]    [28]

0x41c3a0 ADR	Z21.D, [Z26, Z21.D,LSL #3]    [20]

0x41c3a4 ADR	Z21.D, [Z21, Z30.D,SXTW #3]    [5]

0x41c3a8 ADR	Z8.D, [Z27, Z8.D,LSL #3]    [21]

0x41c3ac ST1D	{Z0.D}, P0, [V21.D]    [4]

0x41c3b0 MUL	Z21.D, Z17.D, Z15.D

0x41c3b4 ADR	Z8.D, [Z8, Z30.D,SXTW #3]    [7]

0x41c3b8 LD1D	{Z10.D}, P0/Z, [V10.D]    [2]

0x41c3bc LD1D	{Z9.D}, P0/Z, [V9.D]    [12]

0x41c3c0 LD1D	{Z23.D}, P0/Z, [V23.D]    [27]

0x41c3c4 LD1D	{Z8.D}, P0/Z, [V8.D]    [6]

0x41c3c8 ADR	Z21.D, [Z27, Z21.D,LSL #3]    [21]

0x41c3cc ADR	Z21.D, [Z21, Z30.D,SXTW #3]    [24]

0x41c3d0 LD1D	{Z21.D}, P0/Z, [V21.D]    [23]

0x41c3d4 FMUL	Z9.D, Z10.D, Z9.D

0x41c3d8 MOVPRFX	Z10, Z0

0x41c3dc FABS	Z10.D, P0/M, Z0.D

0x41c3e0 FDIVR	Z9.D, P0/M, Z9.D, Z10.D

0x41c3e4 FSUB	Z12.D, Z8.D, Z21.D

0x41c3e8 FABD	Z8.D, P0/M, Z8.D, Z21.D

0x41c3ec FSUB	Z11.D, Z21.D, Z23.D

0x41c3f0 FABD	Z23.D, P0/M, Z23.D, Z21.D

0x41c3f4 FMUL	Z3.D, Z3.D, Z8.D

0x41c3f8 FCMLE	P2.D, P0/Z, Z12.D, #0

0x41c3fc FMUL	Z11.D, Z11.D, Z12.D

0x41c400 EOR	P2.B, P0/Z, P2.B, P0.B

0x41c404 FMAD	Z2.D, P0/M, Z23.D, Z3.D

0x41c408 MOVPRFX	Z3, Z23

0x41c40c FMINNM	Z3.D, P0/M, Z3.D, Z8.D

0x41c410 FCMGT	P1.D, P0/Z, Z11.D, #0

0x41c414 EOR	P1.B, P0/Z, P1.B, P0.B

0x41c418 FMUL	Z2.D, Z2.D, Z25.D

0x41c41c FSUBR	Z9.D, P0/M, Z9.D, #1

0x41c420 MOVPRFX	Z10, Z9

0x41c424 FNEG	Z10.D, P0/M, Z9.D

0x41c428 FMINNM	Z2.D, P0/M, Z2.D, Z3.D

0x41c42c SEL	Z9.D, P2, Z9.D, Z10.D

0x41c430 FMUL	Z2.D, Z2.D, Z9.D

0x41c434 CPY	Z2.D, P1/M, #0

0x41c438 FADD	Z2.D, Z21.D, Z2.D

0x41c43c FMUL	Z0.D, Z0.D, Z2.D

0x41c440 MUL	Z2.D, Z18.D, Z31.D

0x41c444 ADR	Z2.D, [Z28, Z2.D,LSL #3]    [22]

0x41c448 ADR	Z2.D, [Z2, Z30.D,SXTW #3]    [19]

0x41c44c ST1D	{Z0.D}, P0, [V2.D]    [1]

0x41c450 LDR	Z0, [X19, #511, MUL VL]    [11]

0x41c454 ADD	Z29.D, Z29.D, Z0.D

0x41c458 CBNZ	X7, 41c240

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 158 - 202

--------------------------------------------------------------------------------

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.81 - 1.45
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source	advec_cell.cpp:158-202,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.25 - 40.98
CQA cycles if no scalar integer	28.25 - 40.98
CQA cycles if FP arith vectorized	28.25 - 40.98
CQA cycles if fully vectorized	25.05 - 40.98
Front-end cycles	15.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	4.00
P7 cycles	1.00
P8 cycles	28.25
P9 cycles	28.25
P10 cycles	28.25
P11 cycles	28.25
P12 cycles	5.67
P13 cycles	5.67
P14 cycles	5.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	11.36 - 40.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	135.00
Nb uops	125.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.05 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.64 - 9.63
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	17.00
Stride indirect	11.00
Vectorization ratio all	71.43
Vectorization ratio load	42.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	44.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.00
Vector-efficiency ratio all	87.36
Vector-efficiency ratio load	71.43
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.37
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.81 - 1.45
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source	advec_cell.cpp:158-202,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.25 - 40.98
CQA cycles if no scalar integer	28.25 - 40.98
CQA cycles if FP arith vectorized	28.25 - 40.98
CQA cycles if fully vectorized	25.05 - 40.98
Front-end cycles	15.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	4.00
P7 cycles	1.00
P8 cycles	28.25
P9 cycles	28.25
P10 cycles	28.25
P11 cycles	28.25
P12 cycles	5.67
P13 cycles	5.67
P14 cycles	5.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	11.36 - 40.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	135.00
Nb uops	125.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.05 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.64 - 9.63
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	17.00
Stride indirect	11.00
Vectorization ratio all	71.43
Vectorization ratio load	42.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	44.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	66.00
Vector-efficiency ratio all	87.36
Vector-efficiency ratio load	71.43
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.37
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source file and lines	advec_cell.cpp:158-202
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158-202
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
44% of VPU addition or subtraction instructions are used in vector version.
66% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
6: divide

The binary loop is loading 240 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	135
loop length	540
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	28.25	28.25	28.25	28.25	5.67	5.67	5.67	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	28.25	28.25	28.25	28.25	5.67	5.67	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	11.36-40.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.63
Data deps.	2.00
Overall L1	28.25-40.98

Vectorization ratios

INT

all	57%
load	42%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	51%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	71%
load	42%
store	100%
mul	100%
add-sub	44%
fma	100%
div/sqrt	100%
other	66%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.98 cycles. At this rate:

6% of peak load performance is reached (5.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c240

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z9.D, P0/M, Z9.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X19, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X19, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z10.D, Z0.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X19, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z30.D, P0/M, Z9.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z31, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z31.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [X13, Z10.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z8.D, Z4.D, Z31.D																					vect (100.0%)
ADD Z30.D, Z0.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUPM Z0.D, #4294967294	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z12.D, Z10.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z10.D, Z10.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z8.D, [Z19, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SXTW Z10.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z8.D, [Z8, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVPRFX Z14, Z20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SMIN Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z10.D, Z5.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z11.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P1.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z15.D, P1, Z11.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z10.D, P1, Z10.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z12.D, P1, Z12.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z11.D, P1, Z31.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z14.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z9.D, Z6.D, Z15.D																					vect (100.0%)
LD1D {Z23.D}, P0/Z, [X13, Z10.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
SXTW Z12.D, P0/M, Z12.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z10.D, Z7.D, Z15.D																					vect (100.0%)
ADR Z9.D, [Z22, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z24, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIVR Z23.D, P0/M, Z23.D, Z13.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MUL Z13.D, Z7.D, Z12.D																					vect (100.0%)
ADR Z13.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z13, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIVR Z21.D, P0/M, Z21.D, Z14.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MUL Z14.D, Z7.D, Z11.D																					vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z14.D, [Z24, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z14, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z2.D, Z0.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z3.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z3.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FDUP Z3.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FSUB Z3.D, Z3.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P1.D, P0/Z, Z2.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z2.D, P0/M, Z2.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUBR Z21.D, P0/M, Z21.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z23, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z21.D, P2, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABD Z23.D, P0/M, Z23.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z13, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABD Z13.D, P0/M, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMINNM Z14.D, P0/M, Z14.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z13.D, Z3.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAD Z23.D, P0/M, Z2.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z23.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z23.D, P0/M, Z23.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z23.D, Z17.D, Z12.D																					vect (100.0%)
CPY Z21.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z0.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z16.D, Z31.D																					vect (100.0%)
ADR Z23.D, [Z27, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z0.D, Z8.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z8.D, Z17.D, Z11.D																					vect (100.0%)
ADR Z23.D, [Z23, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z26, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z8.D, [Z27, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V21.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z21.D, Z17.D, Z15.D																					vect (100.0%)
ADR Z8.D, [Z8, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z23.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z21.D, [Z27, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z9.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z10.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB Z12.D, Z8.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z8.D, P0/M, Z8.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z11.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z23.D, P0/M, Z23.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z3.D, Z3.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z12.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z11.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMAD Z2.D, P0/M, Z23.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MOVPRFX Z3, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMINNM Z3.D, P0/M, Z3.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGT P1.D, P0/Z, Z11.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z2.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUBR Z9.D, P0/M, Z9.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z10.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM Z2.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z9.D, P2, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
CPY Z2.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z2.D, Z21.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z2.D, Z18.D, Z31.D																					vect (100.0%)
ADR Z2.D, [Z28, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X19, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z29.D, Z29.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X7, 41c240 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source file and lines	advec_cell.cpp:158-202
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158-202
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
44% of VPU addition or subtraction instructions are used in vector version.
66% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
6: divide

The binary loop is loading 240 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	135
loop length	540
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	28.25	28.25	28.25	28.25	5.67	5.67	5.67	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	28.25	28.25	28.25	28.25	5.67	5.67	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	11.36-40.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.63
Data deps.	2.00
Overall L1	28.25-40.98

Vectorization ratios

INT

all	57%
load	42%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	51%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	71%
load	42%
store	100%
mul	100%
add-sub	44%
fma	100%
div/sqrt	100%
other	66%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.98 cycles. At this rate:

6% of peak load performance is reached (5.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c240

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z9.D, P0/M, Z9.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X19, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X19, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z10.D, Z0.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X19, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z30.D, P0/M, Z9.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
MOVPRFX Z31, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z31.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [X13, Z10.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MUL Z8.D, Z4.D, Z31.D																					vect (100.0%)
ADD Z30.D, Z0.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUPM Z0.D, #4294967294	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z12.D, Z10.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z10.D, Z10.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z8.D, [Z19, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SXTW Z10.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z8.D, [Z8, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVPRFX Z14, Z20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SMIN Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z10.D, Z5.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z11.D, P0/M, Z10.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P1.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z15.D, P1, Z11.D, Z31.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z10.D, P1, Z10.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z12.D, P1, Z12.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z11.D, P1, Z31.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z14.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z9.D, Z6.D, Z15.D																					vect (100.0%)
LD1D {Z23.D}, P0/Z, [X13, Z10.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
SXTW Z12.D, P0/M, Z12.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z10.D, Z7.D, Z15.D																					vect (100.0%)
ADR Z9.D, [Z22, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z24, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z10.D, [Z10, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIVR Z23.D, P0/M, Z23.D, Z13.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MUL Z13.D, Z7.D, Z12.D																					vect (100.0%)
ADR Z13.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z13.D, [Z13, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIVR Z21.D, P0/M, Z21.D, Z14.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
MUL Z14.D, Z7.D, Z11.D																					vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z14.D, [Z24, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z14.D, [Z14, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z2.D, Z0.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z3.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z3.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FDUP Z3.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FSUB Z3.D, Z3.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P1.D, P0/Z, Z2.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z2.D, P0/M, Z2.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUBR Z21.D, P0/M, Z21.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z23, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z21.D, P2, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABD Z23.D, P0/M, Z23.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z13, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABD Z13.D, P0/M, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMINNM Z14.D, P0/M, Z14.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z13.D, Z3.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMAD Z23.D, P0/M, Z2.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z23.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z23.D, P0/M, Z23.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z23.D, Z17.D, Z12.D																					vect (100.0%)
CPY Z21.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z0.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z21.D, Z16.D, Z31.D																					vect (100.0%)
ADR Z23.D, [Z27, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z0.D, Z8.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z8.D, Z17.D, Z11.D																					vect (100.0%)
ADR Z23.D, [Z23, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z26, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z8.D, [Z27, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V21.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z21.D, Z17.D, Z15.D																					vect (100.0%)
ADR Z8.D, [Z8, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z10.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z23.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z8.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z21.D, [Z27, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z21.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z21.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FMUL Z9.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z10.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FDIVR Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB Z12.D, Z8.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z8.D, P0/M, Z8.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z11.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z23.D, P0/M, Z23.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z3.D, Z3.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z12.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z11.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMAD Z2.D, P0/M, Z23.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
MOVPRFX Z3, Z23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMINNM Z3.D, P0/M, Z3.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGT P1.D, P0/Z, Z11.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z2.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUBR Z9.D, P0/M, Z9.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z10.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMINNM Z2.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z9.D, P2, Z9.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z2.D, Z2.D, Z9.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
CPY Z2.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z2.D, Z21.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z2.D, Z18.D, Z31.D																					vect (100.0%)
ADR Z2.D, [Z28, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z2, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X19, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z29.D, Z29.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X7, 41c240 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code