OV - exec - Loop 161

	Loop Id: 161	Module: exec	Source: advec_cell.cpp:66-110 [...]	Coverage: 3.37%

0x41b3ac MOVPRFX	Z30, Z29

0x41b3b0 SDIV	Z30.D, P0/M, Z30.D, Z1.D

0x41b3b4 SUB	X19, X29, #64

0x41b3b8 DECD	X7, ALL

0x41b3bc LDR	Z0, [X19, #510, MUL VL]    [24]

0x41b3c0 ADD	Z31.D, Z0.D, Z30.D

0x41b3c4 LDR	Z0, [X19, #509, MUL VL]    [24]

0x41b3c8 MOVPRFX	Z8, Z29

0x41b3cc MLS	Z8.D, P0/M, Z30.D, Z1.D

0x41b3d0 SXTW	Z31.D, P0/M, Z31.D

0x41b3d4 ADD	Z30.D, Z0.D, Z8.D

0x41b3d8 LDR	Z0, [X19, #508, MUL VL]    [24]

0x41b3dc ADD	Z8.D, Z5.D, Z8.D

0x41b3e0 ORR	Z11.D, Z30.D, Z30.D

0x41b3e4 MOVPRFX	Z14, Z8

0x41b3e8 SXTW	Z14.D, P0/M, Z8.D

0x41b3ec MOVPRFX	Z10, Z30

0x41b3f0 SXTW	Z10.D, P0/M, Z30.D

0x41b3f4 ADD	Z11.D, Z11.D, #1

0x41b3f8 SXTW	Z11.D, P0/M, Z11.D

0x41b3fc MUL	Z9.D, Z0.D, Z31.D

0x41b400 DUPM	Z0.D, #4294967294

0x41b404 LD1D	{Z12.D}, P0/Z, [X13, Z30.D,SXTW #3]    [18]

0x41b408 SMIN	Z11.D, P0/M, Z11.D, Z20.D

0x41b40c ADR	Z9.D, [Z19, Z9.D,LSL #3]    [19]

0x41b410 ADR	Z9.D, [Z9, Z30.D,SXTW #3]    [8]

0x41b414 LD1D	{Z13.D}, P0/Z, [V9.D]    [7]

0x41b418 ADD	Z9.D, Z30.D, Z0.D

0x41b41c MOVPRFX	Z8, Z9

0x41b420 SXTW	Z8.D, P0/M, Z9.D

0x41b424 FCMGT	P1.D, P0/Z, Z13.D, #0

0x41b428 SEL	Z15.D, P1, Z8.D, Z11.D

0x41b42c MUL	Z8.D, Z6.D, Z31.D

0x41b430 SEL	Z21.D, P1, Z14.D, Z10.D

0x41b434 SEL	Z11.D, P1, Z14.D, Z11.D

0x41b438 SEL	Z9.D, P1, Z10.D, Z14.D

0x41b43c MOVPRFX	Z14, Z13

0x41b440 FABS	Z14.D, P0/M, Z13.D

0x41b444 LD1D	{Z23.D}, P0/Z, [X13, Z11.D,LSL #3]    [18]

0x41b448 ADR	Z8.D, [Z22, Z8.D,LSL #3]    [6]

0x41b44c MUL	Z11.D, Z7.D, Z31.D

0x41b450 ADR	Z8.D, [Z8, Z21.D,LSL #3]    [4]

0x41b454 ADR	Z0.D, [Z24, Z11.D,LSL #3]    [11]

0x41b458 LD1D	{Z10.D}, P0/Z, [V8.D]    [3]

0x41b45c ADR	Z11.D, [Z0, Z21.D,LSL #3]    [10]

0x41b460 LD1D	{Z2.D}, P0/Z, [V11.D]    [2]

0x41b464 FDIVR	Z23.D, P0/M, Z23.D, Z12.D

0x41b468 ADR	Z12.D, [Z0, Z15.D,LSL #3]    [10]

0x41b46c ADR	Z0.D, [Z0, Z9.D,LSL #3]    [10]

0x41b470 LD1D	{Z3.D}, P0/Z, [V12.D]    [5]

0x41b474 LD1D	{Z0.D}, P0/Z, [V0.D]    [9]

0x41b478 FDIV	Z14.D, P0/M, Z14.D, Z10.D

0x41b47c FSUB	Z4.D, Z0.D, Z2.D

0x41b480 FABD	Z0.D, P0/M, Z0.D, Z2.D

0x41b484 FCMLE	P2.D, P0/Z, Z4.D, #0

0x41b488 EOR	P2.B, P0/Z, P2.B, P0.B

0x41b48c MOVPRFX	Z10, Z14

0x41b490 FADD	Z10.D, P0/M, Z10.D, #1

0x41b494 FMUL	Z10.D, Z10.D, Z23.D

0x41b498 FSUB	Z23.D, Z2.D, Z3.D

0x41b49c FABD	Z3.D, P0/M, Z3.D, Z2.D

0x41b4a0 FMUL	Z23.D, Z23.D, Z4.D

0x41b4a4 MOVPRFX	Z4, Z14

0x41b4a8 FSUBR	Z4.D, P0/M, Z4.D, #1

0x41b4ac FCMGT	P1.D, P0/Z, Z23.D, #0

0x41b4b0 FDUP	Z23.D, #0

0x41b4b4 FSUB	Z12.D, Z23.D, Z14.D

0x41b4b8 MOVPRFX	Z23, Z4

0x41b4bc FNEG	Z23.D, P0/M, Z4.D

0x41b4c0 EOR	P1.B, P0/Z, P1.B, P0.B

0x41b4c4 SEL	Z4.D, P2, Z4.D, Z23.D

0x41b4c8 MOVPRFX	Z23, Z3

0x41b4cc FMINNM	Z23.D, P0/M, Z23.D, Z0.D

0x41b4d0 FMUL	Z0.D, Z12.D, Z0.D

0x41b4d4 FMLA	Z0.D, P0/M, Z10.D, Z3.D

0x41b4d8 FMUL	Z0.D, Z0.D, Z25.D

0x41b4dc FMINNM	Z0.D, P0/M, Z0.D, Z23.D

0x41b4e0 FMUL	Z0.D, Z4.D, Z0.D

0x41b4e4 MUL	Z4.D, Z18.D, Z31.D

0x41b4e8 CPY	Z0.D, P1/M, #0

0x41b4ec FADD	Z0.D, Z2.D, Z0.D

0x41b4f0 ADR	Z4.D, [Z28, Z4.D,LSL #3]    [17]

0x41b4f4 FMUL	Z13.D, Z13.D, Z0.D

0x41b4f8 MUL	Z0.D, Z16.D, Z31.D

0x41b4fc ADR	Z4.D, [Z4, Z30.D,SXTW #3]    [14]

0x41b500 ADR	Z0.D, [Z26, Z0.D,LSL #3]    [15]

0x41b504 ADR	Z0.D, [Z0, Z30.D,SXTW #3]    [1]

0x41b508 ST1D	{Z13.D}, P0, [V0.D]    [22]

0x41b50c MUL	Z0.D, Z17.D, Z31.D

0x41b510 LD1D	{Z30.D}, P0/Z, [V11.D]    [2]

0x41b514 ADR	Z0.D, [Z27, Z0.D,LSL #3]    [16]

0x41b518 ADR	Z2.D, [Z0, Z21.D,LSL #3]    [21]

0x41b51c ADR	Z3.D, [Z0, Z15.D,LSL #3]    [21]

0x41b520 ADR	Z0.D, [Z0, Z9.D,LSL #3]    [21]

0x41b524 LD1D	{Z2.D}, P0/Z, [V2.D]    [23]

0x41b528 LD1D	{Z3.D}, P0/Z, [V3.D]    [12]

0x41b52c LD1D	{Z0.D}, P0/Z, [V0.D]    [20]

0x41b530 FSUB	Z21.D, Z2.D, Z3.D

0x41b534 FSUB	Z23.D, Z0.D, Z2.D

0x41b538 FABD	Z0.D, P0/M, Z0.D, Z2.D

0x41b53c FABD	Z3.D, P0/M, Z3.D, Z2.D

0x41b540 FMUL	Z21.D, Z21.D, Z23.D

0x41b544 FCMLE	P2.D, P0/Z, Z23.D, #0

0x41b548 MOVPRFX	Z23, Z13

0x41b54c FABS	Z23.D, P0/M, Z13.D

0x41b550 EOR	P2.B, P0/Z, P2.B, P0.B

0x41b554 FCMGT	P1.D, P0/Z, Z21.D, #0

0x41b558 LD1D	{Z21.D}, P0/Z, [V8.D]    [3]

0x41b55c EOR	P1.B, P0/Z, P1.B, P0.B

0x41b560 FMUL	Z21.D, Z30.D, Z21.D

0x41b564 FDIVR	Z21.D, P0/M, Z21.D, Z23.D

0x41b568 FSUBR	Z21.D, P0/M, Z21.D, #1

0x41b56c MOVPRFX	Z23, Z21

0x41b570 FNEG	Z23.D, P0/M, Z21.D

0x41b574 SEL	Z21.D, P2, Z21.D, Z23.D

0x41b578 FMUL	Z23.D, Z12.D, Z0.D

0x41b57c FMINNM	Z0.D, P0/M, Z0.D, Z3.D

0x41b580 FMLA	Z23.D, P0/M, Z10.D, Z3.D

0x41b584 FMUL	Z3.D, Z23.D, Z25.D

0x41b588 FMINNM	Z0.D, P0/M, Z0.D, Z3.D

0x41b58c FMUL	Z0.D, Z0.D, Z21.D

0x41b590 CPY	Z0.D, P1/M, #0

0x41b594 FADD	Z0.D, Z2.D, Z0.D

0x41b598 FMUL	Z0.D, Z13.D, Z0.D

0x41b59c ST1D	{Z0.D}, P0, [V4.D]    [13]

0x41b5a0 LDR	Z0, [X19, #511, MUL VL]    [24]

0x41b5a4 ADD	Z29.D, Z29.D, Z0.D

0x41b5a8 CBNZ	X7, 41b3ac

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 66 - 110

--------------------------------------------------------------------------------

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.11 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79 - 1.50
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source	advec_cell.cpp:66-110,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.25 - 40.98
CQA cycles if no scalar integer	27.25 - 40.98
CQA cycles if FP arith vectorized	27.25 - 40.98
CQA cycles if fully vectorized	24.55 - 40.98
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	4.00
P7 cycles	1.00
P8 cycles	27.25
P9 cycles	27.25
P10 cycles	27.25
P11 cycles	27.25
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	11.36 - 40.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	128.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.13 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.03 - 10.57
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	17.00
Stride indirect	7.00
Vectorization ratio all	74.60
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	70.00
Vector-efficiency ratio all	88.24
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.11 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79 - 1.50
Bottlenecks	P8, P10,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source	advec_cell.cpp:66-110,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.25 - 40.98
CQA cycles if no scalar integer	27.25 - 40.98
CQA cycles if FP arith vectorized	27.25 - 40.98
CQA cycles if fully vectorized	24.55 - 40.98
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.17
P5 cycles	0.17
P6 cycles	4.00
P7 cycles	1.00
P8 cycles	27.25
P9 cycles	27.25
P10 cycles	27.25
P11 cycles	27.25
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	11.36 - 40.98
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	128.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.13 - 1.42
Nb FLOP add-sub	20.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.03 - 10.57
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	17.00
Stride indirect	7.00
Vectorization ratio all	74.60
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	70.00
Vector-efficiency ratio all	88.24
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

74% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
70% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
6: divide

The binary loop is loading 256 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	128
loop length	512
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	27.25	27.25	27.25	27.25	6.00	6.00	6.00	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	27.25	27.25	27.25	27.25	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	11.36-40.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Data deps.	2.00
Overall L1	27.25-40.98

Vectorization ratios

INT

all	61%
load	50%
store	100%
mul	100%
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	74%
load	50%
store	100%
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	70%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.98 cycles. At this rate:

6% of peak load performance is reached (6.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b3ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z30.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X19, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X19, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z31.D, Z0.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X19, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z8, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z8.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z0.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X19, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z8.D, Z5.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z11.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z14.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z10.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z11.D, Z11.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z11.D, P0/M, Z11.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z9.D, Z0.D, Z31.D																					vect (100.0%)
DUPM Z0.D, #4294967294	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z12.D}, P0/Z, [X13, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
SMIN Z11.D, P0/M, Z11.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z9.D, [Z19, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z13.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADD Z9.D, Z30.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z8.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P1.D, P0/Z, Z13.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z15.D, P1, Z8.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z8.D, Z6.D, Z31.D																					vect (100.0%)
SEL Z21.D, P1, Z14.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z11.D, P1, Z14.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z9.D, P1, Z10.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z14.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P0/Z, [X13, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z8.D, [Z22, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z11.D, Z7.D, Z31.D																					vect (100.0%)
ADR Z8.D, [Z8, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z24, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z10.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z11.D, [Z0, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIVR Z23.D, P0/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ADR Z12.D, [Z0, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z3.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB Z4.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z4.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z10, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z10.D, P0/M, Z10.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z10.D, Z10.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB Z23.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z3.D, P0/M, Z3.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z23.D, Z23.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z4, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FSUBR Z4.D, P0/M, Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGT P1.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FDUP Z23.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FSUB Z12.D, Z23.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z4.D, P2, Z4.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMINNM Z23.D, P0/M, Z23.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z12.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z0.D, P0/M, Z10.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z4.D, Z18.D, Z31.D																					vect (100.0%)
CPY Z0.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z4.D, [Z28, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z13.D, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z0.D, Z16.D, Z31.D																					vect (100.0%)
ADR Z4.D, [Z4, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z26, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z13.D}, P0, [V0.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z0.D, Z17.D, Z31.D																					vect (100.0%)
LD1D {Z30.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z0.D, [Z27, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z0, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z0, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z21.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z23.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z3.D, P0/M, Z3.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z23, Z13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z23.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P1.D, P0/Z, Z21.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z21.D, Z30.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIVR Z21.D, P0/M, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUBR Z21.D, P0/M, Z21.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z21.D, P2, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z23.D, Z12.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMLA Z23.D, P0/M, Z10.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z3.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
CPY Z0.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z0.D}, P0, [V4.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X19, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z29.D, Z29.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X7, 41b3ac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.4]
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

74% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
70% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
28: multiply (4 inside FMA instructions)
6: divide

The binary loop is loading 256 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	128
loop length	512
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	27.25	27.25	27.25	27.25	6.00	6.00	6.00	0.00	0.00
cycles	0.50	0.50	0.33	0.33	0.17	0.17	4.00	1.00	27.25	27.25	27.25	27.25	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	11.36-40.98
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Data deps.	2.00
Overall L1	27.25-40.98

Vectorization ratios

INT

all	61%
load	50%
store	100%
mul	100%
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	74%
load	50%
store	100%
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	70%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.98 cycles. At this rate:

6% of peak load performance is reached (6.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b3ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SDIV Z30.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X19, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DECD X7, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR Z0, [X19, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z31.D, Z0.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X19, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVPRFX Z8, Z29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
MLS Z8.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	vect (100.0%)
SXTW Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z0.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [X19, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z8.D, Z5.D, Z8.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z11.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z14.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z10.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z11.D, Z11.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SXTW Z11.D, P0/M, Z11.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z9.D, Z0.D, Z31.D																					vect (100.0%)
DUPM Z0.D, #4294967294	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z12.D}, P0/Z, [X13, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
SMIN Z11.D, P0/M, Z11.D, Z20.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z9.D, [Z19, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z9.D, [Z9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z13.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADD Z9.D, Z30.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z8, Z9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
SXTW Z8.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P1.D, P0/Z, Z13.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z15.D, P1, Z8.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MUL Z8.D, Z6.D, Z31.D																					vect (100.0%)
SEL Z21.D, P1, Z14.D, Z10.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z11.D, P1, Z14.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z9.D, P1, Z10.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z14, Z13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z14.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LD1D {Z23.D}, P0/Z, [X13, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADR Z8.D, [Z22, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MUL Z11.D, Z7.D, Z31.D																					vect (100.0%)
ADR Z8.D, [Z8, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z24, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z10.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z11.D, [Z0, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIVR Z23.D, P0/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
ADR Z12.D, [Z0, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z3.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FDIV Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUB Z4.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z4.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z10, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD Z10.D, P0/M, Z10.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z10.D, Z10.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FSUB Z23.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z3.D, P0/M, Z3.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z23.D, Z23.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MOVPRFX Z4, Z14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FSUBR Z4.D, P0/M, Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FCMGT P1.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
FDUP Z23.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FSUB Z12.D, Z23.D, Z14.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z4.D, P2, Z4.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMINNM Z23.D, P0/M, Z23.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z12.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMLA Z0.D, P0/M, Z10.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z4.D, Z18.D, Z31.D																					vect (100.0%)
CPY Z0.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADR Z4.D, [Z28, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL Z13.D, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
MUL Z0.D, Z16.D, Z31.D																					vect (100.0%)
ADR Z4.D, [Z4, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z26, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ST1D {Z13.D}, P0, [V0.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
MUL Z0.D, Z17.D, Z31.D																					vect (100.0%)
LD1D {Z30.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
ADR Z0.D, [Z27, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z2.D, [Z0, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z3.D, [Z0, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADR Z0.D, [Z0, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
FSUB Z21.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FSUB Z23.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FABD Z3.D, P0/M, Z3.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FCMLE P2.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z23, Z13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FABS Z23.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P1.D, P0/Z, Z21.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V8.D]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	9	1	vect (100.0%)
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z21.D, Z30.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FDIVR Z21.D, P0/M, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FSUBR Z21.D, P0/M, Z21.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVPRFX Z23, Z21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FNEG Z23.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SEL Z21.D, P2, Z21.D, Z23.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z23.D, Z12.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMLA Z23.D, P0/M, Z10.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMUL Z3.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
CPY Z0.D, P1/M, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMUL Z0.D, Z13.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
ST1D {Z0.D}, P0, [V4.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Z0, [X19, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD Z29.D, Z29.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CBNZ X7, 41b3ac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code