OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 5.05% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e9b0 SUB	SP, SP, #144

0x41e9b4 STP	D11, D10, [SP, #32]

0x41e9b8 STP	D9, D8, [SP, #48]

0x41e9bc STP	X29, X30, [SP, #64]

0x41e9c0 STR	X25, [SP, #80]

0x41e9c4 STP	X24, X23, [SP, #96]

0x41e9c8 STP	X22, X21, [SP, #112]

0x41e9cc STP	X20, X19, [SP, #128]

0x41e9d0 ADD	X29, SP, #64

0x41e9d4 LDR	W9, [X4]

0x41e9d8 LDR	W8, [X3]

0x41e9dc LDR	W22, [X2]

0x41e9e0 ADD	W23, W9, #1

0x41e9e4 LDR	W9, [X5]

0x41e9e8 ADD	W8, W8, #3

0x41e9ec SUBS	W8, W8, W22

0x41e9f0 ADD	W9, W9, #3

0x41e9f4 CCMP	W9, W23, #4, #12

0x41e9f8 B.LE	41ea78

0x41e9fc LDR	W19, [X0]

0x41ea00 SUB	W24, W9, W23

0x41ea04 MOVN	X9, #0

0x41ea08 ORR	X20, XZR, X7

0x41ea0c ORR	X21, XZR, X6

0x41ea10 ADRP	X0,

0x41ea14 ADD	X0, X0, #264

0x41ea18 ADD	X3, SP, #12

0x41ea1c ADD	X4, X29, #24

0x41ea20 STR	XZR, [X29, #24]

0x41ea24 STR	WZR, [SP, #12]

0x41ea28 ORR	W1, WZR, W19

0x41ea2c UMADDL	X25, W24, W8, X9

0x41ea30 MOVZ	W8, #1

0x41ea34 ADD	X5, SP, #24

0x41ea38 ADD	X6, SP, #16

0x41ea3c MOVZ	W2, #34

0x41ea40 MOVZ	W7, #1

0x41ea44 STP	X8, X25, [SP, #16]

0x41ea48 STR	X8, [SP]

0x41ea4c BL	402e00

0x41ea50 LDR	X8, [SP, #24]

0x41ea54 LDR	X3, [X29, #24]

0x41ea58 CMP	X8, X25

0x41ea5c CSEL	X18, X8, X25, #11

0x41ea60 CMP	X3, X18

0x41ea64 B.LE	41ea9c

(197) 0x41ea68 ADRP	X0,

(197) 0x41ea6c ADD	X0, X0, #288

(197) 0x41ea70 ORR	W1, WZR, W19

(197) 0x41ea74 BL	402cc0

(197) 0x41ea78 LDP	D9, D8, [SP, #48]

(197) 0x41ea7c LDP	D11, D10, [SP, #32]

(197) 0x41ea80 LDP	X20, X19, [SP, #128]

(197) 0x41ea84 LDP	X22, X21, [SP, #112]

(197) 0x41ea88 LDP	X24, X23, [SP, #96]

(197) 0x41ea8c LDR	X25, [SP, #80]

(197) 0x41ea90 LDP	X29, X30, [SP, #64]

(197) 0x41ea94 ADD	SP, SP, #144

(197) 0x41ea98 RET

(197) 0x41ea9c LDP	X13, X16, [X29, #88]

(197) 0x41eaa0 LDR	X14, [X29, #80]

(197) 0x41eaa4 LDR	X8, [X21, #16]

(197) 0x41eaa8 SUB	X17, X18, X3

(197) 0x41eaac CNTD	X2, ALL

(197) 0x41eab0 ADD	X0, X17, #1

(197) 0x41eab4 LDR	X9, [X21]

(197) 0x41eab8 LDR	X10, [X20, #16]

(197) 0x41eabc LDR	X11, [X20]

(197) 0x41eac0 ORR	X17, XZR, X3

(197) 0x41eac4 LDR	X12, [X13, #16]

(197) 0x41eac8 LDR	X13, [X13]

(197) 0x41eacc LDR	X14, [X14, #8]

(197) 0x41ead0 LDR	X15, [X16, #16]

(197) 0x41ead4 LDR	X16, [X16]

(197) 0x41ead8 CMP	X0, X2

(197) 0x41eadc B.CC	41ec8c

(197) 0x41eae0 INDEX	Z24.D, X3, #1

(197) 0x41eae4 SUB	X17, XZR, X2

(197) 0x41eae8 PTRUE	P0.D, ALL

(197) 0x41eaec DUP	Z17.D, #0

(197) 0x41eaf0 DUPM	Z18.D, #4294967295

(197) 0x41eaf4 FDUP	Z21.D, #0

(197) 0x41eaf8 FDUP	Z22.D, #24

(197) 0x41eafc AND	X1, X0, X17

(197) 0x41eb00 ADD	X17, X3, X1

(197) 0x41eb04 DUP	Z0.D, X2

(197) 0x41eb08 ORR	X2, XZR, X1

(197) 0x41eb0c DUP	Z1.D, X24

(197) 0x41eb10 DUP	Z2.D, X22

(197) 0x41eb14 DUP	Z3.D, X23

(197) 0x41eb18 DUP	Z4.D, X9

(197) 0x41eb1c DUP	Z5.D, X11

(197) 0x41eb20 DUP	Z6.D, X13

(197) 0x41eb24 DUP	Z7.D, X16

(197) 0x41eb28 DUP	Z16.D, X8

(197) 0x41eb2c DUP	Z19.D, X10

(197) 0x41eb30 DUP	Z20.D, X12

(197) 0x41eb34 DUP	Z23.D, X15

(197) 0x41eb38 HINT	#0

(197) 0x41eb3c HINT	#0

  (199) 0x41eb40 MOVPRFX	Z25, Z24

  (199) 0x41eb44 SDIV	Z25.D, P0/M, Z25.D, Z1.D

  (199) 0x41eb48 DECD	X2, ALL

  (199) 0x41eb4c ADD	Z28.D, Z2.D, Z25.D

  (199) 0x41eb50 MSB	Z25.D, P0/M, Z1.D, Z24.D

  (199) 0x41eb54 ADD	Z24.D, Z24.D, Z0.D

  (199) 0x41eb58 MOVPRFX	Z26, Z28

  (199) 0x41eb5c SXTW	Z26.D, P0/M, Z28.D

  (199) 0x41eb60 ORR	Z29.D, Z28.D, Z28.D

  (199) 0x41eb64 ORR	Z10.D, Z28.D, Z28.D

  (199) 0x41eb68 ADD	Z31.D, Z28.D, Z18.D

  (199) 0x41eb6c MUL	Z27.D, Z4.D, Z26.D

  (199) 0x41eb70 ADD	Z29.D, Z29.D, #1

  (199) 0x41eb74 ADD	Z10.D, Z10.D, #2

  (199) 0x41eb78 ADD	Z25.D, Z3.D, Z25.D

  (199) 0x41eb7c MOVPRFX	Z30, Z29

  (199) 0x41eb80 SXTW	Z30.D, P0/M, Z29.D

  (199) 0x41eb84 ADR	Z27.D, [Z16, Z27.D,LSL #3]

  (199) 0x41eb88 ADR	Z27.D, [Z27, Z25.D,SXTW #3]

  (199) 0x41eb8c LD1D	{Z27.D}, P0/Z, [V27.D]

  (199) 0x41eb90 FCMLT	P1.D, P0/Z, Z27.D, #0

  (199) 0x41eb94 SEL	Z8.D, P1, Z30.D, Z26.D

  (199) 0x41eb98 SEL	Z10.D, P1, Z10.D, Z31.D

  (199) 0x41eb9c SEL	Z30.D, P1, Z26.D, Z30.D

  (199) 0x41eba0 SEL	Z29.D, P1, Z29.D, Z31.D

  (199) 0x41eba4 MOVPRFX	Z31, Z27

  (199) 0x41eba8 FABS	Z31.D, P0/M, Z27.D

  (199) 0x41ebac MUL	Z26.D, Z7.D, Z26.D

  (199) 0x41ebb0 MUL	Z9.D, Z5.D, Z8.D

  (199) 0x41ebb4 SXTW	Z10.D, P0/M, Z10.D

  (199) 0x41ebb8 MUL	Z8.D, Z6.D, Z8.D

  (199) 0x41ebbc MUL	Z30.D, Z6.D, Z30.D

  (199) 0x41ebc0 MUL	Z10.D, Z6.D, Z10.D

  (199) 0x41ebc4 ADR	Z26.D, [Z23, Z26.D,LSL #3]

  (199) 0x41ebc8 ADR	Z9.D, [Z19, Z9.D,LSL #3]

  (199) 0x41ebcc ADR	Z8.D, [Z20, Z8.D,LSL #3]

  (199) 0x41ebd0 ADR	Z30.D, [Z20, Z30.D,LSL #3]

  (199) 0x41ebd4 ADR	Z9.D, [Z9, Z25.D,SXTW #3]

  (199) 0x41ebd8 ADR	Z10.D, [Z20, Z10.D,LSL #3]

  (199) 0x41ebdc ADR	Z8.D, [Z8, Z25.D,SXTW #3]

  (199) 0x41ebe0 ADR	Z30.D, [Z30, Z25.D,SXTW #3]

  (199) 0x41ebe4 ADR	Z10.D, [Z10, Z25.D,SXTW #3]

  (199) 0x41ebe8 LD1D	{Z9.D}, P0/Z, [V9.D]

  (199) 0x41ebec LD1D	{Z8.D}, P0/Z, [V8.D]

  (199) 0x41ebf0 LD1D	{Z30.D}, P0/Z, [V30.D]

  (199) 0x41ebf4 ADR	Z25.D, [Z26, Z25.D,SXTW #3]

  (199) 0x41ebf8 LD1D	{Z10.D}, P0/Z, [V10.D]

  (199) 0x41ebfc FDIV	Z31.D, P0/M, Z31.D, Z9.D

  (199) 0x41ec00 FSUB	Z11.D, Z30.D, Z8.D

  (199) 0x41ec04 FABD	Z30.D, P0/M, Z30.D, Z8.D

  (199) 0x41ec08 FSUB	Z9.D, Z8.D, Z10.D

  (199) 0x41ec0c FCMLE	P2.D, P0/Z, Z11.D, #0

  (199) 0x41ec10 FMUL	Z9.D, Z9.D, Z11.D

  (199) 0x41ec14 EOR	P2.B, P0/Z, P2.B, P0.B

  (199) 0x41ec18 FCMGT	P1.D, P0/Z, Z9.D, #0

  (199) 0x41ec1c MOVPRFX	Z9, Z8

  (199) 0x41ec20 FABD	Z9.D, P0/M, Z9.D, Z10.D

  (199) 0x41ec24 FSUB	Z10.D, Z21.D, Z31.D

  (199) 0x41ec28 MOVPRFX	Z11, Z31

  (199) 0x41ec2c FADD	Z11.D, P0/M, Z11.D, #1

  (199) 0x41ec30 LD1D	{Z28.D}, P1/Z, [X14, Z28.D,SXTW #3]

  (199) 0x41ec34 LD1D	{Z29.D}, P1/Z, [X14, Z29.D,SXTW #3]

  (199) 0x41ec38 FMUL	Z10.D, Z10.D, Z30.D

  (199) 0x41ec3c FMUL	Z11.D, Z11.D, Z9.D

  (199) 0x41ec40 FDIV	Z10.D, P0/M, Z10.D, Z28.D

  (199) 0x41ec44 FDIVR	Z29.D, P0/M, Z29.D, Z11.D

  (199) 0x41ec48 FADD	Z29.D, Z10.D, Z29.D

  (199) 0x41ec4c FMUL	Z28.D, Z28.D, Z29.D

  (199) 0x41ec50 FDIV	Z28.D, P0/M, Z28.D, Z22.D

  (199) 0x41ec54 FMINNM	Z28.D, P0/M, Z28.D, Z9.D

  (199) 0x41ec58 FMINNM	Z28.D, P0/M, Z28.D, Z30.D

  (199) 0x41ec5c MOVPRFX	Z29, Z28

  (199) 0x41ec60 FNEG	Z29.D, P0/M, Z28.D

  (199) 0x41ec64 SEL	Z28.D, P2, Z28.D, Z29.D

  (199) 0x41ec68 MOVPRFX	Z29, Z31

  (199) 0x41ec6c FSUBR	Z29.D, P0/M, Z29.D, #1

  (199) 0x41ec70 SEL	Z28.D, P1, Z28.D, Z17.D

  (199) 0x41ec74 FMAD	Z28.D, P0/M, Z29.D, Z8.D

  (199) 0x41ec78 FMUL	Z27.D, Z27.D, Z28.D

  (199) 0x41ec7c ST1D	{Z27.D}, P0, [V25.D]

  (199) 0x41ec80 CBNZ	X2, 41eb40

(197) 0x41ec84 CMP	X0, X1

(197) 0x41ec88 B.EQ	41ea68

(197) 0x41ec8c FMOV	D0, #2.0000000

(197) 0x41ec90 FMOV	D1, #1.0000000

(197) 0x41ec94 FMOV	D2, #6.0000000

(197) 0x41ec98 ADD	X18, X18, #1

(197) 0x41ec9c SUB	W0, WZR, W24

(197) 0x41eca0 B	41ecc8

  (198) 0x41eca4 FSUB	D4, D1, S4

  (198) 0x41eca8 MADD	X2, X16, X2, XZR

  (198) 0x41ecac ADD	X17, X17, #1

  (198) 0x41ecb0 FMADD	D4, D4, D16, D5

  (198) 0x41ecb4 ADD	X2, X15, X2,LSL #3

  (198) 0x41ecb8 FMUL	D3, D3, D4

  (198) 0x41ecbc STR	D3, [X2, X1,SXTW #3]

  (198) 0x41ecc0 CMP	X18, X17

  (198) 0x41ecc4 B.EQ	41ea68

  (198) 0x41ecc8 SDIV	X1, X17, X24

  (198) 0x41eccc ADD	W2, W23, W17

  (198) 0x41ecd0 ADD	W3, W22, W1

  (198) 0x41ecd4 MADD	W1, W0, W1, W2

  (198) 0x41ecd8 SBFM	X2, X3, #0, #31

  (198) 0x41ecdc ADD	W3, W3, #1

  (198) 0x41ece0 MADD	X4, X9, X2, XZR

  (198) 0x41ece4 ADD	X4, X8, X4,LSL #3

  (198) 0x41ece8 LDR	D3, [X4, X1,SXTW #3]

  (198) 0x41ecec SBFM	X4, X3, #0, #31

  (198) 0x41ecf0 FCMP	D3, #0

  (198) 0x41ecf4 B.PL	41ed04

  (198) 0x41ecf8 ADD	W6, W2, #2

  (198) 0x41ecfc ORR	X5, XZR, X2

  (198) 0x41ed00 B	41ed14

  (198) 0x41ed04 SUB	W3, W2, #1

  (198) 0x41ed08 ORR	X5, XZR, X4

  (198) 0x41ed0c ORR	X4, XZR, X2

  (198) 0x41ed10 ORR	W6, WZR, W3

  (198) 0x41ed14 MADD	X7, X11, X4, XZR

  (198) 0x41ed18 MADD	X4, X13, X4, XZR

  (198) 0x41ed1c FABS	D4, D3

  (198) 0x41ed20 MOVI	D16, #0

  (198) 0x41ed24 ADD	X7, X10, X7,LSL #3

  (198) 0x41ed28 ADD	X4, X12, X4,LSL #3

  (198) 0x41ed2c LDR	D5, [X7, X1,SXTW #3]

  (198) 0x41ed30 FDIV	D4, D4, D5

  (198) 0x41ed34 LDR	D5, [X4, X1,SXTW #3]

  (198) 0x41ed38 SBFM	X4, X6, #0, #31

  (198) 0x41ed3c MADD	X4, X13, X4, XZR

  (198) 0x41ed40 ADD	X4, X12, X4,LSL #3

  (198) 0x41ed44 LDR	D6, [X4, X1,SXTW #3]

  (198) 0x41ed48 MADD	X4, X13, X5, XZR

  (198) 0x41ed4c ADD	X4, X12, X4,LSL #3

  (198) 0x41ed50 FSUB	D7, D5, S6

  (198) 0x41ed54 LDR	D6, [X4, X1,SXTW #3]

  (198) 0x41ed58 FSUB	D6, D6, S5

  (198) 0x41ed5c FMUL	D17, D7, D6

  (198) 0x41ed60 FCMP	D17, #0

  (198) 0x41ed64 B.LE	41eca4

  (198) 0x41ed68 LDR	D16, [X14, X2,LSL #3]

  (198) 0x41ed6c LDR	D20, [X14, X3,SXTW #3]

  (198) 0x41ed70 FABS	D7, D7

  (198) 0x41ed74 FABS	D17, D6

  (198) 0x41ed78 FSUB	D18, D0, S4

  (198) 0x41ed7c FADD	D19, D4, D1

  (198) 0x41ed80 FCMP	D6, #0

  (198) 0x41ed84 FMUL	D18, D18, D17

  (198) 0x41ed88 FMUL	D19, D19, D7

  (198) 0x41ed8c FDIV	D18, D18, D16

  (198) 0x41ed90 FDIV	D19, D19, D20

  (198) 0x41ed94 FADD	D18, D18, D19

  (198) 0x41ed98 FMUL	D16, D16, D18

  (198) 0x41ed9c FDIV	D16, D16, D2

  (198) 0x41eda0 FMINNM	D7, D16, D7

  (198) 0x41eda4 FMINNM	D7, D7, D17

  (198) 0x41eda8 FNEG	D16, D7

  (198) 0x41edac FCSEL	D16, D7, D16, #8

  (198) 0x41edb0 B	41eca4

0x41edb4 HINT	#0

0x41edb8 HINT	#0

0x41edbc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.00 cycles (6.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.17 to 4.37 cycles (1.41x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.17 to 0.50 cycles (12.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	6.17

Vectorization ratios

all	6%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

6% of peak load performance is reached (5.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.70 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e9b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41ea78 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46da10>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #264	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X8, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X18, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41ea9c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.00 cycles (6.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.17 to 0.50 cycles (12.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	6.17

Vectorization ratios

all	6%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

6% of peak load performance is reached (5.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.70 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e9b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41ea78 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46da10>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #264	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X8, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X18, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41ea9c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	5.05	4.21
▼Loop 197 - advec_mom.cpp:180-211 - exec–	0.00	0.00
○Loop 199 - advec_mom.cpp:181-211 - exec	5.05	4.18
○Loop 198 - advec_mom.cpp:181-211 - exec	0.00	0.00

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