OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage (incl. loops): 4.40% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41e190 SUB	SP, SP, #128

0x41e194 STP	X29, X30, [SP, #48]

0x41e198 STP	X26, X25, [SP, #64]

0x41e19c STP	X24, X23, [SP, #80]

0x41e1a0 STP	X22, X21, [SP, #96]

0x41e1a4 STP	X20, X19, [SP, #112]

0x41e1a8 ADD	X29, SP, #48

0x41e1ac LDR	W8, [X2]

0x41e1b0 LDR	W23, [X4]

0x41e1b4 LDR	W9, [X5]

0x41e1b8 ADD	W22, W8, #1

0x41e1bc LDR	W8, [X3]

0x41e1c0 ADD	W25, W23, #1

0x41e1c4 ADD	W9, W9, #3

0x41e1c8 ADD	W8, W8, #3

0x41e1cc SUBS	W8, W8, W22

0x41e1d0 CCMP	W9, W25, #4, #12

0x41e1d4 B.LE	41e3d8

0x41e1d8 LDR	W19, [X0]

0x41e1dc SUB	W24, W9, W25

0x41e1e0 MOVN	X9, #0

0x41e1e4 ORR	X20, XZR, X7

0x41e1e8 ORR	X21, XZR, X6

0x41e1ec ADRP	X0,

0x41e1f0 ADD	X0, X0, #48

0x41e1f4 ADD	X3, SP, #20

0x41e1f8 SUB	X4, X29, #8

0x41e1fc STR	WZR, [SP, #20]

0x41e200 ORR	W1, WZR, W19

0x41e204 UMADDL	X26, W24, W8, X9

0x41e208 MOVZ	W8, #1

0x41e20c SUB	X5, X29, #16

0x41e210 ADD	X6, SP, #24

0x41e214 MOVZ	W2, #34

0x41e218 MOVZ	W7, #1

0x41e21c STP	X26, XZR, [X29, #1008]

0x41e220 STR	X8, [SP, #24]

0x41e224 STR	X8, [SP]

0x41e228 BL	402e00

0x41e22c LDP	X8, X1, [X29, #1008]

0x41e230 CMP	X8, X26

0x41e234 CSEL	X17, X8, X26, #11

0x41e238 CMP	X1, X17

0x41e23c B.GT	41e3c8

0x41e240 LDP	X13, X15, [X29, #80]

0x41e244 LDR	X8, [X21, #16]

0x41e248 LDR	X9, [X21]

0x41e24c SUB	X16, X17, X1

0x41e250 CNTD	X2, ALL

0x41e254 ADD	X18, X16, #1

0x41e258 LDR	X10, [X20, #16]

0x41e25c LDR	X11, [X20]

0x41e260 ORR	X16, XZR, X1

0x41e264 LDR	X12, [X13, #16]

0x41e268 LDR	X13, [X13]

0x41e26c LDR	X14, [X15, #16]

0x41e270 LDR	X15, [X15]

0x41e274 CMP	X18, X2

0x41e278 B.CC	41e350

0x41e27c INDEX	Z21.D, X1, #1

0x41e280 SUB	X16, XZR, X2

0x41e284 PTRUE	P0.D, ALL

0x41e288 AND	X0, X18, X16

0x41e28c ADD	X16, X1, X0

0x41e290 DUP	Z0.D, X2

0x41e294 ORR	X2, XZR, X0

0x41e298 DUP	Z1.D, X24

0x41e29c DUP	Z2.D, X22

0x41e2a0 DUP	Z3.D, X25

0x41e2a4 DUP	Z4.D, X9

0x41e2a8 DUP	Z5.D, X11

0x41e2ac DUP	Z6.D, X23

0x41e2b0 DUP	Z7.D, X13

0x41e2b4 DUP	Z16.D, X15

0x41e2b8 DUP	Z17.D, X8

0x41e2bc DUP	Z18.D, X10

0x41e2c0 DUP	Z19.D, X12

0x41e2c4 DUP	Z20.D, X14

(192) 0x41e2c8 MOVPRFX	Z22, Z21

(192) 0x41e2cc SDIV	Z22.D, P0/M, Z22.D, Z1.D

(192) 0x41e2d0 DECD	X2, ALL

(192) 0x41e2d4 ADD	Z23.D, Z2.D, Z22.D

(192) 0x41e2d8 MSB	Z22.D, P0/M, Z1.D, Z21.D

(192) 0x41e2dc ADD	Z21.D, Z21.D, Z0.D

(192) 0x41e2e0 SXTW	Z23.D, P0/M, Z23.D

(192) 0x41e2e4 MUL	Z25.D, Z4.D, Z23.D

(192) 0x41e2e8 MUL	Z27.D, Z5.D, Z23.D

(192) 0x41e2ec MUL	Z28.D, Z7.D, Z23.D

(192) 0x41e2f0 MUL	Z23.D, Z16.D, Z23.D

(192) 0x41e2f4 ADD	Z24.D, Z3.D, Z22.D

(192) 0x41e2f8 ADD	Z22.D, Z6.D, Z22.D

(192) 0x41e2fc ADR	Z25.D, [Z17, Z25.D,LSL #3]

(192) 0x41e300 ADR	Z27.D, [Z18, Z27.D,LSL #3]

(192) 0x41e304 ADR	Z28.D, [Z19, Z28.D,LSL #3]

(192) 0x41e308 ADR	Z23.D, [Z20, Z23.D,LSL #3]

(192) 0x41e30c ADR	Z25.D, [Z25, Z24.D,SXTW #3]

(192) 0x41e310 ADR	Z27.D, [Z27, Z24.D,SXTW #3]

(192) 0x41e314 ADR	Z22.D, [Z28, Z22.D,SXTW #3]

(192) 0x41e318 ADR	Z23.D, [Z23, Z24.D,SXTW #3]

(192) 0x41e31c LD1D	{Z26.D}, P0/Z, [V25.D]

(192) 0x41e320 LD1D	{Z27.D}, P0/Z, [V27.D]

(192) 0x41e324 LD1D	{Z22.D}, P0/Z, [V22.D]

(192) 0x41e328 LD1D	{Z23.D}, P0/Z, [V23.D]

(192) 0x41e32c FMLA	Z22.D, P0/M, Z26.D, Z27.D

(192) 0x41e330 ADR	Z26.D, [Z28, Z24.D,SXTW #3]

(192) 0x41e334 LD1D	{Z26.D}, P0/Z, [V26.D]

(192) 0x41e338 FSUB	Z22.D, Z22.D, Z26.D

(192) 0x41e33c FDIV	Z22.D, P0/M, Z22.D, Z23.D

(192) 0x41e340 ST1D	{Z22.D}, P0, [V25.D]

(192) 0x41e344 CBNZ	X2, 41e2c8

0x41e348 CMP	X18, X0

0x41e34c B.EQ	41e3c8

0x41e350 ADD	X17, X17, #1

0x41e354 SUB	W18, WZR, W24

0x41e358 HINT	#0

0x41e35c HINT	#0

(191) 0x41e360 SDIV	X0, X16, X24

(191) 0x41e364 ADD	W2, W23, W16

(191) 0x41e368 ADD	X16, X16, #1

(191) 0x41e36c ADD	W1, W22, W0

(191) 0x41e370 MADD	W0, W18, W0, W2

(191) 0x41e374 SBFM	X1, X1, #0, #31

(191) 0x41e378 MADD	X4, X11, X1, XZR

(191) 0x41e37c ADD	W2, W0, #1

(191) 0x41e380 MADD	X3, X9, X1, XZR

(191) 0x41e384 ADD	X4, X10, X4,LSL #3

(191) 0x41e388 ADD	X3, X8, X3,LSL #3

(191) 0x41e38c LDR	D1, [X4, X2,SXTW #3]

(191) 0x41e390 MADD	X4, X13, X1, XZR

(191) 0x41e394 LDR	D0, [X3, X2,SXTW #3]

(191) 0x41e398 ADD	X4, X12, X4,LSL #3

(191) 0x41e39c LDR	D2, [X4, X0,SXTW #3]

(191) 0x41e3a0 MADD	X0, X15, X1, XZR

(191) 0x41e3a4 ADD	X0, X14, X0,LSL #3

(191) 0x41e3a8 FMADD	D0, D0, D1, D2

(191) 0x41e3ac LDR	D1, [X4, X2,SXTW #3]

(191) 0x41e3b0 FSUB	D0, D0, S1

(191) 0x41e3b4 LDR	D1, [X0, X2,SXTW #3]

(191) 0x41e3b8 FDIV	D0, D0, D1

(191) 0x41e3bc STR	D0, [X3, X2,SXTW #3]

(191) 0x41e3c0 CMP	X17, X16

(191) 0x41e3c4 B.NE	41e360

0x41e3c8 ADRP	X0,

0x41e3cc ADD	X0, X0, #72

0x41e3d0 ORR	W1, WZR, W19

0x41e3d4 BL	402cc0

0x41e3d8 LDP	X20, X19, [SP, #112]

0x41e3dc LDP	X22, X21, [SP, #96]

0x41e3e0 LDP	X24, X23, [SP, #80]

0x41e3e4 LDP	X26, X25, [SP, #64]

0x41e3e8 LDP	X29, X30, [SP, #48]

0x41e3ec ADD	SP, SP, #128

0x41e3f0 RET

0x41e3f4 HINT	#0

0x41e3f8 HINT	#0

0x41e3fc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 13.00 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.00 to 8.18 cycles (1.71x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.00 to 1.00 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 196 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	8.83	8.83	8.83	8.83	14.00	8.67	0.50	0.00	0.50	0.00	9.83	9.50	9.67	4.50	4.50
cycles	3.50	3.50	8.83	8.83	8.83	8.83	14.00	8.67	0.50	0.00	0.50	0.00	9.83	9.50	9.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.63
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

14% of peak load performance is reached (14.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e190

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W25, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W25, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41e3d8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d1ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X26, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X1, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X17, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41e3c8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X15, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X16, X17, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X18, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X16, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 41e350 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z21.D, X1, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
SUB X16, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
AND X0, X18, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X1, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z0.D, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z1.D, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z2.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z3.D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z4.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z5.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z6.D, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z7.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z16.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z17.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z18.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z19.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z20.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP X18, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41e3c8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W18, WZR, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <46d3c8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.00 to 1.00 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 196 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	8.83	8.83	8.83	8.83	14.00	8.67	0.50	0.00	0.50	0.00	9.83	9.50	9.67	4.50	4.50
cycles	3.50	3.50	8.83	8.83	8.83	8.83	14.00	8.67	0.50	0.00	0.50	0.00	9.83	9.50	9.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.63
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

14% of peak load performance is reached (14.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e190

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W25, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W25, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41e3d8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d1ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X26, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X1, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X17, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41e3c8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X15, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X16, X17, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X2, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X18, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X16, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 41e350 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z21.D, X1, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
SUB X16, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
AND X0, X18, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X1, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z0.D, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z1.D, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z2.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z3.D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z4.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z5.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z6.D, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z7.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z16.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z17.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z18.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z19.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z20.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP X18, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 41e3c8 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.14+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W18, WZR, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <46d3c8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.40	3.66
○Loop 192 - advec_mom.cpp:147-149 - exec	4.40	3.64
○Loop 191 - advec_mom.cpp:147-149 - exec	0.00	0.00

Report Configuration

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code