OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 4.53% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41dd70 SUB	SP, SP, #144

0x41dd74 STP	D11, D10, [SP, #32]

0x41dd78 STP	D9, D8, [SP, #48]

0x41dd7c STP	X29, X30, [SP, #64]

0x41dd80 STR	X25, [SP, #80]

0x41dd84 STP	X24, X23, [SP, #96]

0x41dd88 STP	X22, X21, [SP, #112]

0x41dd8c STP	X20, X19, [SP, #128]

0x41dd90 ADD	X29, SP, #64

0x41dd94 LDR	W8, [X2]

0x41dd98 LDR	W9, [X5]

0x41dd9c LDR	W23, [X4]

0x41dda0 ADD	W22, W8, #1

0x41dda4 LDR	W8, [X3]

0x41dda8 ADD	W9, W9, #3

0x41ddac ADD	W8, W8, #3

0x41ddb0 SUBS	W8, W8, W22

0x41ddb4 CCMP	W9, W23, #4, #12

0x41ddb8 B.LE	41de38

0x41ddbc LDR	W19, [X0]

0x41ddc0 SUB	W24, W9, W23

0x41ddc4 MOVN	X9, #0

0x41ddc8 ORR	X20, XZR, X7

0x41ddcc ORR	X21, XZR, X6

0x41ddd0 ADRP	X0,

0x41ddd4 ADD	X0, X0, #4072

0x41ddd8 ADD	X3, SP, #12

0x41dddc ADD	X4, X29, #24

0x41dde0 STR	XZR, [X29, #24]

0x41dde4 STR	WZR, [SP, #12]

0x41dde8 ORR	W1, WZR, W19

0x41ddec UMADDL	X25, W24, W8, X9

0x41ddf0 MOVZ	W8, #1

0x41ddf4 ADD	X5, SP, #24

0x41ddf8 ADD	X6, SP, #16

0x41ddfc MOVZ	W2, #34

0x41de00 MOVZ	W7, #1

0x41de04 STP	X8, X25, [SP, #16]

0x41de08 STR	X8, [SP]

0x41de0c BL	402e00

0x41de10 LDR	X8, [SP, #24]

0x41de14 LDR	X3, [X29, #24]

0x41de18 CMP	X8, X25

0x41de1c CSEL	X18, X8, X25, #11

0x41de20 CMP	X3, X18

0x41de24 B.LE	41de5c

    (190) 0x41de28 ADRP	X0,

    (190) 0x41de2c ADD	X0, X0, #0

    (190) 0x41de30 ORR	W1, WZR, W19

    (190) 0x41de34 BL	402cc0

    (190) 0x41de38 LDP	D9, D8, [SP, #48]

    (190) 0x41de3c LDP	D11, D10, [SP, #32]

    (190) 0x41de40 LDP	X20, X19, [SP, #128]

    (190) 0x41de44 LDP	X22, X21, [SP, #112]

    (190) 0x41de48 LDP	X24, X23, [SP, #96]

    (190) 0x41de4c LDR	X25, [SP, #80]

    (190) 0x41de50 LDP	X29, X30, [SP, #64]

    (190) 0x41de54 ADD	SP, SP, #144

    (190) 0x41de58 RET

    (190) 0x41de5c LDP	X13, X16, [X29, #88]

    (190) 0x41de60 LDR	X14, [X29, #80]

    (190) 0x41de64 LDR	X8, [X21, #16]

    (190) 0x41de68 SUB	X17, X18, X3

    (190) 0x41de6c CNTD	X2, ALL

    (190) 0x41de70 ADD	X0, X17, #1

    (190) 0x41de74 LDR	X9, [X21]

    (190) 0x41de78 LDR	X10, [X20, #16]

    (190) 0x41de7c LDR	X11, [X20]

    (190) 0x41de80 ORR	X17, XZR, X3

    (190) 0x41de84 LDR	X12, [X13, #16]

    (190) 0x41de88 LDR	X13, [X13]

    (190) 0x41de8c LDR	X14, [X14, #8]

    (190) 0x41de90 LDR	X15, [X16, #16]

    (190) 0x41de94 LDR	X16, [X16]

    (190) 0x41de98 CMP	X0, X2

    (190) 0x41de9c B.CC	41e038

    (190) 0x41dea0 INDEX	Z24.D, X3, #1

    (190) 0x41dea4 SUB	X17, XZR, X2

    (190) 0x41dea8 PTRUE	P0.D, ALL

    (190) 0x41deac DUP	Z17.D, #0

    (190) 0x41deb0 DUPM	Z18.D, #4294967295

    (190) 0x41deb4 FDUP	Z21.D, #0

    (190) 0x41deb8 FDUP	Z22.D, #24

    (190) 0x41debc AND	X1, X0, X17

    (190) 0x41dec0 ADD	X17, X3, X1

    (190) 0x41dec4 DUP	Z0.D, X2

    (190) 0x41dec8 ORR	X2, XZR, X1

    (190) 0x41decc DUP	Z1.D, X24

    (190) 0x41ded0 DUP	Z2.D, X22

    (190) 0x41ded4 DUP	Z3.D, X23

    (190) 0x41ded8 DUP	Z4.D, X9

    (190) 0x41dedc DUP	Z5.D, X11

    (190) 0x41dee0 DUP	Z6.D, X13

    (190) 0x41dee4 DUP	Z7.D, X16

    (190) 0x41dee8 DUP	Z16.D, X8

    (190) 0x41deec DUP	Z19.D, X10

    (190) 0x41def0 DUP	Z20.D, X12

    (190) 0x41def4 DUP	Z23.D, X15

    (190) 0x41def8 HINT	#0

    (190) 0x41defc HINT	#0

      (189) 0x41df00 MOVPRFX	Z25, Z24

      (189) 0x41df04 SDIV	Z25.D, P0/M, Z25.D, Z1.D

      (189) 0x41df08 DECD	X2, ALL

      (189) 0x41df0c ADD	Z26.D, Z2.D, Z25.D

      (189) 0x41df10 MSB	Z25.D, P0/M, Z1.D, Z24.D

      (189) 0x41df14 ADD	Z24.D, Z24.D, Z0.D

      (189) 0x41df18 SXTW	Z26.D, P0/M, Z26.D

      (189) 0x41df1c MUL	Z27.D, Z4.D, Z26.D

      (189) 0x41df20 MUL	Z8.D, Z5.D, Z26.D

      (189) 0x41df24 MUL	Z10.D, Z6.D, Z26.D

      (189) 0x41df28 MUL	Z26.D, Z7.D, Z26.D

      (189) 0x41df2c ADD	Z25.D, Z3.D, Z25.D

      (189) 0x41df30 ORR	Z29.D, Z25.D, Z25.D

      (189) 0x41df34 MOVPRFX	Z28, Z25

      (189) 0x41df38 SXTW	Z28.D, P0/M, Z25.D

      (189) 0x41df3c ORR	Z11.D, Z25.D, Z25.D

      (189) 0x41df40 ADD	Z31.D, Z25.D, Z18.D

      (189) 0x41df44 ADR	Z27.D, [Z16, Z27.D,LSL #3]

      (189) 0x41df48 ADD	Z29.D, Z29.D, #1

      (189) 0x41df4c ADR	Z8.D, [Z19, Z8.D,LSL #3]

      (189) 0x41df50 ADD	Z11.D, Z11.D, #2

      (189) 0x41df54 ADR	Z10.D, [Z20, Z10.D,LSL #3]

      (189) 0x41df58 ADR	Z26.D, [Z23, Z26.D,LSL #3]

      (189) 0x41df5c ADR	Z27.D, [Z27, Z25.D,SXTW #3]

      (189) 0x41df60 MOVPRFX	Z30, Z29

      (189) 0x41df64 SXTW	Z30.D, P0/M, Z29.D

      (189) 0x41df68 LD1D	{Z27.D}, P0/Z, [V27.D]

      (189) 0x41df6c FCMLT	P1.D, P0/Z, Z27.D, #0

      (189) 0x41df70 SEL	Z9.D, P1, Z30.D, Z28.D

      (189) 0x41df74 SEL	Z28.D, P1, Z28.D, Z30.D

      (189) 0x41df78 SEL	Z30.D, P1, Z11.D, Z31.D

      (189) 0x41df7c SEL	Z29.D, P1, Z29.D, Z31.D

      (189) 0x41df80 MOVPRFX	Z31, Z27

      (189) 0x41df84 FABS	Z31.D, P0/M, Z27.D

      (189) 0x41df88 ADR	Z8.D, [Z8, Z9.D,LSL #3]

      (189) 0x41df8c ADR	Z9.D, [Z10, Z9.D,LSL #3]

      (189) 0x41df90 ADR	Z30.D, [Z10, Z30.D,SXTW #3]

      (189) 0x41df94 ADR	Z28.D, [Z10, Z28.D,LSL #3]

      (189) 0x41df98 LD1D	{Z8.D}, P0/Z, [V8.D]

      (189) 0x41df9c FDIV	Z31.D, P0/M, Z31.D, Z8.D

      (189) 0x41dfa0 LD1D	{Z9.D}, P0/Z, [V9.D]

      (189) 0x41dfa4 LD1D	{Z30.D}, P0/Z, [V30.D]

      (189) 0x41dfa8 LD1D	{Z28.D}, P0/Z, [V28.D]

      (189) 0x41dfac FSUB	Z8.D, Z9.D, Z30.D

      (189) 0x41dfb0 FSUB	Z10.D, Z28.D, Z9.D

      (189) 0x41dfb4 FABD	Z30.D, P0/M, Z30.D, Z9.D

      (189) 0x41dfb8 FABD	Z28.D, P0/M, Z28.D, Z9.D

      (189) 0x41dfbc FMUL	Z8.D, Z8.D, Z10.D

      (189) 0x41dfc0 FCMLE	P2.D, P0/Z, Z10.D, #0

      (189) 0x41dfc4 EOR	P2.B, P0/Z, P2.B, P0.B

      (189) 0x41dfc8 FCMGT	P1.D, P0/Z, Z8.D, #0

      (189) 0x41dfcc LD1D	{Z8.D}, P1/Z, [X14, Z25.D,SXTW #3]

      (189) 0x41dfd0 ADR	Z25.D, [Z26, Z25.D,SXTW #3]

      (189) 0x41dfd4 FSUB	Z10.D, Z21.D, Z31.D

      (189) 0x41dfd8 MOVPRFX	Z11, Z31

      (189) 0x41dfdc FADD	Z11.D, P0/M, Z11.D, #1

      (189) 0x41dfe0 FMUL	Z10.D, Z10.D, Z28.D

      (189) 0x41dfe4 LD1D	{Z29.D}, P1/Z, [X14, Z29.D,SXTW #3]

      (189) 0x41dfe8 FMUL	Z11.D, Z11.D, Z30.D

      (189) 0x41dfec FDIV	Z10.D, P0/M, Z10.D, Z8.D

      (189) 0x41dff0 FDIVR	Z29.D, P0/M, Z29.D, Z11.D

      (189) 0x41dff4 FADD	Z29.D, Z10.D, Z29.D

      (189) 0x41dff8 FMUL	Z29.D, Z8.D, Z29.D

      (189) 0x41dffc FDIV	Z29.D, P0/M, Z29.D, Z22.D

      (189) 0x41e000 FMINNM	Z29.D, P0/M, Z29.D, Z30.D

      (189) 0x41e004 FMINNM	Z28.D, P0/M, Z28.D, Z29.D

      (189) 0x41e008 MOVPRFX	Z29, Z28

      (189) 0x41e00c FNEG	Z29.D, P0/M, Z28.D

      (189) 0x41e010 SEL	Z28.D, P2, Z28.D, Z29.D

      (189) 0x41e014 MOVPRFX	Z29, Z31

      (189) 0x41e018 FSUBR	Z29.D, P0/M, Z29.D, #1

      (189) 0x41e01c SEL	Z28.D, P1, Z28.D, Z17.D

      (189) 0x41e020 FMAD	Z28.D, P0/M, Z29.D, Z9.D

      (189) 0x41e024 FMUL	Z27.D, Z27.D, Z28.D

      (189) 0x41e028 ST1D	{Z27.D}, P0, [V25.D]

      (189) 0x41e02c CBNZ	X2, 41df00

    (190) 0x41e030 CMP	X0, X1

    (190) 0x41e034 B.EQ	41de28

  (188) 0x41e038 FMOV	D0, #2.0000000

  (188) 0x41e03c FMOV	D1, #1.0000000

  (188) 0x41e040 FMOV	D2, #6.0000000

  (188) 0x41e044 ADD	X18, X18, #1

  (188) 0x41e048 SUB	W0, WZR, W24

  (188) 0x41e04c B	41e084

0x41e050 HINT	#0

0x41e054 HINT	#0

0x41e058 HINT	#0

0x41e05c HINT	#0

  (188) 0x41e060 FSUB	D4, D1, S4

  (188) 0x41e064 MADD	X2, X16, X2, XZR

  (188) 0x41e068 ADD	X17, X17, #1

  (188) 0x41e06c FMADD	D4, D4, D16, D5

  (188) 0x41e070 ADD	X2, X15, X2,LSL #3

  (188) 0x41e074 FMUL	D3, D3, D4

  (188) 0x41e078 STR	D3, [X2, X1,LSL #3]

  (188) 0x41e07c CMP	X18, X17

  (188) 0x41e080 B.EQ	41de28

  (188) 0x41e084 SDIV	X5, X17, X24

  (188) 0x41e088 ADD	X3, X23, X17

  (188) 0x41e08c ADD	W2, W22, W5

  (188) 0x41e090 MADD	W4, W0, W5, W3

  (188) 0x41e094 SBFM	X2, X2, #0, #31

  (188) 0x41e098 MADD	X6, X9, X2, XZR

  (188) 0x41e09c SBFM	X1, X4, #0, #31

  (188) 0x41e0a0 ADD	X6, X8, X6,LSL #3

  (188) 0x41e0a4 LDR	D3, [X6, X4,SXTW #3]

  (188) 0x41e0a8 MADD	W4, W0, W5, WZR

  (188) 0x41e0ac ADD	X3, X3, X4

  (188) 0x41e0b0 ADD	X3, X3, #1

  (188) 0x41e0b4 SBFM	X4, X3, #0, #31

  (188) 0x41e0b8 FCMP	D3, #0

  (188) 0x41e0bc B.PL	41e0e0

  (188) 0x41e0c0 ADD	W6, W23, W17

  (188) 0x41e0c4 MADD	W5, W0, W5, W6

  (188) 0x41e0c8 ADD	W6, W5, #2

  (188) 0x41e0cc ORR	X5, XZR, X1

  (188) 0x41e0d0 B	41e0f8

0x41e0d4 HINT	#0

0x41e0d8 HINT	#0

0x41e0dc HINT	#0

(187) 0x41e0e0 MSUB	W3, W5, W24, W17

(187) 0x41e0e4 ORR	X5, XZR, X4

(187) 0x41e0e8 ORR	X4, XZR, X1

(187) 0x41e0ec ADD	W3, W23, W3

(187) 0x41e0f0 SUB	W3, W3, #1

(187) 0x41e0f4 ORR	W6, WZR, W3

  (188) 0x41e0f8 MADD	X7, X11, X2, XZR

  (188) 0x41e0fc FABS	D4, D3

  (188) 0x41e100 MOVI	D16, #0

  (188) 0x41e104 ADD	X7, X10, X7,LSL #3

  (188) 0x41e108 LDR	D5, [X7, X4,LSL #3]

  (188) 0x41e10c MADD	X7, X13, X2, XZR

  (188) 0x41e110 ADD	X7, X12, X7,LSL #3

  (188) 0x41e114 LDR	D6, [X7, X6,SXTW #3]

  (188) 0x41e118 FDIV	D4, D4, D5

  (188) 0x41e11c LDR	D5, [X7, X4,LSL #3]

  (188) 0x41e120 FSUB	D7, D5, S6

  (188) 0x41e124 LDR	D6, [X7, X5,LSL #3]

  (188) 0x41e128 FSUB	D6, D6, S5

  (188) 0x41e12c FMUL	D17, D7, D6

  (188) 0x41e130 FCMP	D17, #0

  (188) 0x41e134 B.LE	41e060

  (188) 0x41e138 LDR	D16, [X14, X1,LSL #3]

  (188) 0x41e13c LDR	D20, [X14, X3,SXTW #3]

  (188) 0x41e140 FABS	D7, D7

  (188) 0x41e144 FABS	D17, D6

  (188) 0x41e148 FSUB	D18, D0, S4

  (188) 0x41e14c FADD	D19, D4, D1

  (188) 0x41e150 FCMP	D6, #0

  (188) 0x41e154 FMUL	D18, D18, D17

  (188) 0x41e158 FMUL	D19, D19, D7

  (188) 0x41e15c FDIV	D18, D18, D16

  (188) 0x41e160 FDIV	D19, D19, D20

  (188) 0x41e164 FADD	D18, D18, D19

  (188) 0x41e168 FMUL	D16, D16, D18

  (188) 0x41e16c FDIV	D16, D16, D2

  (188) 0x41e170 FMINNM	D7, D16, D7

  (188) 0x41e174 FMINNM	D7, D7, D17

  (188) 0x41e178 FNEG	D16, D7

  (188) 0x41e17c FCSEL	D16, D7, D16, #8

  (188) 0x41e180 B	41e060

0x41e184 HINT	#0

0x41e188 HINT	#0

0x41e18c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.00 cycles (6.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.17 to 4.37 cycles (1.41x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.17 to 0.50 cycles (12.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	6.17

Vectorization ratios

all	6%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

6% of peak load performance is reached (5.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.70 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41dd70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41de38 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46cdd0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X8, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X18, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41de5c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.00 cycles (6.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.17 to 0.50 cycles (12.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	1.50	1.50	4.42	4.42	4.33	4.33	4.25	4.25	1.00	1.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Overall L1	6.17

Vectorization ratios

all	6%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

6% of peak load performance is reached (5.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.70 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41dd70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41de38 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46cdd0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X8, X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X18, X8, X25, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41de5c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.53	3.78
▼Loop 187 - context.h:69-69 - exec–	0.00	0.00
▼Loop 188 - advec_mom.cpp:108-139 - exec–	0.00	0.00
▼Loop 190 - advec_mom.cpp:108-139 - exec–	0.00	0.00
○Loop 189 - advec_mom.cpp:109-139 - exec	4.53	3.75

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Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code