OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage (incl. loops): 3.75% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41c050 STP	D15, D14, [SP, #864]!

0x41c054 STP	D13, D12, [SP, #16]

0x41c058 STP	D11, D10, [SP, #32]

0x41c05c STP	D9, D8, [SP, #48]

0x41c060 STP	X29, X30, [SP, #64]

0x41c064 STP	X28, X27, [SP, #80]

0x41c068 STP	X26, X25, [SP, #96]

0x41c06c STP	X24, X23, [SP, #112]

0x41c070 STP	X22, X21, [SP, #128]

0x41c074 STP	X20, X19, [SP, #144]

0x41c078 ADD	X29, SP, #64

0x41c07c SUB	SP, SP, #48

0x41c080 ADDVL	SP, SP, #61

0x41c084 LDR	W9, [X4]

0x41c088 LDR	W22, [X2]

0x41c08c LDR	W27, [X3]

0x41c090 ADD	W24, W9, #1

0x41c094 LDR	W9, [X5]

0x41c098 ADD	W23, W22, #1

0x41c09c ADD	W8, W27, #4

0x41c0a0 SUBS	W8, W8, W23

0x41c0a4 ADD	W9, W9, #2

0x41c0a8 CCMP	W9, W24, #4, #12

0x41c0ac B.LE	41c128

0x41c0b0 LDR	W1, [X0]

0x41c0b4 SUB	W25, W9, W24

0x41c0b8 MOVN	X9, #0

0x41c0bc ORR	X20, XZR, X7

0x41c0c0 ORR	X21, XZR, X6

0x41c0c4 ADRP	X0,

0x41c0c8 ADD	X0, X0, #3496

0x41c0cc ADD	X3, SP, #20

0x41c0d0 ADD	X4, SP, #40

0x41c0d4 STP	W1, WZR, [SP, #16]

0x41c0d8 UMADDL	X26, W25, W8, X9

0x41c0dc MOVZ	W8, #1

0x41c0e0 ADD	X5, SP, #32

0x41c0e4 ADD	X6, SP, #24

0x41c0e8 MOVZ	W2, #34

0x41c0ec MOVZ	W7, #1

0x41c0f0 STP	X26, XZR, [SP, #32]

0x41c0f4 STR	X8, [SP, #24]

0x41c0f8 STR	X8, [SP]

0x41c0fc BL	402e00

0x41c100 LDR	X8, [SP, #32]

0x41c104 CMP	X8, X26

0x41c108 CSEL	X4, X8, X26, #11

0x41c10c LDR	X26, [SP, #40]

0x41c110 CMP	X26, X4

0x41c114 B.LE	41c15c

    (172) 0x41c118 LDR	W1, [SP, #16]

    (172) 0x41c11c ADRP	X0,

    (172) 0x41c120 ADD	X0, X0, #3520

    (172) 0x41c124 BL	402cc0

    (172) 0x41c128 ADDVL	SP, SP, #3

    (172) 0x41c12c ADD	SP, SP, #48

    (172) 0x41c130 LDP	D9, D8, [SP, #48]

    (172) 0x41c134 LDP	D11, D10, [SP, #32]

    (172) 0x41c138 LDP	D13, D12, [SP, #16]

    (172) 0x41c13c LDP	X20, X19, [SP, #144]

    (172) 0x41c140 LDP	X22, X21, [SP, #128]

    (172) 0x41c144 LDP	X24, X23, [SP, #112]

    (172) 0x41c148 LDP	X26, X25, [SP, #96]

    (172) 0x41c14c LDP	X28, X27, [SP, #80]

    (172) 0x41c150 LDP	X29, X30, [SP, #64]

    (172) 0x41c154 LDP	D15, D14, [SP], #160

    (172) 0x41c158 RET

    (172) 0x41c15c LDP	X0, X2, [X29, #128]

    (172) 0x41c160 LDR	X17, [X29, #120]

    (172) 0x41c164 LDP	X13, X15, [X29, #96]

    (172) 0x41c168 SUB	X1, X4, X26

    (172) 0x41c16c CNTD	X7, ALL

    (172) 0x41c170 ADD	W10, W27, #2

    (172) 0x41c174 ORR	X3, XZR, X26

    (172) 0x41c178 ADD	X5, X1, #1

    (172) 0x41c17c LDR	X8, [X21, #16]

    (172) 0x41c180 LDR	X9, [X21]

    (172) 0x41c184 LDR	X11, [X20, #16]

    (172) 0x41c188 LDR	X12, [X20]

    (172) 0x41c18c LDR	X13, [X13, #8]

    (172) 0x41c190 LDR	X14, [X15, #16]

    (172) 0x41c194 LDR	X15, [X15]

    (172) 0x41c198 LDR	X16, [X17, #16]

    (172) 0x41c19c LDR	X17, [X17]

    (172) 0x41c1a0 LDR	X18, [X0, #16]

    (172) 0x41c1a4 LDR	X0, [X0]

    (172) 0x41c1a8 LDR	X1, [X2, #16]

    (172) 0x41c1ac LDR	X2, [X2]

    (172) 0x41c1b0 CMP	X5, X7

    (172) 0x41c1b4 B.CC	41c464

    (172) 0x41c1b8 DUP	Z0.D, X7

    (172) 0x41c1bc SUB	X19, X29, #64

    (172) 0x41c1c0 SUB	X3, XZR, X7

    (172) 0x41c1c4 ORR	X7, XZR, #3840

    (172) 0x41c1c8 PTRUE	P0.D, ALL

    (172) 0x41c1cc MOVK	X7, #16325

    (172) 0x41c1d0 INDEX	Z29.D, X26, #1

    (172) 0x41c1d4 AND	X6, X5, X3

    (172) 0x41c1d8 ADD	X3, X26, X6

    (172) 0x41c1dc STR	Z0, [X19, #511, MUL VL]

    (172) 0x41c1e0 DUP	Z0.D, X23

    (172) 0x41c1e4 DUP	Z20.D, X10

    (172) 0x41c1e8 SXTW	Z20.D, P0/M, Z20.D

    (172) 0x41c1ec STR	Z0, [X19, #510, MUL VL]

    (172) 0x41c1f0 DUP	Z1.D, X25

    (172) 0x41c1f4 DUP	Z0.D, X24

    (172) 0x41c1f8 STR	Z0, [X19, #509, MUL VL]

    (172) 0x41c1fc DUP	Z4.D, X9

    (172) 0x41c200 DUP	Z5.D, X22

    (172) 0x41c204 DUP	Z6.D, X12

    (172) 0x41c208 DUP	Z7.D, X15

    (172) 0x41c20c DUP	Z16.D, X17

    (172) 0x41c210 DUP	Z17.D, X0

    (172) 0x41c214 DUP	Z18.D, X2

    (172) 0x41c218 DUP	Z19.D, X8

    (172) 0x41c21c DUP	Z22.D, X11

    (172) 0x41c220 DUP	Z24.D, X14

    (172) 0x41c224 DUP	Z25.D, X7

    (172) 0x41c228 ORR	X7, XZR, X6

    (172) 0x41c22c DUP	Z26.D, X16

    (172) 0x41c230 DUP	Z27.D, X18

    (172) 0x41c234 DUP	Z28.D, X1

    (172) 0x41c238 HINT	#0

    (172) 0x41c23c HINT	#0

      (171) 0x41c240 MOVPRFX	Z9, Z29

      (171) 0x41c244 SDIV	Z9.D, P0/M, Z9.D, Z1.D

      (171) 0x41c248 SUB	X19, X29, #64

      (171) 0x41c24c DECD	X7, ALL

      (171) 0x41c250 LDR	Z0, [X19, #510, MUL VL]

      (171) 0x41c254 ADD	Z10.D, Z0.D, Z9.D

      (171) 0x41c258 LDR	Z0, [X19, #509, MUL VL]

      (171) 0x41c25c MOVPRFX	Z30, Z29

      (171) 0x41c260 MLS	Z30.D, P0/M, Z9.D, Z1.D

      (171) 0x41c264 MOVPRFX	Z31, Z10

      (171) 0x41c268 SXTW	Z31.D, P0/M, Z10.D

      (171) 0x41c26c LD1D	{Z13.D}, P0/Z, [X13, Z10.D,SXTW #3]

      (171) 0x41c270 MUL	Z8.D, Z4.D, Z31.D

      (171) 0x41c274 ADD	Z30.D, Z0.D, Z30.D

      (171) 0x41c278 DUPM	Z0.D, #4294967294

      (171) 0x41c27c ADD	Z12.D, Z10.D, Z0.D

      (171) 0x41c280 ADD	Z10.D, Z10.D, #1

      (171) 0x41c284 ADR	Z8.D, [Z19, Z8.D,LSL #3]

      (171) 0x41c288 SXTW	Z10.D, P0/M, Z10.D

      (171) 0x41c28c ADR	Z8.D, [Z8, Z30.D,SXTW #3]

      (171) 0x41c290 MOVPRFX	Z14, Z20

      (171) 0x41c294 SMIN	Z14.D, P0/M, Z14.D, Z10.D

      (171) 0x41c298 ADD	Z10.D, Z5.D, Z9.D

      (171) 0x41c29c LD1D	{Z8.D}, P0/Z, [V8.D]

      (171) 0x41c2a0 MOVPRFX	Z11, Z10

      (171) 0x41c2a4 SXTW	Z11.D, P0/M, Z10.D

      (171) 0x41c2a8 FCMGT	P1.D, P0/Z, Z8.D, #0

      (171) 0x41c2ac SEL	Z15.D, P1, Z11.D, Z31.D

      (171) 0x41c2b0 SEL	Z10.D, P1, Z10.D, Z14.D

      (171) 0x41c2b4 SEL	Z12.D, P1, Z12.D, Z14.D

      (171) 0x41c2b8 SEL	Z11.D, P1, Z31.D, Z11.D

      (171) 0x41c2bc MOVPRFX	Z14, Z8

      (171) 0x41c2c0 FABS	Z14.D, P0/M, Z8.D

      (171) 0x41c2c4 MUL	Z9.D, Z6.D, Z15.D

      (171) 0x41c2c8 LD1D	{Z23.D}, P0/Z, [X13, Z10.D,SXTW #3]

      (171) 0x41c2cc SXTW	Z12.D, P0/M, Z12.D

      (171) 0x41c2d0 MUL	Z10.D, Z7.D, Z15.D

      (171) 0x41c2d4 ADR	Z9.D, [Z22, Z9.D,LSL #3]

      (171) 0x41c2d8 ADR	Z10.D, [Z24, Z10.D,LSL #3]

      (171) 0x41c2dc ADR	Z9.D, [Z9, Z30.D,SXTW #3]

      (171) 0x41c2e0 ADR	Z10.D, [Z10, Z30.D,SXTW #3]

      (171) 0x41c2e4 LD1D	{Z21.D}, P0/Z, [V9.D]

      (171) 0x41c2e8 LD1D	{Z0.D}, P0/Z, [V10.D]

      (171) 0x41c2ec FDIVR	Z23.D, P0/M, Z23.D, Z13.D

      (171) 0x41c2f0 MUL	Z13.D, Z7.D, Z12.D

      (171) 0x41c2f4 ADR	Z13.D, [Z24, Z13.D,LSL #3]

      (171) 0x41c2f8 ADR	Z13.D, [Z13, Z30.D,SXTW #3]

      (171) 0x41c2fc FDIVR	Z21.D, P0/M, Z21.D, Z14.D

      (171) 0x41c300 MUL	Z14.D, Z7.D, Z11.D

      (171) 0x41c304 LD1D	{Z13.D}, P0/Z, [V13.D]

      (171) 0x41c308 ADR	Z14.D, [Z24, Z14.D,LSL #3]

      (171) 0x41c30c ADR	Z14.D, [Z14, Z30.D,SXTW #3]

      (171) 0x41c310 LD1D	{Z14.D}, P0/Z, [V14.D]

      (171) 0x41c314 FSUB	Z2.D, Z0.D, Z13.D

      (171) 0x41c318 FSUB	Z3.D, Z14.D, Z0.D

      (171) 0x41c31c FMUL	Z2.D, Z2.D, Z3.D

      (171) 0x41c320 FCMLE	P2.D, P0/Z, Z3.D, #0

      (171) 0x41c324 FDUP	Z3.D, #0

      (171) 0x41c328 FSUB	Z3.D, Z3.D, Z21.D

      (171) 0x41c32c EOR	P2.B, P0/Z, P2.B, P0.B

      (171) 0x41c330 FCMGT	P1.D, P0/Z, Z2.D, #0

      (171) 0x41c334 MOVPRFX	Z2, Z21

      (171) 0x41c338 FADD	Z2.D, P0/M, Z2.D, #1

      (171) 0x41c33c FSUBR	Z21.D, P0/M, Z21.D, #1

      (171) 0x41c340 FMUL	Z2.D, Z2.D, Z23.D

      (171) 0x41c344 MOVPRFX	Z23, Z21

      (171) 0x41c348 FNEG	Z23.D, P0/M, Z21.D

      (171) 0x41c34c EOR	P1.B, P0/Z, P1.B, P0.B

      (171) 0x41c350 SEL	Z21.D, P2, Z21.D, Z23.D

      (171) 0x41c354 MOVPRFX	Z23, Z0

      (171) 0x41c358 FABD	Z23.D, P0/M, Z23.D, Z13.D

      (171) 0x41c35c MOVPRFX	Z13, Z14

      (171) 0x41c360 FABD	Z13.D, P0/M, Z13.D, Z0.D

      (171) 0x41c364 MOVPRFX	Z14, Z23

      (171) 0x41c368 FMINNM	Z14.D, P0/M, Z14.D, Z13.D

      (171) 0x41c36c FMUL	Z13.D, Z3.D, Z13.D

      (171) 0x41c370 FMAD	Z23.D, P0/M, Z2.D, Z13.D

      (171) 0x41c374 FMUL	Z23.D, Z23.D, Z25.D

      (171) 0x41c378 FMINNM	Z23.D, P0/M, Z23.D, Z14.D

      (171) 0x41c37c FMUL	Z21.D, Z21.D, Z23.D

      (171) 0x41c380 MUL	Z23.D, Z17.D, Z12.D

      (171) 0x41c384 CPY	Z21.D, P1/M, #0

      (171) 0x41c388 FADD	Z0.D, Z0.D, Z21.D

      (171) 0x41c38c MUL	Z21.D, Z16.D, Z31.D

      (171) 0x41c390 ADR	Z23.D, [Z27, Z23.D,LSL #3]

      (171) 0x41c394 FMUL	Z0.D, Z8.D, Z0.D

      (171) 0x41c398 MUL	Z8.D, Z17.D, Z11.D

      (171) 0x41c39c ADR	Z23.D, [Z23, Z30.D,SXTW #3]

      (171) 0x41c3a0 ADR	Z21.D, [Z26, Z21.D,LSL #3]

      (171) 0x41c3a4 ADR	Z21.D, [Z21, Z30.D,SXTW #3]

      (171) 0x41c3a8 ADR	Z8.D, [Z27, Z8.D,LSL #3]

      (171) 0x41c3ac ST1D	{Z0.D}, P0, [V21.D]

      (171) 0x41c3b0 MUL	Z21.D, Z17.D, Z15.D

      (171) 0x41c3b4 ADR	Z8.D, [Z8, Z30.D,SXTW #3]

      (171) 0x41c3b8 LD1D	{Z10.D}, P0/Z, [V10.D]

      (171) 0x41c3bc LD1D	{Z9.D}, P0/Z, [V9.D]

      (171) 0x41c3c0 LD1D	{Z23.D}, P0/Z, [V23.D]

      (171) 0x41c3c4 LD1D	{Z8.D}, P0/Z, [V8.D]

      (171) 0x41c3c8 ADR	Z21.D, [Z27, Z21.D,LSL #3]

      (171) 0x41c3cc ADR	Z21.D, [Z21, Z30.D,SXTW #3]

      (171) 0x41c3d0 LD1D	{Z21.D}, P0/Z, [V21.D]

      (171) 0x41c3d4 FMUL	Z9.D, Z10.D, Z9.D

      (171) 0x41c3d8 MOVPRFX	Z10, Z0

      (171) 0x41c3dc FABS	Z10.D, P0/M, Z0.D

      (171) 0x41c3e0 FDIVR	Z9.D, P0/M, Z9.D, Z10.D

      (171) 0x41c3e4 FSUB	Z12.D, Z8.D, Z21.D

      (171) 0x41c3e8 FABD	Z8.D, P0/M, Z8.D, Z21.D

      (171) 0x41c3ec FSUB	Z11.D, Z21.D, Z23.D

      (171) 0x41c3f0 FABD	Z23.D, P0/M, Z23.D, Z21.D

      (171) 0x41c3f4 FMUL	Z3.D, Z3.D, Z8.D

      (171) 0x41c3f8 FCMLE	P2.D, P0/Z, Z12.D, #0

      (171) 0x41c3fc FMUL	Z11.D, Z11.D, Z12.D

      (171) 0x41c400 EOR	P2.B, P0/Z, P2.B, P0.B

      (171) 0x41c404 FMAD	Z2.D, P0/M, Z23.D, Z3.D

      (171) 0x41c408 MOVPRFX	Z3, Z23

      (171) 0x41c40c FMINNM	Z3.D, P0/M, Z3.D, Z8.D

      (171) 0x41c410 FCMGT	P1.D, P0/Z, Z11.D, #0

      (171) 0x41c414 EOR	P1.B, P0/Z, P1.B, P0.B

      (171) 0x41c418 FMUL	Z2.D, Z2.D, Z25.D

      (171) 0x41c41c FSUBR	Z9.D, P0/M, Z9.D, #1

      (171) 0x41c420 MOVPRFX	Z10, Z9

      (171) 0x41c424 FNEG	Z10.D, P0/M, Z9.D

      (171) 0x41c428 FMINNM	Z2.D, P0/M, Z2.D, Z3.D

      (171) 0x41c42c SEL	Z9.D, P2, Z9.D, Z10.D

      (171) 0x41c430 FMUL	Z2.D, Z2.D, Z9.D

      (171) 0x41c434 CPY	Z2.D, P1/M, #0

      (171) 0x41c438 FADD	Z2.D, Z21.D, Z2.D

      (171) 0x41c43c FMUL	Z0.D, Z0.D, Z2.D

      (171) 0x41c440 MUL	Z2.D, Z18.D, Z31.D

      (171) 0x41c444 ADR	Z2.D, [Z28, Z2.D,LSL #3]

      (171) 0x41c448 ADR	Z2.D, [Z2, Z30.D,SXTW #3]

      (171) 0x41c44c ST1D	{Z0.D}, P0, [V2.D]

      (171) 0x41c450 LDR	Z0, [X19, #511, MUL VL]

      (171) 0x41c454 ADD	Z29.D, Z29.D, Z0.D

      (171) 0x41c458 CBNZ	X7, 41c240

    (172) 0x41c45c CMP	X5, X6

    (172) 0x41c460 B.EQ	41c118

  (170) 0x41c464 FMOV	D0, #1.0000000

  (170) 0x41c468 FMOV	D1, #2.0000000

  (170) 0x41c46c ORR	X6, XZR, #3840

  (170) 0x41c470 ADD	X4, X4, #1

  (170) 0x41c474 SUB	W5, WZR, W25

  (170) 0x41c478 MOVK	X6, #16325

  (170) 0x41c47c B	41c4a0

  (170) 0x41c480 FADD	D3, D6, D5

  (170) 0x41c484 MADD	X19, X2, X20, XZR

  (170) 0x41c488 ADD	X3, X3, #1

  (170) 0x41c48c FMUL	D2, D2, D3

  (170) 0x41c490 ADD	X19, X1, X19,LSL #3

  (170) 0x41c494 STR	D2, [X19, X7,SXTW #3]

  (170) 0x41c498 CMP	X4, X3

  (170) 0x41c49c B.EQ	41c118

  (170) 0x41c4a0 SDIV	X21, X3, X25

  (170) 0x41c4a4 ADD	W7, W24, W3

  (170) 0x41c4a8 ADD	W20, W23, W21

  (170) 0x41c4ac MADD	W7, W5, W21, W7

  (170) 0x41c4b0 SBFM	X20, X20, #0, #31

  (170) 0x41c4b4 MADD	X26, X9, X20, XZR

  (170) 0x41c4b8 ADD	X26, X8, X26,LSL #3

  (170) 0x41c4bc LDR	D2, [X26, X7,SXTW #3]

  (170) 0x41c4c0 FCMP	D2, #0

  (170) 0x41c4c4 B.LE	41c4e0

  (170) 0x41c4c8 ADD	W28, W22, W21

  (170) 0x41c4cc SUB	W30, W20, #2

  (170) 0x41c4d0 ORR	X21, XZR, X20

  (170) 0x41c4d4 SBFM	X27, X28, #0, #31

  (170) 0x41c4d8 B	41c4fc

0x41c4dc HINT	#0

(169) 0x41c4e0 ADD	W26, W20, #1

(169) 0x41c4e4 ADD	W21, W22, W21

(169) 0x41c4e8 ORR	X27, XZR, X20

(169) 0x41c4ec CMP	W10, W26

(169) 0x41c4f0 SBFM	X21, X21, #0, #31

(169) 0x41c4f4 CSINC	W28, W10, W20, #11

(169) 0x41c4f8 ORR	W30, WZR, W28

  (170) 0x41c4fc MADD	X26, X12, X27, XZR

  (170) 0x41c500 FABS	D3, D2

  (170) 0x41c504 LDR	D5, [X13, X28,SXTW #3]

  (170) 0x41c508 SBFM	X30, X30, #0, #31

  (170) 0x41c50c MADD	X28, X15, X27, XZR

  (170) 0x41c510 ADD	X26, X11, X26,LSL #3

  (170) 0x41c514 MADD	X19, X15, X30, XZR

  (170) 0x41c518 ADD	X28, X14, X28,LSL #3

  (170) 0x41c51c LDR	D4, [X26, X7,SXTW #3]

  (170) 0x41c520 ADD	X19, X14, X19,LSL #3

  (170) 0x41c524 LDR	D6, [X28, X7,SXTW #3]

  (170) 0x41c528 FDIV	D7, D3, D4

  (170) 0x41c52c LDR	D4, [X13, X20,LSL #3]

  (170) 0x41c530 FDIV	D4, D4, D5

  (170) 0x41c534 LDR	D5, [X19, X7,SXTW #3]

  (170) 0x41c538 MADD	X19, X15, X21, XZR

  (170) 0x41c53c ADD	X19, X14, X19,LSL #3

  (170) 0x41c540 FSUB	D16, D6, S5

  (170) 0x41c544 LDR	D5, [X19, X7,SXTW #3]

  (170) 0x41c548 FADD	D3, D7, D0

  (170) 0x41c54c FSUB	D17, D5, S6

  (170) 0x41c550 MOVI	D5, #0

  (170) 0x41c554 FMUL	D18, D16, D17

  (170) 0x41c558 FMUL	D3, D3, D4

  (170) 0x41c55c FSUB	D4, D1, S7

  (170) 0x41c560 FCMP	D18, #0

  (170) 0x41c564 MOVI	D18, #0

  (170) 0x41c568 B.LE	41c5a0

  (170) 0x41c56c FSUB	D7, D0, S7

  (170) 0x41c570 FCMP	D17, #0

  (170) 0x41c574 FABS	D16, D16

  (170) 0x41c578 FABS	D17, D17

  (170) 0x41c57c FNEG	D18, D7

  (170) 0x41c580 FCSEL	D7, D7, D18, #8

  (170) 0x41c584 FMINNM	D18, D16, D17

  (170) 0x41c588 FMUL	D17, D4, D17

  (170) 0x41c58c FMADD	D16, D3, D16, D17

  (170) 0x41c590 FMOV	D17, X6

  (170) 0x41c594 FMUL	D16, D16, D17

  (170) 0x41c598 FMINNM	D16, D18, D16

  (170) 0x41c59c FMUL	D18, D7, D16

  (170) 0x41c5a0 FADD	D6, D6, D18

  (170) 0x41c5a4 MADD	X19, X17, X20, XZR

  (170) 0x41c5a8 FMUL	D2, D2, D6

  (170) 0x41c5ac ADD	X19, X16, X19,LSL #3

  (170) 0x41c5b0 STR	D2, [X19, X7,SXTW #3]

  (170) 0x41c5b4 MADD	X19, X0, X27, XZR

  (170) 0x41c5b8 ADD	X19, X18, X19,LSL #3

  (170) 0x41c5bc LDR	D6, [X19, X7,SXTW #3]

  (170) 0x41c5c0 MADD	X19, X0, X30, XZR

  (170) 0x41c5c4 ADD	X19, X18, X19,LSL #3

  (170) 0x41c5c8 LDR	D7, [X19, X7,SXTW #3]

  (170) 0x41c5cc MADD	X19, X0, X21, XZR

  (170) 0x41c5d0 ADD	X19, X18, X19,LSL #3

  (170) 0x41c5d4 LDR	D16, [X19, X7,SXTW #3]

  (170) 0x41c5d8 FSUB	D7, D6, S7

  (170) 0x41c5dc FSUB	D16, D16, S6

  (170) 0x41c5e0 FMUL	D17, D7, D16

  (170) 0x41c5e4 FCMP	D17, #0

  (170) 0x41c5e8 B.LE	41c480

  (170) 0x41c5ec LDR	D17, [X28, X7,SXTW #3]

  (170) 0x41c5f0 LDR	D18, [X26, X7,SXTW #3]

  (170) 0x41c5f4 FABS	D5, D2

  (170) 0x41c5f8 FCMP	D16, #0

  (170) 0x41c5fc FABS	D16, D16

  (170) 0x41c600 FABS	D7, D7

  (170) 0x41c604 FMUL	D4, D4, D16

  (170) 0x41c608 FMADD	D3, D3, D7, D4

  (170) 0x41c60c FMOV	D4, X6

  (170) 0x41c610 FMUL	D17, D17, D18

  (170) 0x41c614 FMUL	D3, D3, D4

  (170) 0x41c618 FDIV	D5, D5, D17

  (170) 0x41c61c FSUB	D5, D0, S5

  (170) 0x41c620 FNEG	D17, D5

  (170) 0x41c624 FCSEL	D5, D5, D17, #8

  (170) 0x41c628 FMINNM	D17, D7, D16

  (170) 0x41c62c FMINNM	D3, D17, D3

  (170) 0x41c630 FMUL	D5, D3, D5

  (170) 0x41c634 B	41c480

0x41c638 HINT	#0

0x41c63c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.00 to 6.25 cycles (1.12x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00
cycles	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	11%
load	0%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
59% of peak store performance is reached (28.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c050

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB SP, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #61	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W27, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W24, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W27, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41c128 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W9, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c0c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W1, WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UMADDL X26, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X4, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41c15c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00
cycles	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	11%
load	0%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
59% of peak store performance is reached (28.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c050

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB SP, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #61	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W27, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W24, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W27, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41c128 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W9, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c0c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W1, WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UMADDL X26, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X4, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41c15c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.75	3.13
▼Loop 169 - context.h:69-69 - exec–	0.00	0.00
▼Loop 170 - advec_cell.cpp:157-202 - exec–	0.00	0.00
▼Loop 172 - advec_cell.cpp:157-202 - exec–	0.00	0.00
○Loop 171 - advec_cell.cpp:158-202 - exec	3.75	3.10

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code