OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:65-110 [...]	Coverage (incl. loops): 3.37% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 65 - 110

--------------------------------------------------------------------------------

65: #pragma omp parallel for simd collapse(2)

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41b1c0 STP	D15, D14, [SP, #864]!

0x41b1c4 STP	D13, D12, [SP, #16]

0x41b1c8 STP	D11, D10, [SP, #32]

0x41b1cc STP	D9, D8, [SP, #48]

0x41b1d0 STP	X29, X30, [SP, #64]

0x41b1d4 STP	X28, X27, [SP, #80]

0x41b1d8 STP	X26, X25, [SP, #96]

0x41b1dc STP	X24, X23, [SP, #112]

0x41b1e0 STP	X22, X21, [SP, #128]

0x41b1e4 STP	X20, X19, [SP, #144]

0x41b1e8 ADD	X29, SP, #64

0x41b1ec SUB	SP, SP, #48

0x41b1f0 ADDVL	SP, SP, #60

0x41b1f4 LDR	W8, [X2]

0x41b1f8 LDR	W23, [X4]

0x41b1fc LDR	W27, [X5]

0x41b200 ADD	W22, W8, #1

0x41b204 LDR	W8, [X3]

0x41b208 ADD	W25, W23, #1

0x41b20c ADD	W9, W27, #4

0x41b210 ADD	W8, W8, #2

0x41b214 SUBS	W8, W8, W22

0x41b218 CCMP	W9, W25, #4, #12

0x41b21c B.LE	41b298

0x41b220 LDR	W1, [X0]

0x41b224 SUB	W24, W9, W25

0x41b228 MOVN	X9, #0

0x41b22c ORR	X20, XZR, X7

0x41b230 ORR	X21, XZR, X6

0x41b234 ADRP	X0,

0x41b238 ADD	X0, X0, #3208

0x41b23c ADD	X3, SP, #20

0x41b240 ADD	X4, SP, #40

0x41b244 STP	W1, WZR, [SP, #16]

0x41b248 UMADDL	X26, W24, W8, X9

0x41b24c MOVZ	W8, #1

0x41b250 ADD	X5, SP, #32

0x41b254 ADD	X6, SP, #24

0x41b258 MOVZ	W2, #34

0x41b25c MOVZ	W7, #1

0x41b260 STP	X26, XZR, [SP, #32]

0x41b264 STR	X8, [SP, #24]

0x41b268 STR	X8, [SP]

0x41b26c BL	402e00

0x41b270 LDR	X8, [SP, #32]

0x41b274 CMP	X8, X26

0x41b278 CSEL	X4, X8, X26, #11

0x41b27c LDR	X26, [SP, #40]

0x41b280 CMP	X26, X4

0x41b284 B.LE	41b2cc

    (162) 0x41b288 LDR	W1, [SP, #16]

    (162) 0x41b28c ADRP	X0,

    (162) 0x41b290 ADD	X0, X0, #3232

    (162) 0x41b294 BL	402cc0

    (162) 0x41b298 ADDVL	SP, SP, #4

    (162) 0x41b29c ADD	SP, SP, #48

    (162) 0x41b2a0 LDP	D9, D8, [SP, #48]

    (162) 0x41b2a4 LDP	D11, D10, [SP, #32]

    (162) 0x41b2a8 LDP	D13, D12, [SP, #16]

    (162) 0x41b2ac LDP	X20, X19, [SP, #144]

    (162) 0x41b2b0 LDP	X22, X21, [SP, #128]

    (162) 0x41b2b4 LDP	X24, X23, [SP, #112]

    (162) 0x41b2b8 LDP	X26, X25, [SP, #96]

    (162) 0x41b2bc LDP	X28, X27, [SP, #80]

    (162) 0x41b2c0 LDP	X29, X30, [SP, #64]

    (162) 0x41b2c4 LDP	D15, D14, [SP], #160

    (162) 0x41b2c8 RET

    (162) 0x41b2cc LDP	X0, X2, [X29, #128]

    (162) 0x41b2d0 LDR	X17, [X29, #120]

    (162) 0x41b2d4 LDP	X13, X15, [X29, #96]

    (162) 0x41b2d8 SUB	X1, X4, X26

    (162) 0x41b2dc CNTD	X7, ALL

    (162) 0x41b2e0 ADD	W10, W27, #2

    (162) 0x41b2e4 ORR	X3, XZR, X26

    (162) 0x41b2e8 ADD	X5, X1, #1

    (162) 0x41b2ec LDR	X8, [X21, #16]

    (162) 0x41b2f0 LDR	X9, [X21]

    (162) 0x41b2f4 LDR	X11, [X20, #16]

    (162) 0x41b2f8 LDR	X12, [X20]

    (162) 0x41b2fc LDR	X13, [X13, #8]

    (162) 0x41b300 LDR	X14, [X15, #16]

    (162) 0x41b304 LDR	X15, [X15]

    (162) 0x41b308 LDR	X16, [X17, #16]

    (162) 0x41b30c LDR	X17, [X17]

    (162) 0x41b310 LDR	X18, [X0, #16]

    (162) 0x41b314 LDR	X0, [X0]

    (162) 0x41b318 LDR	X1, [X2, #16]

    (162) 0x41b31c LDR	X2, [X2]

    (162) 0x41b320 CMP	X5, X7

    (162) 0x41b324 B.CC	41b5b4

    (162) 0x41b328 DUP	Z0.D, X7

    (162) 0x41b32c SUB	X19, X29, #64

    (162) 0x41b330 SUB	X3, XZR, X7

    (162) 0x41b334 ORR	X7, XZR, #3840

    (162) 0x41b338 PTRUE	P0.D, ALL

    (162) 0x41b33c MOVK	X7, #16325

    (162) 0x41b340 INDEX	Z29.D, X26, #1

    (162) 0x41b344 AND	X6, X5, X3

    (162) 0x41b348 ADD	X3, X26, X6

    (162) 0x41b34c STR	Z0, [X19, #511, MUL VL]

    (162) 0x41b350 DUP	Z0.D, X22

    (162) 0x41b354 DUP	Z20.D, X10

    (162) 0x41b358 SXTW	Z20.D, P0/M, Z20.D

    (162) 0x41b35c STR	Z0, [X19, #510, MUL VL]

    (162) 0x41b360 DUP	Z0.D, X25

    (162) 0x41b364 DUP	Z1.D, X24

    (162) 0x41b368 STR	Z0, [X19, #509, MUL VL]

    (162) 0x41b36c DUP	Z0.D, X9

    (162) 0x41b370 DUP	Z5.D, X23

    (162) 0x41b374 DUP	Z6.D, X12

    (162) 0x41b378 STR	Z0, [X19, #508, MUL VL]

    (162) 0x41b37c DUP	Z7.D, X15

    (162) 0x41b380 DUP	Z16.D, X17

    (162) 0x41b384 DUP	Z17.D, X0

    (162) 0x41b388 DUP	Z18.D, X2

    (162) 0x41b38c DUP	Z19.D, X8

    (162) 0x41b390 DUP	Z22.D, X11

    (162) 0x41b394 DUP	Z24.D, X14

    (162) 0x41b398 DUP	Z25.D, X7

    (162) 0x41b39c ORR	X7, XZR, X6

    (162) 0x41b3a0 DUP	Z26.D, X16

    (162) 0x41b3a4 DUP	Z27.D, X18

    (162) 0x41b3a8 DUP	Z28.D, X1

      (161) 0x41b3ac MOVPRFX	Z30, Z29

      (161) 0x41b3b0 SDIV	Z30.D, P0/M, Z30.D, Z1.D

      (161) 0x41b3b4 SUB	X19, X29, #64

      (161) 0x41b3b8 DECD	X7, ALL

      (161) 0x41b3bc LDR	Z0, [X19, #510, MUL VL]

      (161) 0x41b3c0 ADD	Z31.D, Z0.D, Z30.D

      (161) 0x41b3c4 LDR	Z0, [X19, #509, MUL VL]

      (161) 0x41b3c8 MOVPRFX	Z8, Z29

      (161) 0x41b3cc MLS	Z8.D, P0/M, Z30.D, Z1.D

      (161) 0x41b3d0 SXTW	Z31.D, P0/M, Z31.D

      (161) 0x41b3d4 ADD	Z30.D, Z0.D, Z8.D

      (161) 0x41b3d8 LDR	Z0, [X19, #508, MUL VL]

      (161) 0x41b3dc ADD	Z8.D, Z5.D, Z8.D

      (161) 0x41b3e0 ORR	Z11.D, Z30.D, Z30.D

      (161) 0x41b3e4 MOVPRFX	Z14, Z8

      (161) 0x41b3e8 SXTW	Z14.D, P0/M, Z8.D

      (161) 0x41b3ec MOVPRFX	Z10, Z30

      (161) 0x41b3f0 SXTW	Z10.D, P0/M, Z30.D

      (161) 0x41b3f4 ADD	Z11.D, Z11.D, #1

      (161) 0x41b3f8 SXTW	Z11.D, P0/M, Z11.D

      (161) 0x41b3fc MUL	Z9.D, Z0.D, Z31.D

      (161) 0x41b400 DUPM	Z0.D, #4294967294

      (161) 0x41b404 LD1D	{Z12.D}, P0/Z, [X13, Z30.D,SXTW #3]

      (161) 0x41b408 SMIN	Z11.D, P0/M, Z11.D, Z20.D

      (161) 0x41b40c ADR	Z9.D, [Z19, Z9.D,LSL #3]

      (161) 0x41b410 ADR	Z9.D, [Z9, Z30.D,SXTW #3]

      (161) 0x41b414 LD1D	{Z13.D}, P0/Z, [V9.D]

      (161) 0x41b418 ADD	Z9.D, Z30.D, Z0.D

      (161) 0x41b41c MOVPRFX	Z8, Z9

      (161) 0x41b420 SXTW	Z8.D, P0/M, Z9.D

      (161) 0x41b424 FCMGT	P1.D, P0/Z, Z13.D, #0

      (161) 0x41b428 SEL	Z15.D, P1, Z8.D, Z11.D

      (161) 0x41b42c MUL	Z8.D, Z6.D, Z31.D

      (161) 0x41b430 SEL	Z21.D, P1, Z14.D, Z10.D

      (161) 0x41b434 SEL	Z11.D, P1, Z14.D, Z11.D

      (161) 0x41b438 SEL	Z9.D, P1, Z10.D, Z14.D

      (161) 0x41b43c MOVPRFX	Z14, Z13

      (161) 0x41b440 FABS	Z14.D, P0/M, Z13.D

      (161) 0x41b444 LD1D	{Z23.D}, P0/Z, [X13, Z11.D,LSL #3]

      (161) 0x41b448 ADR	Z8.D, [Z22, Z8.D,LSL #3]

      (161) 0x41b44c MUL	Z11.D, Z7.D, Z31.D

      (161) 0x41b450 ADR	Z8.D, [Z8, Z21.D,LSL #3]

      (161) 0x41b454 ADR	Z0.D, [Z24, Z11.D,LSL #3]

      (161) 0x41b458 LD1D	{Z10.D}, P0/Z, [V8.D]

      (161) 0x41b45c ADR	Z11.D, [Z0, Z21.D,LSL #3]

      (161) 0x41b460 LD1D	{Z2.D}, P0/Z, [V11.D]

      (161) 0x41b464 FDIVR	Z23.D, P0/M, Z23.D, Z12.D

      (161) 0x41b468 ADR	Z12.D, [Z0, Z15.D,LSL #3]

      (161) 0x41b46c ADR	Z0.D, [Z0, Z9.D,LSL #3]

      (161) 0x41b470 LD1D	{Z3.D}, P0/Z, [V12.D]

      (161) 0x41b474 LD1D	{Z0.D}, P0/Z, [V0.D]

      (161) 0x41b478 FDIV	Z14.D, P0/M, Z14.D, Z10.D

      (161) 0x41b47c FSUB	Z4.D, Z0.D, Z2.D

      (161) 0x41b480 FABD	Z0.D, P0/M, Z0.D, Z2.D

      (161) 0x41b484 FCMLE	P2.D, P0/Z, Z4.D, #0

      (161) 0x41b488 EOR	P2.B, P0/Z, P2.B, P0.B

      (161) 0x41b48c MOVPRFX	Z10, Z14

      (161) 0x41b490 FADD	Z10.D, P0/M, Z10.D, #1

      (161) 0x41b494 FMUL	Z10.D, Z10.D, Z23.D

      (161) 0x41b498 FSUB	Z23.D, Z2.D, Z3.D

      (161) 0x41b49c FABD	Z3.D, P0/M, Z3.D, Z2.D

      (161) 0x41b4a0 FMUL	Z23.D, Z23.D, Z4.D

      (161) 0x41b4a4 MOVPRFX	Z4, Z14

      (161) 0x41b4a8 FSUBR	Z4.D, P0/M, Z4.D, #1

      (161) 0x41b4ac FCMGT	P1.D, P0/Z, Z23.D, #0

      (161) 0x41b4b0 FDUP	Z23.D, #0

      (161) 0x41b4b4 FSUB	Z12.D, Z23.D, Z14.D

      (161) 0x41b4b8 MOVPRFX	Z23, Z4

      (161) 0x41b4bc FNEG	Z23.D, P0/M, Z4.D

      (161) 0x41b4c0 EOR	P1.B, P0/Z, P1.B, P0.B

      (161) 0x41b4c4 SEL	Z4.D, P2, Z4.D, Z23.D

      (161) 0x41b4c8 MOVPRFX	Z23, Z3

      (161) 0x41b4cc FMINNM	Z23.D, P0/M, Z23.D, Z0.D

      (161) 0x41b4d0 FMUL	Z0.D, Z12.D, Z0.D

      (161) 0x41b4d4 FMLA	Z0.D, P0/M, Z10.D, Z3.D

      (161) 0x41b4d8 FMUL	Z0.D, Z0.D, Z25.D

      (161) 0x41b4dc FMINNM	Z0.D, P0/M, Z0.D, Z23.D

      (161) 0x41b4e0 FMUL	Z0.D, Z4.D, Z0.D

      (161) 0x41b4e4 MUL	Z4.D, Z18.D, Z31.D

      (161) 0x41b4e8 CPY	Z0.D, P1/M, #0

      (161) 0x41b4ec FADD	Z0.D, Z2.D, Z0.D

      (161) 0x41b4f0 ADR	Z4.D, [Z28, Z4.D,LSL #3]

      (161) 0x41b4f4 FMUL	Z13.D, Z13.D, Z0.D

      (161) 0x41b4f8 MUL	Z0.D, Z16.D, Z31.D

      (161) 0x41b4fc ADR	Z4.D, [Z4, Z30.D,SXTW #3]

      (161) 0x41b500 ADR	Z0.D, [Z26, Z0.D,LSL #3]

      (161) 0x41b504 ADR	Z0.D, [Z0, Z30.D,SXTW #3]

      (161) 0x41b508 ST1D	{Z13.D}, P0, [V0.D]

      (161) 0x41b50c MUL	Z0.D, Z17.D, Z31.D

      (161) 0x41b510 LD1D	{Z30.D}, P0/Z, [V11.D]

      (161) 0x41b514 ADR	Z0.D, [Z27, Z0.D,LSL #3]

      (161) 0x41b518 ADR	Z2.D, [Z0, Z21.D,LSL #3]

      (161) 0x41b51c ADR	Z3.D, [Z0, Z15.D,LSL #3]

      (161) 0x41b520 ADR	Z0.D, [Z0, Z9.D,LSL #3]

      (161) 0x41b524 LD1D	{Z2.D}, P0/Z, [V2.D]

      (161) 0x41b528 LD1D	{Z3.D}, P0/Z, [V3.D]

      (161) 0x41b52c LD1D	{Z0.D}, P0/Z, [V0.D]

      (161) 0x41b530 FSUB	Z21.D, Z2.D, Z3.D

      (161) 0x41b534 FSUB	Z23.D, Z0.D, Z2.D

      (161) 0x41b538 FABD	Z0.D, P0/M, Z0.D, Z2.D

      (161) 0x41b53c FABD	Z3.D, P0/M, Z3.D, Z2.D

      (161) 0x41b540 FMUL	Z21.D, Z21.D, Z23.D

      (161) 0x41b544 FCMLE	P2.D, P0/Z, Z23.D, #0

      (161) 0x41b548 MOVPRFX	Z23, Z13

      (161) 0x41b54c FABS	Z23.D, P0/M, Z13.D

      (161) 0x41b550 EOR	P2.B, P0/Z, P2.B, P0.B

      (161) 0x41b554 FCMGT	P1.D, P0/Z, Z21.D, #0

      (161) 0x41b558 LD1D	{Z21.D}, P0/Z, [V8.D]

      (161) 0x41b55c EOR	P1.B, P0/Z, P1.B, P0.B

      (161) 0x41b560 FMUL	Z21.D, Z30.D, Z21.D

      (161) 0x41b564 FDIVR	Z21.D, P0/M, Z21.D, Z23.D

      (161) 0x41b568 FSUBR	Z21.D, P0/M, Z21.D, #1

      (161) 0x41b56c MOVPRFX	Z23, Z21

      (161) 0x41b570 FNEG	Z23.D, P0/M, Z21.D

      (161) 0x41b574 SEL	Z21.D, P2, Z21.D, Z23.D

      (161) 0x41b578 FMUL	Z23.D, Z12.D, Z0.D

      (161) 0x41b57c FMINNM	Z0.D, P0/M, Z0.D, Z3.D

      (161) 0x41b580 FMLA	Z23.D, P0/M, Z10.D, Z3.D

      (161) 0x41b584 FMUL	Z3.D, Z23.D, Z25.D

      (161) 0x41b588 FMINNM	Z0.D, P0/M, Z0.D, Z3.D

      (161) 0x41b58c FMUL	Z0.D, Z0.D, Z21.D

      (161) 0x41b590 CPY	Z0.D, P1/M, #0

      (161) 0x41b594 FADD	Z0.D, Z2.D, Z0.D

      (161) 0x41b598 FMUL	Z0.D, Z13.D, Z0.D

      (161) 0x41b59c ST1D	{Z0.D}, P0, [V4.D]

      (161) 0x41b5a0 LDR	Z0, [X19, #511, MUL VL]

      (161) 0x41b5a4 ADD	Z29.D, Z29.D, Z0.D

      (161) 0x41b5a8 CBNZ	X7, 41b3ac

    (162) 0x41b5ac CMP	X5, X6

    (162) 0x41b5b0 B.EQ	41b288

  (160) 0x41b5b4 FMOV	D0, #1.0000000

  (160) 0x41b5b8 FMOV	D1, #2.0000000

  (160) 0x41b5bc ORR	X7, XZR, #3840

  (160) 0x41b5c0 ADD	X4, X4, #1

  (160) 0x41b5c4 SUB	W5, WZR, W24

  (160) 0x41b5c8 SUB	W6, W23, #1

  (160) 0x41b5cc MOVK	X7, #16325

  (160) 0x41b5d0 B	41b600

0x41b5d4 HINT	#0

0x41b5d8 HINT	#0

0x41b5dc HINT	#0

  (160) 0x41b5e0 FADD	D3, D6, D5

  (160) 0x41b5e4 MADD	X19, X2, X21, XZR

  (160) 0x41b5e8 ADD	X3, X3, #1

  (160) 0x41b5ec FMUL	D2, D2, D3

  (160) 0x41b5f0 ADD	X19, X1, X19,LSL #3

  (160) 0x41b5f4 STR	D2, [X19, X20,LSL #3]

  (160) 0x41b5f8 CMP	X4, X3

  (160) 0x41b5fc B.EQ	41b288

  (160) 0x41b600 SDIV	X25, X3, X24

  (160) 0x41b604 ADD	W20, W23, W3

  (160) 0x41b608 ADD	W21, W22, W25

  (160) 0x41b60c MADD	W20, W5, W25, W20

  (160) 0x41b610 SBFM	X21, X21, #0, #31

  (160) 0x41b614 MADD	X27, X9, X21, XZR

  (160) 0x41b618 ADD	W26, W20, #1

  (160) 0x41b61c SBFM	X20, X26, #0, #31

  (160) 0x41b620 ADD	X27, X8, X27,LSL #3

  (160) 0x41b624 LDR	D2, [X27, X26,SXTW #3]

  (160) 0x41b628 FCMP	D2, #0

  (160) 0x41b62c B.LE	41b660

  (160) 0x41b630 ADD	W26, W6, W3

  (160) 0x41b634 ADD	W27, W23, W3

  (160) 0x41b638 MADD	W26, W5, W25, W26

  (160) 0x41b63c MADD	W25, W5, W25, W27

  (160) 0x41b640 ORR	X27, XZR, X20

  (160) 0x41b644 SBFM	X30, X25, #0, #31

  (160) 0x41b648 SBFM	X26, X26, #0, #31

  (160) 0x41b64c ORR	X25, XZR, X30

  (160) 0x41b650 B	41b684

0x41b654 HINT	#0

0x41b658 HINT	#0

0x41b65c HINT	#0

(159) 0x41b660 ADD	W26, W23, W3

(159) 0x41b664 MADD	W25, W5, W25, W26

(159) 0x41b668 ADD	W26, W25, #2

(159) 0x41b66c SBFM	X27, X25, #0, #31

(159) 0x41b670 ORR	X25, XZR, X20

(159) 0x41b674 CMP	W10, W26

(159) 0x41b678 CSEL	W26, W10, W26, #11

(159) 0x41b67c SBFM	X26, X26, #0, #31

(159) 0x41b680 ORR	X30, XZR, X26

  (160) 0x41b684 MADD	X28, X12, X21, XZR

  (160) 0x41b688 FABS	D3, D2

  (160) 0x41b68c LDR	D5, [X13, X30,LSL #3]

  (160) 0x41b690 MADD	X30, X15, X21, XZR

  (160) 0x41b694 ADD	X28, X11, X28,LSL #3

  (160) 0x41b698 ADD	X30, X14, X30,LSL #3

  (160) 0x41b69c LDR	D4, [X28, X25,LSL #3]

  (160) 0x41b6a0 LDR	D6, [X30, X25,LSL #3]

  (160) 0x41b6a4 FDIV	D7, D3, D4

  (160) 0x41b6a8 LDR	D4, [X13, X20,LSL #3]

  (160) 0x41b6ac FDIV	D4, D4, D5

  (160) 0x41b6b0 LDR	D5, [X30, X26,LSL #3]

  (160) 0x41b6b4 FSUB	D16, D6, S5

  (160) 0x41b6b8 LDR	D5, [X30, X27,LSL #3]

  (160) 0x41b6bc FADD	D3, D7, D0

  (160) 0x41b6c0 FSUB	D17, D5, S6

  (160) 0x41b6c4 MOVI	D5, #0

  (160) 0x41b6c8 FMUL	D18, D16, D17

  (160) 0x41b6cc FMUL	D3, D3, D4

  (160) 0x41b6d0 FSUB	D4, D1, S7

  (160) 0x41b6d4 FCMP	D18, #0

  (160) 0x41b6d8 MOVI	D18, #0

  (160) 0x41b6dc B.LE	41b714

  (160) 0x41b6e0 FSUB	D7, D0, S7

  (160) 0x41b6e4 FCMP	D17, #0

  (160) 0x41b6e8 FABS	D16, D16

  (160) 0x41b6ec FABS	D17, D17

  (160) 0x41b6f0 FNEG	D18, D7

  (160) 0x41b6f4 FCSEL	D7, D7, D18, #8

  (160) 0x41b6f8 FMINNM	D18, D16, D17

  (160) 0x41b6fc FMUL	D17, D4, D17

  (160) 0x41b700 FMADD	D16, D3, D16, D17

  (160) 0x41b704 FMOV	D17, X7

  (160) 0x41b708 FMUL	D16, D16, D17

  (160) 0x41b70c FMINNM	D16, D18, D16

  (160) 0x41b710 FMUL	D18, D7, D16

  (160) 0x41b714 FADD	D6, D6, D18

  (160) 0x41b718 MADD	X19, X17, X21, XZR

  (160) 0x41b71c FMUL	D2, D2, D6

  (160) 0x41b720 ADD	X19, X16, X19,LSL #3

  (160) 0x41b724 STR	D2, [X19, X20,LSL #3]

  (160) 0x41b728 MADD	X19, X0, X21, XZR

  (160) 0x41b72c ADD	X19, X18, X19,LSL #3

  (160) 0x41b730 LDR	D6, [X19, X25,LSL #3]

  (160) 0x41b734 LDR	D7, [X19, X26,LSL #3]

  (160) 0x41b738 LDR	D16, [X19, X27,LSL #3]

  (160) 0x41b73c FSUB	D7, D6, S7

  (160) 0x41b740 FSUB	D16, D16, S6

  (160) 0x41b744 FMUL	D17, D7, D16

  (160) 0x41b748 FCMP	D17, #0

  (160) 0x41b74c B.LE	41b5e0

  (160) 0x41b750 LDR	D17, [X30, X25,LSL #3]

  (160) 0x41b754 LDR	D18, [X28, X25,LSL #3]

  (160) 0x41b758 FABS	D5, D2

  (160) 0x41b75c FCMP	D16, #0

  (160) 0x41b760 FABS	D16, D16

  (160) 0x41b764 FABS	D7, D7

  (160) 0x41b768 FMUL	D4, D4, D16

  (160) 0x41b76c FMADD	D3, D3, D7, D4

  (160) 0x41b770 FMOV	D4, X7

  (160) 0x41b774 FMUL	D17, D17, D18

  (160) 0x41b778 FMUL	D3, D3, D4

  (160) 0x41b77c FDIV	D5, D5, D17

  (160) 0x41b780 FSUB	D5, D0, S5

  (160) 0x41b784 FNEG	D17, D5

  (160) 0x41b788 FCSEL	D5, D5, D17, #8

  (160) 0x41b78c FMINNM	D17, D7, D16

  (160) 0x41b790 FMINNM	D3, D17, D3

  (160) 0x41b794 FMUL	D5, D3, D5

  (160) 0x41b798 B	41b5e0

0x41b79c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.00 to 6.25 cycles (1.12x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00
cycles	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	11%
load	0%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
59% of peak store performance is reached (28.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41b1c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB SP, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #60	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W27, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W25, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W27, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W25, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41b298 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c234>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W1, WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UMADDL X26, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X4, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41b2cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	57
loop length	228
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00
cycles	1.50	1.50	4.67	4.67	4.67	4.67	4.67	4.67	2.00	2.00	0.00	0.00	7.00	7.00	7.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	11%
load	0%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
59% of peak store performance is reached (28.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41b1c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB SP, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #60	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W27, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W25, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W27, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W25, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41b298 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W24, W9, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46c234>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W1, WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UMADDL X26, W24, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X26, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X4, X8, X26, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 41b2cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.37	2.81
▼Loop 159 - context.h:69-69 - exec–	0.00	0.00
▼Loop 160 - advec_cell.cpp:65-110 - exec–	0.00	0.00
▼Loop 162 - advec_cell.cpp:65-110 - exec–	0.00	0.00
○Loop 161 - advec_cell.cpp:66-110 - exec	3.37	2.79

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code