OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 5.88% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x41a140 STP	D15, D14, [SP, #864]!

0x41a144 STP	D13, D12, [SP, #16]

0x41a148 STP	D11, D10, [SP, #32]

0x41a14c STP	D9, D8, [SP, #48]

0x41a150 STP	X29, X30, [SP, #64]

0x41a154 STP	X28, X27, [SP, #80]

0x41a158 STP	X26, X25, [SP, #96]

0x41a15c STP	X24, X23, [SP, #112]

0x41a160 STP	X22, X21, [SP, #128]

0x41a164 STP	X20, X19, [SP, #144]

0x41a168 ADD	X29, SP, #64

0x41a16c SUB	SP, SP, #144

0x41a170 ADDVL	SP, SP, #54

0x41a174 LDR	W23, [X2]

0x41a178 LDR	W8, [X3]

0x41a17c LDR	W19, [X4]

0x41a180 ADD	W24, W23, #1

0x41a184 LDR	W9, [X5]

0x41a188 ADD	W8, W8, #3

0x41a18c ADD	W28, W19, #1

0x41a190 ADD	W9, W9, #3

0x41a194 SUBS	W8, W8, W24

0x41a198 CCMP	W9, W28, #4, #12

0x41a19c B.LE	41a87c

0x41a1a0 LDR	W1, [X0]

0x41a1a4 SUB	W25, W9, W28

0x41a1a8 MOVN	X9, #0

0x41a1ac ORR	X21, XZR, X7

0x41a1b0 ADRP	X0,

0x41a1b4 ADD	X0, X0, #2992

0x41a1b8 ADD	X3, SP, #116

0x41a1bc ADD	X4, SP, #136

0x41a1c0 STP	X6, X23, [SP, #72]

0x41a1c4 STR	WZR, [SP, #116]

0x41a1c8 STP	X19, X24, [SP, #88]

0x41a1cc ADD	X5, SP, #128

0x41a1d0 ADD	X6, SP, #120

0x41a1d4 UMADDL	X20, W25, W8, X9

0x41a1d8 MOVZ	W8, #1

0x41a1dc MOVZ	W2, #34

0x41a1e0 MOVZ	W7, #1

0x41a1e4 STR	X8, [SP, #120]

0x41a1e8 STR	X8, [SP]

0x41a1ec STP	X20, XZR, [SP, #128]

0x41a1f0 STR	W1, [SP, #36]

0x41a1f4 BL	402e00

0x41a1f8 LDR	X8, [SP, #128]

0x41a1fc CMP	X8, X20

0x41a200 CSEL	X27, X8, X20, #11

0x41a204 LDR	X20, [SP, #136]

0x41a208 CMP	X20, X27

0x41a20c B.GT	41a86c

0x41a210 LDP	X6, X2, [X29, #136]

0x41a214 STR	X25, [SP, #104]

0x41a218 LDP	X12, X25, [X29, #152]

0x41a21c ORR	X26, XZR, X20

0x41a220 LDP	X15, X17, [X29, #120]

0x41a224 LDP	X0, X13, [X29, #104]

0x41a228 LDR	X8, [X29, #96]

0x41a22c LDR	X1, [X21]

0x41a230 LDR	X9, [X21, #16]

0x41a234 LDR	X10, [X2, #16]

0x41a238 LDR	X11, [X8, #16]

0x41a23c LDR	X14, [X8]

0x41a240 LDR	X3, [X13, #16]

0x41a244 LDR	X4, [X13]

0x41a248 LDR	X8, [X15, #16]

0x41a24c LDR	X15, [X15]

0x41a250 LDR	X16, [X17, #16]

0x41a254 LDR	X17, [X17]

0x41a258 LDR	X5, [X0, #16]

0x41a25c LDR	X7, [X0]

0x41a260 LDR	X24, [X2]

0x41a264 LDR	X19, [X12, #16]

0x41a268 LDR	X22, [X12]

0x41a26c SUB	X12, X27, X20

0x41a270 ADD	X2, X12, #1

0x41a274 CNTD	X12, ALL

0x41a278 LDR	X13, [X6]

0x41a27c LDR	X21, [X25]

0x41a280 LDR	X0, [SP, #104]

0x41a284 STP	X10, X1, [SP, #56]

0x41a288 LDR	X10, [X6, #16]

0x41a28c LDR	X6, [X25, #16]

0x41a290 STR	X13, [SP, #48]

0x41a294 CMP	X2, X12

0x41a298 B.CC	41a620

0x41a29c DUP	Z0.D, X12

0x41a2a0 SUB	X25, XZR, X12

0x41a2a4 SUB	X12, X29, #64

0x41a2a8 STR	X14, [SP, #24]

0x41a2ac LDR	X0, [SP, #104]

0x41a2b0 PTRUE	P0.D, ALL

0x41a2b4 STR	X24, [SP, #40]

0x41a2b8 AND	X18, X2, X25

0x41a2bc DUP	Z7.D, X14

0x41a2c0 SUB	X14, X29, #64

0x41a2c4 ORR	X25, XZR, X11

0x41a2c8 ADD	X26, X20, X18

0x41a2cc DUP	Z6.D, X1

0x41a2d0 ORR	X1, XZR, X9

0x41a2d4 STR	Z0, [X12, #511, MUL VL]

0x41a2d8 LDR	X12, [SP, #96]

0x41a2dc DUP	Z24.D, X9

0x41a2e0 ORR	X9, XZR, X18

0x41a2e4 ORR	X18, XZR, X8

0x41a2e8 ORR	X30, XZR, X9

0x41a2ec DUP	Z28.D, X8

0x41a2f0 LDR	X8, [SP, #56]

0x41a2f4 DUP	Z17.D, X15

0x41a2f8 DUP	Z18.D, X17

0x41a2fc DUP	Z23.D, X21

0x41a300 DUP	Z25.D, X11

0x41a304 DUP	Z27.D, X3

0x41a308 DUP	Z29.D, X16

0x41a30c DUP	Z30.D, X5

0x41a310 DUP	Z8.D, X19

0x41a314 DUP	Z9.D, X10

0x41a318 DUP	Z10.D, X6

0x41a31c DUP	Z1.D, X0

0x41a320 DUP	Z31.D, X8

0x41a324 LDR	X8, [SP, #72]

0x41a328 DUP	Z0.D, X12

0x41a32c SUB	X12, X29, #64

0x41a330 STR	Z0, [X12, #510, MUL VL]

0x41a334 DUP	Z0.D, X28

0x41a338 ORR	X28, XZR, X19

0x41a33c STR	Z0, [X12, #509, MUL VL]

0x41a340 LDR	X12, [SP, #88]

0x41a344 DUP	Z0.D, X12

0x41a348 SUB	X12, X29, #64

0x41a34c STR	Z0, [X12, #508, MUL VL]

0x41a350 LDR	X12, [SP, #80]

0x41a354 INDEX	Z11.D, X20, #1

0x41a358 DUP	Z0.D, X12

0x41a35c SUB	X12, X29, #64

0x41a360 STR	Z0, [X12, #507, MUL VL]

0x41a364 DUP	Z0.D, X4

0x41a368 STR	Z0, [X12, #506, MUL VL]

0x41a36c DUP	Z0.D, X7

0x41a370 ORR	X12, XZR, X7

0x41a374 STR	Z0, [X14, #505, MUL VL]

0x41a378 DUP	Z0.D, X24

0x41a37c STR	Z0, [X14, #504, MUL VL]

0x41a380 DUP	Z0.D, X22

0x41a384 ORR	X14, XZR, X22

0x41a388 SUB	X22, X29, #64

0x41a38c STR	Z0, [X22, #503, MUL VL]

0x41a390 DUP	Z0.D, X13

0x41a394 SUB	X13, X29, #64

0x41a398 STR	Z0, [X13, #502, MUL VL]

0x41a39c ORR	X13, XZR, X10

(153) 0x41a3a0 MOVPRFX	Z0, Z11

(153) 0x41a3a4 SDIV	Z0.D, P0/M, Z0.D, Z1.D

(153) 0x41a3a8 SUB	X10, X29, #64

(153) 0x41a3ac DECD	X30, ALL

(153) 0x41a3b0 LDR	Z2, [X10, #508, MUL VL]

(153) 0x41a3b4 LDR	Z4, [X10, #510, MUL VL]

(153) 0x41a3b8 LDR	Z21, [X10, #509, MUL VL]

(153) 0x41a3bc MOVPRFX	Z26, Z11

(153) 0x41a3c0 MLS	Z26.D, P0/M, Z0.D, Z1.D

(153) 0x41a3c4 ADD	Z12.D, Z2.D, Z26.D

(153) 0x41a3c8 LDR	Z2, [X10, #507, MUL VL]

(153) 0x41a3cc ADD	Z13.D, Z2.D, Z0.D

(153) 0x41a3d0 ADD	Z0.D, Z4.D, Z0.D

(153) 0x41a3d4 SXTW	Z13.D, P0/M, Z13.D

(153) 0x41a3d8 MUL	Z14.D, Z6.D, Z13.D

(153) 0x41a3dc MUL	Z15.D, Z7.D, Z13.D

(153) 0x41a3e0 ADR	Z2.D, [Z24, Z14.D,LSL #3]

(153) 0x41a3e4 ADR	Z5.D, [Z25, Z15.D,LSL #3]

(153) 0x41a3e8 ADR	Z14.D, [Z2, Z12.D,SXTW #3]

(153) 0x41a3ec ADR	Z15.D, [Z5, Z12.D,SXTW #3]

(153) 0x41a3f0 LD1D	{Z3.D}, P0/Z, [V14.D]

(153) 0x41a3f4 MOVPRFX	Z14, Z0

(153) 0x41a3f8 SXTW	Z14.D, P0/M, Z0.D

(153) 0x41a3fc LD1D	{Z20.D}, P0/Z, [V15.D]

(153) 0x41a400 ADD	Z15.D, Z21.D, Z26.D

(153) 0x41a404 MUL	Z0.D, Z6.D, Z14.D

(153) 0x41a408 MUL	Z16.D, Z7.D, Z14.D

(153) 0x41a40c ADR	Z2.D, [Z2, Z15.D,SXTW #3]

(153) 0x41a410 ADR	Z5.D, [Z5, Z15.D,SXTW #3]

(153) 0x41a414 LD1D	{Z2.D}, P0/Z, [V2.D]

(153) 0x41a418 LD1D	{Z5.D}, P0/Z, [V5.D]

(153) 0x41a41c ADR	Z0.D, [Z24, Z0.D,LSL #3]

(153) 0x41a420 ADR	Z16.D, [Z25, Z16.D,LSL #3]

(153) 0x41a424 ADR	Z4.D, [Z0, Z12.D,SXTW #3]

(153) 0x41a428 ADR	Z19.D, [Z16, Z12.D,SXTW #3]

(153) 0x41a42c ADR	Z0.D, [Z0, Z15.D,SXTW #3]

(153) 0x41a430 ADR	Z16.D, [Z16, Z15.D,SXTW #3]

(153) 0x41a434 LD1D	{Z4.D}, P0/Z, [V4.D]

(153) 0x41a438 LD1D	{Z19.D}, P0/Z, [V19.D]

(153) 0x41a43c LD1D	{Z0.D}, P0/Z, [V0.D]

(153) 0x41a440 LD1D	{Z16.D}, P0/Z, [V16.D]

(153) 0x41a444 FMUL	Z4.D, Z4.D, Z19.D

(153) 0x41a448 MUL	Z19.D, Z17.D, Z14.D

(153) 0x41a44c FMAD	Z3.D, P0/M, Z20.D, Z4.D

(153) 0x41a450 LDR	Z4, [X10, #506, MUL VL]

(153) 0x41a454 ADR	Z19.D, [Z28, Z19.D,LSL #3]

(153) 0x41a458 FMAD	Z0.D, P0/M, Z16.D, Z3.D

(153) 0x41a45c MUL	Z3.D, Z18.D, Z14.D

(153) 0x41a460 ADR	Z26.D, [Z19, Z15.D,SXTW #3]

(153) 0x41a464 FMLA	Z0.D, P0/M, Z2.D, Z5.D

(153) 0x41a468 MUL	Z2.D, Z18.D, Z13.D

(153) 0x41a46c MUL	Z4.D, Z4.D, Z14.D

(153) 0x41a470 ADR	Z3.D, [Z29, Z3.D,LSL #3]

(153) 0x41a474 ADR	Z16.D, [Z3, Z15.D,SXTW #3]

(153) 0x41a478 ADR	Z3.D, [Z3, Z12.D,SXTW #3]

(153) 0x41a47c ADR	Z2.D, [Z29, Z2.D,LSL #3]

(153) 0x41a480 ADR	Z4.D, [Z27, Z4.D,LSL #3]

(153) 0x41a484 ADR	Z5.D, [Z2, Z15.D,SXTW #3]

(153) 0x41a488 ADR	Z2.D, [Z2, Z12.D,SXTW #3]

(153) 0x41a48c LD1D	{Z19.D}, P0/Z, [V16.D]

(153) 0x41a490 LD1D	{Z20.D}, P0/Z, [V3.D]

(153) 0x41a494 ADR	Z4.D, [Z4, Z15.D,SXTW #3]

(153) 0x41a498 LD1D	{Z21.D}, P0/Z, [V5.D]

(153) 0x41a49c LD1D	{Z22.D}, P0/Z, [V2.D]

(153) 0x41a4a0 LD1D	{Z4.D}, P0/Z, [V4.D]

(153) 0x41a4a4 FSUB	Z19.D, Z19.D, Z20.D

(153) 0x41a4a8 MUL	Z20.D, Z17.D, Z13.D

(153) 0x41a4ac MUL	Z13.D, Z23.D, Z13.D

(153) 0x41a4b0 FSUB	Z21.D, Z21.D, Z22.D

(153) 0x41a4b4 ADR	Z20.D, [Z28, Z20.D,LSL #3]

(153) 0x41a4b8 ADR	Z13.D, [Z10, Z13.D,LSL #3]

(153) 0x41a4bc ADR	Z20.D, [Z20, Z15.D,SXTW #3]

(153) 0x41a4c0 LD1D	{Z22.D}, P0/Z, [V20.D]

(153) 0x41a4c4 FMUL	Z21.D, Z22.D, Z21.D

(153) 0x41a4c8 LD1D	{Z22.D}, P0/Z, [V26.D]

(153) 0x41a4cc FMAD	Z19.D, P0/M, Z22.D, Z21.D

(153) 0x41a4d0 LD1RD	{Z21.D}, P0/Z, [X8]

(153) 0x41a4d4 FDUP	Z22.D, #80

(153) 0x41a4d8 FMUL	Z0.D, Z0.D, Z22.D

(153) 0x41a4dc FNEG	Z21.D, P0/M, Z21.D

(153) 0x41a4e0 FDIVR	Z0.D, P0/M, Z0.D, Z21.D

(153) 0x41a4e4 LDR	Z21, [X10, #504, MUL VL]

(153) 0x41a4e8 MUL	Z21.D, Z21.D, Z14.D

(153) 0x41a4ec FMLA	Z4.D, P0/M, Z0.D, Z19.D

(153) 0x41a4f0 LDR	Z19, [X10, #505, MUL VL]

(153) 0x41a4f4 MUL	Z19.D, Z19.D, Z14.D

(153) 0x41a4f8 ADR	Z19.D, [Z30, Z19.D,LSL #3]

(153) 0x41a4fc ADR	Z19.D, [Z19, Z15.D,SXTW #3]

(153) 0x41a500 ST1D	{Z4.D}, P0, [V19.D]

(153) 0x41a504 ADR	Z4.D, [Z31, Z21.D,LSL #3]

(153) 0x41a508 LDR	Z21, [X10, #503, MUL VL]

(153) 0x41a50c LD1D	{Z3.D}, P0/Z, [V3.D]

(153) 0x41a510 LD1D	{Z2.D}, P0/Z, [V2.D]

(153) 0x41a514 LD1D	{Z16.D}, P0/Z, [V16.D]

(153) 0x41a518 LD1D	{Z5.D}, P0/Z, [V5.D]

(153) 0x41a51c ADR	Z4.D, [Z4, Z15.D,SXTW #3]

(153) 0x41a520 LD1D	{Z4.D}, P0/Z, [V4.D]

(153) 0x41a524 MUL	Z21.D, Z21.D, Z14.D

(153) 0x41a528 FSUB	Z2.D, Z3.D, Z2.D

(153) 0x41a52c FSUB	Z5.D, Z16.D, Z5.D

(153) 0x41a530 ADR	Z21.D, [Z8, Z21.D,LSL #3]

(153) 0x41a534 ADR	Z22.D, [Z21, Z15.D,SXTW #3]

(153) 0x41a538 ADR	Z21.D, [Z21, Z12.D,SXTW #3]

(153) 0x41a53c LD1D	{Z3.D}, P0/Z, [V21.D]

(153) 0x41a540 FMUL	Z2.D, Z3.D, Z2.D

(153) 0x41a544 LDR	Z3, [X10, #502, MUL VL]

(153) 0x41a548 MUL	Z3.D, Z3.D, Z14.D

(153) 0x41a54c LD1D	{Z16.D}, P0/Z, [V22.D]

(153) 0x41a550 FMLA	Z2.D, P0/M, Z16.D, Z5.D

(153) 0x41a554 FMAD	Z2.D, P0/M, Z0.D, Z4.D

(153) 0x41a558 ADR	Z3.D, [Z9, Z3.D,LSL #3]

(153) 0x41a55c ADR	Z3.D, [Z3, Z15.D,SXTW #3]

(153) 0x41a560 ST1D	{Z2.D}, P0, [V3.D]

(153) 0x41a564 MUL	Z2.D, Z23.D, Z14.D

(153) 0x41a568 ADR	Z14.D, [Z13, Z15.D,SXTW #3]

(153) 0x41a56c LD1D	{Z20.D}, P0/Z, [V20.D]

(153) 0x41a570 LD1D	{Z26.D}, P0/Z, [V26.D]

(153) 0x41a574 ADR	Z2.D, [Z10, Z2.D,LSL #3]

(153) 0x41a578 ADR	Z4.D, [Z2, Z15.D,SXTW #3]

(153) 0x41a57c ADR	Z2.D, [Z2, Z12.D,SXTW #3]

(153) 0x41a580 LD1D	{Z15.D}, P0/Z, [V14.D]

(153) 0x41a584 LD1D	{Z5.D}, P0/Z, [V4.D]

(153) 0x41a588 LD1D	{Z16.D}, P0/Z, [V2.D]

(153) 0x41a58c FSUB	Z5.D, Z5.D, Z16.D

(153) 0x41a590 ADR	Z16.D, [Z13, Z12.D,SXTW #3]

(153) 0x41a594 LD1D	{Z12.D}, P0/Z, [V16.D]

(153) 0x41a598 FSUB	Z12.D, Z15.D, Z12.D

(153) 0x41a59c FMUL	Z20.D, Z20.D, Z12.D

(153) 0x41a5a0 FMAD	Z5.D, P0/M, Z26.D, Z20.D

(153) 0x41a5a4 LD1D	{Z20.D}, P0/Z, [V19.D]

(153) 0x41a5a8 FMAD	Z5.D, P0/M, Z0.D, Z20.D

(153) 0x41a5ac ST1D	{Z5.D}, P0, [V19.D]

(153) 0x41a5b0 LD1D	{Z2.D}, P0/Z, [V2.D]

(153) 0x41a5b4 LD1D	{Z16.D}, P0/Z, [V16.D]

(153) 0x41a5b8 FSUB	Z2.D, Z2.D, Z16.D

(153) 0x41a5bc LD1D	{Z19.D}, P0/Z, [V21.D]

(153) 0x41a5c0 LD1D	{Z4.D}, P0/Z, [V4.D]

(153) 0x41a5c4 LD1D	{Z5.D}, P0/Z, [V14.D]

(153) 0x41a5c8 FSUB	Z4.D, Z4.D, Z5.D

(153) 0x41a5cc LD1D	{Z20.D}, P0/Z, [V22.D]

(153) 0x41a5d0 FMUL	Z2.D, Z19.D, Z2.D

(153) 0x41a5d4 FMLA	Z2.D, P0/M, Z20.D, Z4.D

(153) 0x41a5d8 LD1D	{Z4.D}, P0/Z, [V3.D]

(153) 0x41a5dc FMAD	Z0.D, P0/M, Z2.D, Z4.D

(153) 0x41a5e0 ST1D	{Z0.D}, P0, [V3.D]

(153) 0x41a5e4 LDR	Z0, [X10, #511, MUL VL]

(153) 0x41a5e8 ADD	Z11.D, Z11.D, Z0.D

(153) 0x41a5ec CBNZ	X30, 41a3a0

0x41a5f0 ORR	X7, XZR, X12

0x41a5f4 LDR	X24, [SP, #40]

0x41a5f8 ORR	X19, XZR, X28

0x41a5fc ORR	X22, XZR, X14

0x41a600 ORR	X10, XZR, X13

0x41a604 ORR	X11, XZR, X25

0x41a608 LDR	X14, [SP, #24]

0x41a60c ORR	X8, XZR, X18

0x41a610 CMP	X2, X9

0x41a614 ORR	X9, XZR, X1

0x41a618 LDR	X1, [SP, #64]

0x41a61c B.EQ	41a86c

0x41a620 FMOV	D0, #-0.2500000

0x41a624 ADD	X12, X27, #1

0x41a628 SUB	W28, WZR, W0

0x41a62c STR	X12, [SP, #40]

0x41a630 HINT	#0

0x41a634 HINT	#0

0x41a638 HINT	#0

0x41a63c HINT	#0

(152) 0x41a640 SDIV	X12, X26, X0

(152) 0x41a644 LDP	X18, X13, [SP, #88]

(152) 0x41a648 ORR	X23, XZR, X21

(152) 0x41a64c ORR	X21, XZR, X7

(152) 0x41a650 ORR	X27, XZR, X22

(152) 0x41a654 ORR	X22, XZR, X6

(152) 0x41a658 ORR	X6, XZR, X5

(152) 0x41a65c ADD	W20, W18, W26

(152) 0x41a660 LDP	X0, X18, [SP, #72]

(152) 0x41a664 ADD	X26, X26, #1

(152) 0x41a668 LDR	D1, [X0]

(152) 0x41a66c ADD	W13, W13, W12

(152) 0x41a670 MADD	W20, W28, W12, W20

(152) 0x41a674 ADD	W12, W18, W12

(152) 0x41a678 SBFM	X25, X12, #0, #31

(152) 0x41a67c MADD	X12, X1, X25, XZR

(152) 0x41a680 ADD	W30, W20, #1

(152) 0x41a684 ADD	X18, X9, X12,LSL #3

(152) 0x41a688 MADD	X12, X14, X25, XZR

(152) 0x41a68c LDR	D2, [X18, X20,SXTW #3]

(152) 0x41a690 ADD	X0, X11, X12,LSL #3

(152) 0x41a694 SBFM	X12, X13, #0, #31

(152) 0x41a698 MADD	X13, X1, X12, XZR

(152) 0x41a69c MADD	X1, X14, X12, XZR

(152) 0x41a6a0 LDR	D3, [X0, X20,SXTW #3]

(152) 0x41a6a4 MADD	X2, X7, X12, XZR

(152) 0x41a6a8 ORR	X7, XZR, X10

(152) 0x41a6ac ORR	X10, XZR, X19

(152) 0x41a6b0 ORR	X19, XZR, X17

(152) 0x41a6b4 ADD	X13, X9, X13,LSL #3

(152) 0x41a6b8 ADD	X1, X11, X1,LSL #3

(152) 0x41a6bc ADD	X2, X5, X2,LSL #3

(152) 0x41a6c0 ORR	X5, XZR, X4

(152) 0x41a6c4 LDR	D4, [X13, X20,SXTW #3]

(152) 0x41a6c8 LDR	D5, [X1, X20,SXTW #3]

(152) 0x41a6cc FMUL	D4, D4, D5

(152) 0x41a6d0 FMADD	D2, D2, D3, D4

(152) 0x41a6d4 LDR	D3, [X13, X30,SXTW #3]

(152) 0x41a6d8 LDR	D4, [X1, X30,SXTW #3]

(152) 0x41a6dc MADD	X13, X4, X12, XZR

(152) 0x41a6e0 MADD	X1, X17, X25, XZR

(152) 0x41a6e4 ORR	X4, XZR, X3

(152) 0x41a6e8 ADD	X13, X3, X13,LSL #3

(152) 0x41a6ec ADD	X1, X16, X1,LSL #3

(152) 0x41a6f0 MADD	X3, X24, X12, XZR

(152) 0x41a6f4 LDR	D16, [X1, X30,SXTW #3]

(152) 0x41a6f8 FMADD	D2, D3, D4, D2

(152) 0x41a6fc LDR	D3, [X18, X30,SXTW #3]

(152) 0x41a700 LDR	D4, [X0, X30,SXTW #3]

(152) 0x41a704 MADD	X18, X17, X12, XZR

(152) 0x41a708 MADD	X0, X15, X25, XZR

(152) 0x41a70c ORR	X17, XZR, X16

(152) 0x41a710 ADD	X18, X16, X18,LSL #3

(152) 0x41a714 ADD	X0, X8, X0,LSL #3

(152) 0x41a718 ORR	X16, XZR, X15

(152) 0x41a71c LDR	D5, [X18, X30,SXTW #3]

(152) 0x41a720 LDR	D6, [X18, X20,SXTW #3]

(152) 0x41a724 LDR	D7, [X0, X30,SXTW #3]

(152) 0x41a728 FMADD	D2, D3, D4, D2

(152) 0x41a72c LDR	D3, [X13, X30,SXTW #3]

(152) 0x41a730 MADD	X13, X15, X12, XZR

(152) 0x41a734 LDR	X15, [SP, #56]

(152) 0x41a738 ADD	X13, X8, X13,LSL #3

(152) 0x41a73c FSUB	D5, D5, S6

(152) 0x41a740 LDR	D6, [X1, X20,SXTW #3]

(152) 0x41a744 LDR	D4, [X13, X30,SXTW #3]

(152) 0x41a748 FMUL	D2, D2, D0

(152) 0x41a74c ADD	X3, X15, X3,LSL #3

(152) 0x41a750 ORR	X15, XZR, X16

(152) 0x41a754 ORR	X16, XZR, X17

(152) 0x41a758 ORR	X17, XZR, X19

(152) 0x41a75c ORR	X19, XZR, X10

(152) 0x41a760 ORR	X10, XZR, X7

(152) 0x41a764 ORR	X7, XZR, X21

(152) 0x41a768 ORR	X21, XZR, X23

(152) 0x41a76c FDIV	D1, D1, D2

(152) 0x41a770 FSUB	D6, D16, S6

(152) 0x41a774 FMUL	D6, D7, D6

(152) 0x41a778 FMADD	D4, D4, D5, D6

(152) 0x41a77c FMADD	D2, D1, D4, D3

(152) 0x41a780 STR	D2, [X2, X30,SXTW #3]

(152) 0x41a784 LDR	D3, [X18, X30,SXTW #3]

(152) 0x41a788 LDR	D6, [X1, X30,SXTW #3]

(152) 0x41a78c LDR	D4, [X18, X20,SXTW #3]

(152) 0x41a790 MADD	X18, X27, X12, XZR

(152) 0x41a794 LDR	D7, [X1, X20,SXTW #3]

(152) 0x41a798 LDR	D2, [X3, X30,SXTW #3]

(152) 0x41a79c LDR	X1, [SP, #48]

(152) 0x41a7a0 ORR	X3, XZR, X4

(152) 0x41a7a4 ORR	X4, XZR, X5

(152) 0x41a7a8 ORR	X5, XZR, X6

(152) 0x41a7ac ORR	X6, XZR, X22

(152) 0x41a7b0 ORR	X22, XZR, X27

(152) 0x41a7b4 ADD	X18, X19, X18,LSL #3

(152) 0x41a7b8 LDR	D5, [X18, X30,SXTW #3]

(152) 0x41a7bc MADD	X1, X1, X12, XZR

(152) 0x41a7c0 MADD	X12, X23, X12, XZR

(152) 0x41a7c4 FSUB	D3, D3, S6

(152) 0x41a7c8 LDR	D6, [X18, X20,SXTW #3]

(152) 0x41a7cc FSUB	D4, D4, S7

(152) 0x41a7d0 ADD	X1, X10, X1,LSL #3

(152) 0x41a7d4 ADD	X12, X6, X12,LSL #3

(152) 0x41a7d8 FMUL	D4, D6, D4

(152) 0x41a7dc FMADD	D3, D5, D3, D4

(152) 0x41a7e0 FMADD	D2, D1, D3, D2

(152) 0x41a7e4 STR	D2, [X1, X30,SXTW #3]

(152) 0x41a7e8 LDR	D5, [X12, X30,SXTW #3]

(152) 0x41a7ec LDR	D6, [X12, X20,SXTW #3]

(152) 0x41a7f0 LDR	D2, [X13, X30,SXTW #3]

(152) 0x41a7f4 MADD	X13, X23, X25, XZR

(152) 0x41a7f8 LDR	D3, [X0, X30,SXTW #3]

(152) 0x41a7fc LDR	D4, [X2, X30,SXTW #3]

(152) 0x41a800 LDR	X0, [SP, #104]

(152) 0x41a804 ADD	X13, X6, X13,LSL #3

(152) 0x41a808 LDR	D7, [X13, X20,SXTW #3]

(152) 0x41a80c FSUB	D5, D5, S6

(152) 0x41a810 LDR	D6, [X13, X30,SXTW #3]

(152) 0x41a814 FSUB	D6, D6, S7

(152) 0x41a818 FMUL	D3, D3, D6

(152) 0x41a81c FMADD	D2, D2, D5, D3

(152) 0x41a820 FMADD	D2, D1, D2, D4

(152) 0x41a824 STR	D2, [X2, X30,SXTW #3]

(152) 0x41a828 LDR	D5, [X12, X20,SXTW #3]

(152) 0x41a82c LDR	D6, [X13, X20,SXTW #3]

(152) 0x41a830 LDR	D4, [X12, X30,SXTW #3]

(152) 0x41a834 LDR	D7, [X13, X30,SXTW #3]

(152) 0x41a838 LDR	D3, [X18, X20,SXTW #3]

(152) 0x41a83c LDR	D2, [X18, X30,SXTW #3]

(152) 0x41a840 LDR	D16, [X1, X30,SXTW #3]

(152) 0x41a844 LDR	X12, [SP, #40]

(152) 0x41a848 FSUB	D5, D5, S6

(152) 0x41a84c FSUB	D4, D4, S7

(152) 0x41a850 FMUL	D3, D3, D5

(152) 0x41a854 FMADD	D2, D2, D4, D3

(152) 0x41a858 FMADD	D1, D1, D2, D16

(152) 0x41a85c STR	D1, [X1, X30,SXTW #3]

(152) 0x41a860 LDR	X1, [SP, #64]

(152) 0x41a864 CMP	X12, X26

(152) 0x41a868 B.NE	41a640

0x41a86c LDR	W1, [SP, #36]

0x41a870 ADRP	X0,

0x41a874 ADD	X0, X0, #3016

0x41a878 BL	402cc0

0x41a87c ADDVL	SP, SP, #10

0x41a880 ADD	SP, SP, #144

0x41a884 LDP	D9, D8, [SP, #48]

0x41a888 LDP	D11, D10, [SP, #32]

0x41a88c LDP	D13, D12, [SP, #16]

0x41a890 LDP	X20, X19, [SP, #144]

0x41a894 LDP	X22, X21, [SP, #128]

0x41a898 LDP	X24, X23, [SP, #112]

0x41a89c LDP	X26, X25, [SP, #96]

0x41a8a0 LDP	X28, X27, [SP, #80]

0x41a8a4 LDP	X29, X30, [SP, #64]

0x41a8a8 LDP	D15, D14, [SP], #160

0x41a8ac RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.83 to 26.00 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 61% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.83 to 23.75 cycles (1.21x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
42% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.83 to 1.00 cycles (28.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 512 bytes. The binary function is storing 448 bytes.

General properties

nb instructions	189
loop length	756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	13.42	13.42	13.50	13.33	27.00	13.33	7.00	7.00	1.00	1.00	28.83	28.50	28.67	9.50	9.50
cycles	3.50	3.50	13.42	13.42	13.50	13.33	27.00	13.33	7.00	7.00	1.00	1.00	28.83	28.50	28.67	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Overall L1	28.83

Vectorization ratios

INT

all	16%
load	16%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	16%
load	16%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.83 cycles. At this rate:

18% of peak load performance is reached (17.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.54 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41a140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #54	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W19, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W24, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W28, W19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W28, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41a87c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x73c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W9, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46c1b0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2992	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #116	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X6, X23, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR WZR, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X19, X24, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X5, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #120	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X20, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X27, X8, X20, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X20, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X20, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41a86c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X2, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X25, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X26, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X15, X17, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X0, X13, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X22, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X27, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CNTD X12, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X10, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X2, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 41a620 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X25, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STR X24, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X18, X2, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z7.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X14, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X20, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z6.D, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X1, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z24.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X9, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X18, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X30, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z28.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z17.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z18.D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z23.D, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z25.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z27.D, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z29.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z30.D, X5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z8.D, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z9.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z10.D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z1.D, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z31.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X28, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X12, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
INDEX Z11.D, X20, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X12, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X14, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X14, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X14, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X22, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X13, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X13, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X13, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X7, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X24, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X19, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X11, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR X9, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 41a86c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X12, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB W28, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46c870>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3016	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP D15, D14, [SP], #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
42% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.83 to 1.00 cycles (28.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 512 bytes. The binary function is storing 448 bytes.

General properties

nb instructions	189
loop length	756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	13.42	13.42	13.50	13.33	27.00	13.33	7.00	7.00	1.00	1.00	28.83	28.50	28.67	9.50	9.50
cycles	3.50	3.50	13.42	13.42	13.50	13.33	27.00	13.33	7.00	7.00	1.00	1.00	28.83	28.50	28.67	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Overall L1	28.83

Vectorization ratios

INT

all	16%
load	16%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	16%
load	16%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.83 cycles. At this rate:

18% of peak load performance is reached (17.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.54 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41a140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #54	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W19, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W24, W23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W28, W19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W28, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 41a87c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x73c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W9, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46c1b0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2992	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #116	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X6, X23, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR WZR, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X19, X24, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X5, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #120	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X20, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X27, X8, X20, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X20, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X20, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 41a86c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X2, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X25, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X26, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X15, X17, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X0, X13, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X22, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X27, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CNTD X12, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X10, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X2, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 41a620 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X25, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STR X24, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X18, X2, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z7.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X14, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X20, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z6.D, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X1, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z24.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X9, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X18, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X30, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z28.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z17.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z18.D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z23.D, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z25.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z27.D, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z29.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z30.D, X5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z8.D, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z9.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z10.D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z1.D, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z31.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X28, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X12, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
INDEX Z11.D, X20, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
DUP Z0.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X12, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X12, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X14, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X14, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X14, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X22, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X13, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X13, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X13, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X7, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X24, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X19, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X11, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR X9, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 41a86c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X12, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB W28, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #36]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46c870>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3016	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP D15, D14, [SP], #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.88	4.90
○Loop 153 - accelerate.cpp:41-53 - exec	5.88	4.86
○Loop 152 - accelerate.cpp:41-53 - exec	0.00	0.00

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Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code