OV - exec - Function viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, ...	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage (incl. loops): 3.66% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

0x43b560 STP	D15, D14, [SP, #864]!

0x43b564 STP	D13, D12, [SP, #16]

0x43b568 STP	D11, D10, [SP, #32]

0x43b56c STP	D9, D8, [SP, #48]

0x43b570 STP	X29, X30, [SP, #64]

0x43b574 STP	X28, X27, [SP, #80]

0x43b578 STP	X26, X25, [SP, #96]

0x43b57c STP	X24, X23, [SP, #112]

0x43b580 STP	X22, X21, [SP, #128]

0x43b584 STP	X20, X19, [SP, #144]

0x43b588 ADD	X29, SP, #64

0x43b58c SUB	SP, SP, #48

0x43b590 ADDVL	SP, SP, #59

0x43b594 LDR	W22, [X2]

0x43b598 LDR	W8, [X3]

0x43b59c LDR	W24, [X4]

0x43b5a0 ADD	W23, W22, #1

0x43b5a4 LDR	W9, [X5]

0x43b5a8 ADD	W8, W8, #2

0x43b5ac ADD	W26, W24, #1

0x43b5b0 ADD	W9, W9, #2

0x43b5b4 SUBS	W8, W8, W23

0x43b5b8 CCMP	W9, W26, #4, #12

0x43b5bc B.LE	43b638

0x43b5c0 LDR	W19, [X0]

0x43b5c4 SUB	W25, W9, W26

0x43b5c8 MOVN	X9, #0

0x43b5cc ORR	X20, XZR, X7

0x43b5d0 ORR	X21, XZR, X6

0x43b5d4 ADRP	X0,

0x43b5d8 ADD	X0, X0, #3224

0x43b5dc ADD	X3, SP, #20

0x43b5e0 ADD	X4, SP, #40

0x43b5e4 STR	WZR, [SP, #20]

0x43b5e8 ORR	W1, WZR, W19

0x43b5ec UMADDL	X27, W25, W8, X9

0x43b5f0 MOVZ	W8, #1

0x43b5f4 ADD	X5, SP, #32

0x43b5f8 ADD	X6, SP, #24

0x43b5fc MOVZ	W2, #34

0x43b600 MOVZ	W7, #1

0x43b604 STP	X27, XZR, [SP, #32]

0x43b608 STR	X8, [SP, #24]

0x43b60c STR	X8, [SP]

0x43b610 BL	402e00

0x43b614 LDP	X8, X7, [SP, #32]

0x43b618 CMP	X8, X27

0x43b61c CSEL	X3, X8, X27, #11

0x43b620 CMP	X7, X3

0x43b624 B.LE	43b66c

  (740) 0x43b628 ADRP	X0,

  (740) 0x43b62c ADD	X0, X0, #3248

  (740) 0x43b630 ORR	W1, WZR, W19

  (740) 0x43b634 BL	402cc0

  (740) 0x43b638 ADDVL	SP, SP, #5

  (740) 0x43b63c ADD	SP, SP, #48

  (740) 0x43b640 LDP	D9, D8, [SP, #48]

  (740) 0x43b644 LDP	D11, D10, [SP, #32]

  (740) 0x43b648 LDP	D13, D12, [SP, #16]

  (740) 0x43b64c LDP	X20, X19, [SP, #144]

  (740) 0x43b650 LDP	X22, X21, [SP, #128]

  (740) 0x43b654 LDP	X24, X23, [SP, #112]

  (740) 0x43b658 LDP	X26, X25, [SP, #96]

  (740) 0x43b65c LDP	X28, X27, [SP, #80]

  (740) 0x43b660 LDP	X29, X30, [SP, #64]

  (740) 0x43b664 LDP	D15, D14, [SP], #160

  (740) 0x43b668 RET

  (740) 0x43b66c LDP	X13, X15, [X29, #104]

  (740) 0x43b670 LDP	X1, X18, [X29, #120]

  (740) 0x43b674 LDR	X12, [X29, #96]

  (740) 0x43b678 SUB	X2, X3, X7

  (740) 0x43b67c CNTD	X6, ALL

  (740) 0x43b680 ADD	X4, X2, #1

  (740) 0x43b684 LDR	X8, [X21, #16]

  (740) 0x43b688 LDR	X9, [X21]

  (740) 0x43b68c LDR	X10, [X20, #16]

  (740) 0x43b690 ORR	X2, XZR, X7

  (740) 0x43b694 LDR	X11, [X20]

  (740) 0x43b698 LDR	X13, [X13, #8]

  (740) 0x43b69c LDR	X12, [X12, #8]

  (740) 0x43b6a0 LDR	X14, [X15, #16]

  (740) 0x43b6a4 LDR	X15, [X15]

  (740) 0x43b6a8 LDR	X17, [X18, #16]

  (740) 0x43b6ac LDR	X18, [X18]

  (740) 0x43b6b0 LDR	X0, [X1, #16]

  (740) 0x43b6b4 LDR	X1, [X1]

  (740) 0x43b6b8 ADD	X16, X13, #16

  (740) 0x43b6bc CMP	X4, X6

  (740) 0x43b6c0 B.CC	43b998

  (740) 0x43b6c4 DUP	Z0.D, X6

  (740) 0x43b6c8 SUB	X20, X29, #64

  (740) 0x43b6cc PTRUE	P0.D, ALL

  (740) 0x43b6d0 SUB	X2, XZR, X6

  (740) 0x43b6d4 ADRP	X6,

  (740) 0x43b6d8 ADD	X6, X6, #656

  (740) 0x43b6dc AND	X5, X4, X2

  (740) 0x43b6e0 INDEX	Z26.D, X7, #1

  (740) 0x43b6e4 LD1RD	{Z22.D}, P0/Z, [X6]

  (740) 0x43b6e8 ADD	X2, X7, X5

  (740) 0x43b6ec ORR	X6, XZR, X5

  (740) 0x43b6f0 STR	Z0, [X20, #511, MUL VL]

  (740) 0x43b6f4 DUP	Z0.D, X23

  (740) 0x43b6f8 STR	Z0, [X20, #510, MUL VL]

  (740) 0x43b6fc DUP	Z0.D, X26

  (740) 0x43b700 DUP	Z1.D, X25

  (740) 0x43b704 DUP	Z4.D, X9

  (740) 0x43b708 STR	Z0, [X20, #509, MUL VL]

  (740) 0x43b70c DUP	Z0.D, X24

  (740) 0x43b710 DUP	Z5.D, X11

  (740) 0x43b714 DUP	Z6.D, X15

  (740) 0x43b718 STR	Z0, [X20, #508, MUL VL]

  (740) 0x43b71c DUP	Z0.D, X22

  (740) 0x43b720 DUP	Z17.D, X18

  (740) 0x43b724 DUP	Z18.D, X1

  (740) 0x43b728 STR	Z0, [X20, #507, MUL VL]

  (740) 0x43b72c DUP	Z19.D, X8

  (740) 0x43b730 DUP	Z20.D, X10

  (740) 0x43b734 DUP	Z21.D, X14

  (740) 0x43b738 DUP	Z24.D, X17

  (740) 0x43b73c DUP	Z25.D, X0

    (739) 0x43b740 MOVPRFX	Z23, Z26

    (739) 0x43b744 SDIV	Z23.D, P0/M, Z23.D, Z1.D

    (739) 0x43b748 SUB	X20, X29, #64

    (739) 0x43b74c DECD	X6, ALL

    (739) 0x43b750 LDR	Z0, [X20, #510, MUL VL]

    (739) 0x43b754 ADD	Z27.D, Z0.D, Z23.D

    (739) 0x43b758 LDR	Z0, [X20, #509, MUL VL]

    (739) 0x43b75c MOVPRFX	Z28, Z26

    (739) 0x43b760 MLS	Z28.D, P0/M, Z23.D, Z1.D

    (739) 0x43b764 MOVPRFX	Z29, Z27

    (739) 0x43b768 SXTW	Z29.D, P0/M, Z27.D

    (739) 0x43b76c ADD	Z30.D, Z0.D, Z28.D

    (739) 0x43b770 MUL	Z0.D, Z4.D, Z29.D

    (739) 0x43b774 ADR	Z2.D, [Z19, Z0.D,LSL #3]

    (739) 0x43b778 ORR	Z0.D, Z27.D, Z27.D

    (739) 0x43b77c ADD	Z0.D, Z0.D, #1

    (739) 0x43b780 ADR	Z9.D, [Z2, Z30.D,SXTW #3]

    (739) 0x43b784 SXTW	Z0.D, P0/M, Z0.D

    (739) 0x43b788 LD1D	{Z15.D}, P0/Z, [V9.D]

    (739) 0x43b78c MUL	Z8.D, Z5.D, Z0.D

    (739) 0x43b790 MUL	Z31.D, Z4.D, Z0.D

    (739) 0x43b794 MUL	Z0.D, Z6.D, Z0.D

    (739) 0x43b798 ADR	Z12.D, [Z20, Z8.D,LSL #3]

    (739) 0x43b79c MUL	Z8.D, Z5.D, Z29.D

    (739) 0x43b7a0 ADR	Z31.D, [Z19, Z31.D,LSL #3]

    (739) 0x43b7a4 ADR	Z0.D, [Z21, Z0.D,LSL #3]

    (739) 0x43b7a8 ADR	Z11.D, [Z31, Z30.D,SXTW #3]

    (739) 0x43b7ac ADR	Z13.D, [Z12, Z30.D,SXTW #3]

    (739) 0x43b7b0 ADR	Z0.D, [Z0, Z30.D,SXTW #3]

    (739) 0x43b7b4 LD1D	{Z7.D}, P0/Z, [V11.D]

    (739) 0x43b7b8 LD1D	{Z11.D}, P0/Z, [V13.D]

    (739) 0x43b7bc ADR	Z14.D, [Z20, Z8.D,LSL #3]

    (739) 0x43b7c0 ORR	Z8.D, Z30.D, Z30.D

    (739) 0x43b7c4 ADD	Z8.D, Z8.D, #1

    (739) 0x43b7c8 ADR	Z3.D, [Z14, Z30.D,SXTW #3]

    (739) 0x43b7cc LD1D	{Z0.D}, P0/Z, [V0.D]

    (739) 0x43b7d0 ADR	Z2.D, [Z2, Z8.D,SXTW #3]

    (739) 0x43b7d4 ADR	Z12.D, [Z12, Z8.D,SXTW #3]

    (739) 0x43b7d8 LD1D	{Z13.D}, P0/Z, [V3.D]

    (739) 0x43b7dc ADR	Z3.D, [Z14, Z8.D,SXTW #3]

    (739) 0x43b7e0 FADD	Z9.D, Z15.D, Z7.D

    (739) 0x43b7e4 LD1D	{Z10.D}, P0/Z, [V2.D]

    (739) 0x43b7e8 ADR	Z2.D, [Z31, Z8.D,SXTW #3]

    (739) 0x43b7ec LD1D	{Z2.D}, P0/Z, [V2.D]

    (739) 0x43b7f0 LD1D	{Z12.D}, P0/Z, [V12.D]

    (739) 0x43b7f4 LD1D	{Z14.D}, P0/Z, [V3.D]

    (739) 0x43b7f8 FADD	Z16.D, Z11.D, Z12.D

    (739) 0x43b7fc FADD	Z3.D, Z13.D, Z14.D

    (739) 0x43b800 FADD	Z31.D, Z10.D, Z2.D

    (739) 0x43b804 FSUB	Z31.D, Z31.D, Z9.D

    (739) 0x43b808 FSUB	Z9.D, Z16.D, Z3.D

    (739) 0x43b80c LDR	Z3, [X20, #507, MUL VL]

    (739) 0x43b810 MUL	Z16.D, Z6.D, Z29.D

    (739) 0x43b814 ADR	Z16.D, [Z21, Z16.D,LSL #3]

    (739) 0x43b818 ADD	Z3.D, Z3.D, Z23.D

    (739) 0x43b81c SXTW	Z3.D, P0/M, Z3.D

    (739) 0x43b820 MUL	Z3.D, Z6.D, Z3.D

    (739) 0x43b824 ADR	Z3.D, [Z21, Z3.D,LSL #3]

    (739) 0x43b828 ADR	Z23.D, [Z3, Z30.D,SXTW #3]

    (739) 0x43b82c FADD	Z3.D, Z2.D, Z7.D

    (739) 0x43b830 MUL	Z2.D, Z17.D, Z29.D

    (739) 0x43b834 MUL	Z7.D, Z18.D, Z29.D

    (739) 0x43b838 LDR	Z29, [X20, #508, MUL VL]

    (739) 0x43b83c FSUB	Z3.D, Z3.D, Z15.D

    (739) 0x43b840 LD1D	{Z23.D}, P0/Z, [V23.D]

    (739) 0x43b844 FSUB	Z3.D, Z3.D, Z10.D

    (739) 0x43b848 ADR	Z2.D, [Z24, Z2.D,LSL #3]

    (739) 0x43b84c ADR	Z7.D, [Z25, Z7.D,LSL #3]

    (739) 0x43b850 ADD	Z28.D, Z29.D, Z28.D

    (739) 0x43b854 FADD	Z29.D, Z12.D, Z14.D

    (739) 0x43b858 FMUL	Z3.D, P0/M, Z3.D, #0

    (739) 0x43b85c ADR	Z2.D, [Z2, Z30.D,SXTW #3]

    (739) 0x43b860 ADR	Z15.D, [Z7, Z30.D,SXTW #3]

    (739) 0x43b864 LD1D	{Z7.D}, P0/Z, [X12, Z30.D,SXTW #3]

    (739) 0x43b868 ADR	Z28.D, [Z16, Z28.D,SXTW #3]

    (739) 0x43b86c ADR	Z16.D, [Z16, Z8.D,SXTW #3]

    (739) 0x43b870 FSUB	Z29.D, Z29.D, Z13.D

    (739) 0x43b874 LD1D	{Z30.D}, P0/Z, [X12, Z8.D,SXTW #3]

    (739) 0x43b878 LD1D	{Z28.D}, P0/Z, [V28.D]

    (739) 0x43b87c LD1D	{Z16.D}, P0/Z, [V16.D]

    (739) 0x43b880 FSUB	Z29.D, Z29.D, Z11.D

    (739) 0x43b884 FSUB	Z0.D, Z0.D, Z23.D

    (739) 0x43b888 FMUL	Z29.D, P0/M, Z29.D, #0

    (739) 0x43b88c FADD	Z30.D, Z7.D, Z30.D

    (739) 0x43b890 FDIV	Z29.D, P0/M, Z29.D, Z7.D

    (739) 0x43b894 FSUB	Z16.D, Z16.D, Z28.D

    (739) 0x43b898 LD1D	{Z28.D}, P0/Z, [X13, Z27.D,SXTW #3]

    (739) 0x43b89c LD1D	{Z27.D}, P0/Z, [X16, Z27.D,SXTW #3]

    (739) 0x43b8a0 FDIV	Z16.D, P0/M, Z16.D, Z30.D

    (739) 0x43b8a4 MOVPRFX	Z30, Z9

    (739) 0x43b8a8 FMUL	Z30.D, P0/M, Z30.D, #0

    (739) 0x43b8ac FADD	Z23.D, Z28.D, Z27.D

    (739) 0x43b8b0 FDIV	Z3.D, P0/M, Z3.D, Z28.D

    (739) 0x43b8b4 MOVPRFX	Z27, Z31

    (739) 0x43b8b8 FMUL	Z27.D, P0/M, Z27.D, #0

    (739) 0x43b8bc FDIV	Z30.D, P0/M, Z30.D, Z28.D

    (739) 0x43b8c0 FDIV	Z0.D, P0/M, Z0.D, Z23.D

    (739) 0x43b8c4 FDIV	Z27.D, P0/M, Z27.D, Z7.D

    (739) 0x43b8c8 FCMLT	P2.D, P0/Z, Z16.D, #0

    (739) 0x43b8cc FADD	Z3.D, Z3.D, Z29.D

    (739) 0x43b8d0 FMUL	Z29.D, Z9.D, Z28.D

    (739) 0x43b8d4 FMUL	Z23.D, Z0.D, Z0.D

    (739) 0x43b8d8 FMUL	Z3.D, Z3.D, Z16.D

    (739) 0x43b8dc FMLA	Z29.D, P0/M, Z7.D, Z31.D

    (739) 0x43b8e0 FMUL	Z31.D, Z16.D, Z16.D

    (739) 0x43b8e4 FABS	Z16.D, P0/M, Z16.D

    (739) 0x43b8e8 FMUL	Z30.D, Z30.D, Z23.D

    (739) 0x43b8ec FMAXNM	Z16.D, P0/M, Z16.D, Z22.D

    (739) 0x43b8f0 FADD	Z23.D, Z31.D, Z23.D

    (739) 0x43b8f4 FCMGE	P1.D, P0/Z, Z29.D, #0

    (739) 0x43b8f8 FMAD	Z27.D, P0/M, Z31.D, Z30.D

    (739) 0x43b8fc FMAXNM	Z23.D, P0/M, Z23.D, Z22.D

    (739) 0x43b900 FMAD	Z3.D, P0/M, Z0.D, Z27.D

    (739) 0x43b904 MOVPRFX	Z27, Z16

    (739) 0x43b908 FNEG	Z27.D, P0/M, Z16.D

    (739) 0x43b90c FABS	Z0.D, P0/M, Z0.D

    (739) 0x43b910 SEL	Z16.D, P2, Z27.D, Z16.D

    (739) 0x43b914 FMAXNM	Z0.D, P0/M, Z0.D, Z22.D

    (739) 0x43b918 FCMLT	P2.D, P0/Z, Z16.D, #0

    (739) 0x43b91c FDIV	Z3.D, P0/M, Z3.D, Z23.D

    (739) 0x43b920 MOVPRFX	Z23, Z0

    (739) 0x43b924 FNEG	Z23.D, P0/M, Z0.D

    (739) 0x43b928 SEL	Z0.D, P2, Z23.D, Z0.D

    (739) 0x43b92c FMUL	Z23.D, Z0.D, Z0.D

    (739) 0x43b930 FMLA	Z23.D, P0/M, Z16.D, Z16.D

    (739) 0x43b934 FSQRT	Z23.D, P0/M, Z23.D

    (739) 0x43b938 FCMGT	P2.D, P0/Z, Z3.D, #0

    (739) 0x43b93c EOR	P2.B, P0/Z, P2.B, P0.B

    (739) 0x43b940 BIC	P1.B, P2/Z, P2.B, P1.B

    (739) 0x43b944 LD1D	{Z2.D}, P1/Z, [V2.D]

    (739) 0x43b948 FMUL	Z7.D, Z7.D, Z23.D

    (739) 0x43b94c FADD	Z2.D, Z2.D, Z2.D

    (739) 0x43b950 FDIV	Z7.D, P0/M, Z7.D, Z16.D

    (739) 0x43b954 FMUL	Z16.D, Z28.D, Z23.D

    (739) 0x43b958 FDIVR	Z0.D, P0/M, Z0.D, Z16.D

    (739) 0x43b95c FABS	Z7.D, P0/M, Z7.D

    (739) 0x43b960 FABS	Z0.D, P0/M, Z0.D

    (739) 0x43b964 FMINNM	Z0.D, P0/M, Z0.D, Z7.D

    (739) 0x43b968 FMUL	Z0.D, Z0.D, Z0.D

    (739) 0x43b96c FMUL	Z0.D, Z0.D, Z2.D

    (739) 0x43b970 DUP	Z2.D, #0

    (739) 0x43b974 FMUL	Z0.D, Z3.D, Z0.D

    (739) 0x43b978 FMUL	Z0.D, Z3.D, Z0.D

    (739) 0x43b97c SEL	Z0.D, P1, Z0.D, Z2.D

    (739) 0x43b980 ST1D	{Z0.D}, P0, [V15.D]

    (739) 0x43b984 LDR	Z0, [X20, #511, MUL VL]

    (739) 0x43b988 ADD	Z26.D, Z26.D, Z0.D

    (739) 0x43b98c CBNZ	X6, 43b740

  (740) 0x43b990 CMP	X4, X5

  (740) 0x43b994 B.EQ	43b628

(738) 0x43b998 ADRP	X5,

(738) 0x43b99c FMOV	D0, #0.5000000

(738) 0x43b9a0 ADD	X3, X3, #1

(738) 0x43b9a4 SUB	W4, WZR, W25

(738) 0x43b9a8 LDR	D1, [X5, #656]

(738) 0x43b9ac B	43b9d8

0x43b9b0 HINT	#0

0x43b9b4 HINT	#0

0x43b9b8 HINT	#0

0x43b9bc HINT	#0

(738) 0x43b9c0 MADD	X6, X1, X6, XZR

(738) 0x43b9c4 ADD	X2, X2, #1

(738) 0x43b9c8 ADD	X6, X0, X6,LSL #3

(738) 0x43b9cc STR	D17, [X6, X5,SXTW #3]

(738) 0x43b9d0 CMP	X3, X2

(738) 0x43b9d4 B.EQ	43b628

(738) 0x43b9d8 SDIV	X20, X2, X25

(738) 0x43b9dc ADD	W5, W24, W2

(738) 0x43b9e0 ADD	W7, W23, W20

(738) 0x43b9e4 MADD	W21, W4, W20, W5

(738) 0x43b9e8 ADD	W20, W22, W20

(738) 0x43b9ec SBFM	X6, X7, #0, #31

(738) 0x43b9f0 ADD	W28, W7, #1

(738) 0x43b9f4 SBFM	X20, X20, #0, #31

(738) 0x43b9f8 MADD	X27, X9, X6, XZR

(738) 0x43b9fc SBFM	X28, X28, #0, #31

(738) 0x43ba00 ADD	W5, W21, #1

(738) 0x43ba04 ADD	W26, W21, #2

(738) 0x43ba08 MADD	X20, X15, X20, XZR

(738) 0x43ba0c MADD	X30, X9, X28, XZR

(738) 0x43ba10 ADD	X27, X8, X27,LSL #3

(738) 0x43ba14 ADD	X20, X14, X20,LSL #3

(738) 0x43ba18 LDR	D6, [X27, X26,SXTW #3]

(738) 0x43ba1c LDR	D16, [X27, X5,SXTW #3]

(738) 0x43ba20 MADD	X27, X11, X28, XZR

(738) 0x43ba24 ADD	X30, X8, X30,LSL #3

(738) 0x43ba28 LDR	D7, [X30, X26,SXTW #3]

(738) 0x43ba2c LDR	D17, [X30, X5,SXTW #3]

(738) 0x43ba30 ADD	X27, X10, X27,LSL #3

(738) 0x43ba34 LDR	D18, [X27, X5,SXTW #3]

(738) 0x43ba38 LDR	D19, [X27, X26,SXTW #3]

(738) 0x43ba3c MADD	X27, X11, X6, XZR

(738) 0x43ba40 ADD	X27, X10, X27,LSL #3

(738) 0x43ba44 LDR	D21, [X27, X26,SXTW #3]

(738) 0x43ba48 LDR	D20, [X27, X5,SXTW #3]

(738) 0x43ba4c MADD	X27, X15, X6, XZR

(738) 0x43ba50 FADD	D2, D6, D7

(738) 0x43ba54 FADD	D7, D7, D17

(738) 0x43ba58 FADD	D3, D16, D17

(738) 0x43ba5c LDR	D17, [X20, X5,SXTW #3]

(738) 0x43ba60 ADD	X27, X14, X27,LSL #3

(738) 0x43ba64 FSUB	D7, D7, S16

(738) 0x43ba68 FSUB	D4, D2, S3

(738) 0x43ba6c FADD	D2, D18, D19

(738) 0x43ba70 LDR	D16, [X27, X21,SXTW #3]

(738) 0x43ba74 MADD	X21, X15, X28, XZR

(738) 0x43ba78 FSUB	D6, D7, S6

(738) 0x43ba7c ADD	X21, X14, X21,LSL #3

(738) 0x43ba80 FADD	D7, D19, D21

(738) 0x43ba84 FADD	D3, D20, D21

(738) 0x43ba88 FMUL	D19, D4, D0

(738) 0x43ba8c FMUL	D6, D6, D0

(738) 0x43ba90 FSUB	D7, D7, S20

(738) 0x43ba94 FSUB	D5, D2, S3

(738) 0x43ba98 LDR	D3, [X12, X5,SXTW #3]

(738) 0x43ba9c LDR	D2, [X13, X7,SXTW #3]

(738) 0x43baa0 FSUB	D7, D7, S18

(738) 0x43baa4 FMUL	D20, D5, D0

(738) 0x43baa8 FMUL	D7, D7, D0

(738) 0x43baac FDIV	D6, D6, D2

(738) 0x43bab0 FDIV	D20, D20, D2

(738) 0x43bab4 FDIV	D19, D19, D3

(738) 0x43bab8 FDIV	D7, D7, D3

(738) 0x43babc FADD	D7, D6, D7

(738) 0x43bac0 LDR	D6, [X27, X26,SXTW #3]

(738) 0x43bac4 FSUB	D6, D6, S16

(738) 0x43bac8 LDR	D16, [X12, X26,SXTW #3]

(738) 0x43bacc FADD	D16, D3, D16

(738) 0x43bad0 FDIV	D6, D6, D16

(738) 0x43bad4 LDR	D16, [X21, X5,SXTW #3]

(738) 0x43bad8 FSUB	D16, D16, S17

(738) 0x43badc LDR	D17, [X16, X7,SXTW #3]

(738) 0x43bae0 FADD	D17, D2, D17

(738) 0x43bae4 FDIV	D16, D16, D17

(738) 0x43bae8 FMUL	D17, D6, D6

(738) 0x43baec FMUL	D7, D7, D6

(738) 0x43baf0 FMUL	D18, D16, D16

(738) 0x43baf4 FMUL	D20, D20, D18

(738) 0x43baf8 FMADD	D19, D19, D17, D20

(738) 0x43bafc FADD	D17, D17, D18

(738) 0x43bb00 FMADD	D7, D7, D16, D19

(738) 0x43bb04 FMAXNM	D17, D17, D1

(738) 0x43bb08 FDIV	D7, D7, D17

(738) 0x43bb0c MOVI	D17, #0

(738) 0x43bb10 FCMP	D7, #0

(738) 0x43bb14 B.GT	43b9c0

(738) 0x43bb18 FMUL	D5, D5, D2

(738) 0x43bb1c FMADD	D4, D3, D4, D5

(738) 0x43bb20 FCMP	D4, #0

(738) 0x43bb24 B.GE	43b9c0

(738) 0x43bb28 FABS	D4, D6

(738) 0x43bb2c FCMP	D6, #0

(738) 0x43bb30 MADD	X7, X18, X6, XZR

(738) 0x43bb34 FMAXNM	D4, D4, D1

(738) 0x43bb38 ADD	X7, X17, X7,LSL #3

(738) 0x43bb3c FNEG	D5, D4

(738) 0x43bb40 FCSEL	D4, D5, D4, #4

(738) 0x43bb44 FABS	D5, D16

(738) 0x43bb48 FMAXNM	D5, D5, D1

(738) 0x43bb4c FCMP	D4, #0

(738) 0x43bb50 FNEG	D6, D5

(738) 0x43bb54 FCSEL	D5, D6, D5, #4

(738) 0x43bb58 FMUL	D6, D5, D5

(738) 0x43bb5c FMADD	D6, D4, D4, D6

(738) 0x43bb60 FSQRT	D6, D6

(738) 0x43bb64 FMUL	D3, D3, D6

(738) 0x43bb68 FMUL	D2, D2, D6

(738) 0x43bb6c FDIV	D3, D3, D4

(738) 0x43bb70 FDIV	D2, D2, D5

(738) 0x43bb74 FABS	D3, D3

(738) 0x43bb78 FABS	D2, D2

(738) 0x43bb7c FMINNM	D2, D3, D2

(738) 0x43bb80 LDR	D3, [X7, X5,SXTW #3]

(738) 0x43bb84 FMUL	D2, D2, D2

(738) 0x43bb88 FADD	D3, D3, D3

(738) 0x43bb8c FMUL	D2, D2, D3

(738) 0x43bb90 FMUL	D2, D7, D2

(738) 0x43bb94 FMUL	D17, D7, D2

(738) 0x43bb98 B	43b9c0

0x43bb9c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 7.00 to 6.12 cycles (1.14x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 196 bytes.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	7.00	7.00	6.00	5.00	5.00
cycles	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	7.00	7.00	6.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	11%
load	0%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
58% of peak store performance is reached (28.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43b560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB SP, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #59	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W26, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W26, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 43b638 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W9, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46f5d4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X27, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X7, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X3, X8, X27, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43b66c <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 196 bytes.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	7.00	7.00	6.00	5.00	5.00
cycles	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	7.00	7.00	6.00	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	11%
load	0%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
58% of peak store performance is reached (28.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43b560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB SP, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #59	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W23, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W26, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, W26, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 43b638 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W25, W9, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46f5d4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X27, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X7, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X3, X8, X27, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43b66c <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]–	3.66	3.05
▼Loop 738 - viscosity.cpp:36-64 - exec–	0.00	0.00
▼Loop 740 - viscosity.cpp:36-64 - exec–	0.00	0.00
○Loop 739 - viscosity.cpp:37-64 - exec	3.66	3.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code