OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 6.90% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x428520 STP	D15, D14, [SP, #864]!

0x428524 STP	D13, D12, [SP, #16]

0x428528 STP	D11, D10, [SP, #32]

0x42852c STP	D9, D8, [SP, #48]

0x428530 STP	X29, X30, [SP, #64]

0x428534 STP	X28, X27, [SP, #80]

0x428538 STP	X26, X25, [SP, #96]

0x42853c STP	X24, X23, [SP, #112]

0x428540 STP	X22, X21, [SP, #128]

0x428544 STP	X20, X19, [SP, #144]

0x428548 ADD	X29, SP, #64

0x42854c SUB	SP, SP, #256

0x428550 ADDVL	SP, SP, #56

0x428554 LDR	W8, [X2]

0x428558 LDR	W22, [X4]

0x42855c LDR	W9, [X5]

0x428560 ADD	W25, W8, #1

0x428564 LDR	W8, [X3]

0x428568 ADD	W24, W22, #1

0x42856c ADD	W9, W9, #2

0x428570 ADD	W8, W8, #2

0x428574 SUBS	W8, W8, W25

0x428578 CCMP	W9, W24, #4, #12

0x42857c B.LE	428cdc

0x428580 LDR	W1, [X0]

0x428584 SUB	W10, W9, W24

0x428588 MOVN	X9, #0

0x42858c ORR	X23, XZR, X7

0x428590 ORR	X26, XZR, X6

0x428594 ADRP	X0,

0x428598 ADD	X0, X0, #2488

0x42859c ADD	X3, SP, #228

0x4285a0 ADD	X4, SP, #248

0x4285a4 STR	WZR, [SP, #228]

0x4285a8 STR	X22, [SP, #200]

0x4285ac STP	X25, X10, [SP, #208]

0x4285b0 UMADDL	X19, W10, W8, X9

0x4285b4 MOVZ	W8, #1

0x4285b8 ADD	X5, SP, #240

0x4285bc ADD	X6, SP, #232

0x4285c0 MOVZ	W2, #34

0x4285c4 MOVZ	W7, #1

0x4285c8 STR	X8, [SP, #232]

0x4285cc STR	X8, [SP]

0x4285d0 STP	X19, XZR, [SP, #240]

0x4285d4 STR	W1, [SP, #148]

0x4285d8 BL	402e00

0x4285dc LDP	X8, X2, [SP, #240]

0x4285e0 CMP	X8, X19

0x4285e4 CSEL	X8, X8, X19, #11

0x4285e8 CMP	X2, X8

0x4285ec B.GT	428ccc

0x4285f0 STR	X8, [SP, #152]

0x4285f4 LDP	X8, X11, [X29, #104]

0x4285f8 LDP	X9, X3, [X29, #176]

0x4285fc LDR	X10, [X29, #168]

0x428600 LDP	X5, X4, [X29, #152]

0x428604 LDP	X7, X6, [X29, #136]

0x428608 LDP	X0, X19, [X29, #120]

0x42860c LDR	X12, [X26, #16]

0x428610 LDR	X17, [X26]

0x428614 LDR	X13, [X23]

0x428618 STR	X8, [SP, #184]

0x42861c LDR	X8, [X29, #96]

0x428620 LDR	X26, [X4, #16]

0x428624 LDR	X25, [X4]

0x428628 LDR	X4, [SP, #152]

0x42862c LDR	X30, [X9, #16]

0x428630 LDR	X22, [X9]

0x428634 LDR	X9, [X10]

0x428638 STR	X12, [SP, #176]

0x42863c LDR	X12, [X23, #16]

0x428640 LDR	X16, [X11, #16]

0x428644 LDR	X21, [X11]

0x428648 LDR	X18, [X0, #16]

0x42864c LDR	X0, [X0]

0x428650 LDR	X1, [X19, #16]

0x428654 LDR	X28, [X19]

0x428658 LDR	X11, [X7, #16]

0x42865c LDR	X27, [X7]

0x428660 LDR	X19, [X6, #16]

0x428664 LDR	X6, [X6]

0x428668 LDR	X23, [X5, #16]

0x42866c LDR	X20, [X5]

0x428670 LDR	X7, [X3, #16]

0x428674 LDR	X3, [X3]

0x428678 LDR	X14, [X8, #16]

0x42867c LDR	X15, [X8]

0x428680 LDR	X8, [X10, #16]

0x428684 CNTD	X10, ALL

0x428688 STR	X9, [SP, #192]

0x42868c SUB	X9, X4, X2

0x428690 ADD	X5, X9, #1

0x428694 ORR	X9, XZR, X2

0x428698 STP	X3, X6, [SP, #160]

0x42869c CMP	X5, X10

0x4286a0 B.CC	428a70

0x4286a4 DUP	Z0.D, X10

0x4286a8 SUB	X9, XZR, X10

0x4286ac SUB	X10, X29, #64

0x4286b0 STP	X12, X22, [SP, #104]

0x4286b4 STP	X5, X28, [SP, #24]

0x4286b8 PTRUE	P0.D, ALL

0x4286bc FDUP	Z28.D, #80

0x4286c0 STP	X20, X17, [SP, #128]

0x4286c4 INDEX	Z14.D, X2, #1

0x4286c8 AND	X5, X5, X9

0x4286cc STP	X14, X13, [SP, #88]

0x4286d0 STP	X16, X15, [SP, #72]

0x4286d4 STP	X18, X21, [SP, #56]

0x4286d8 STP	X1, X0, [SP, #40]

0x4286dc DUP	Z26.D, X12

0x4286e0 ORR	X12, XZR, X8

0x4286e4 LDR	X8, [SP, #184]

0x4286e8 DUP	Z5.D, X13

0x4286ec ADD	X9, X2, X5

0x4286f0 ORR	X13, XZR, X27

0x4286f4 STR	X25, [SP, #120]

0x4286f8 DUP	Z6.D, X15

0x4286fc DUP	Z7.D, X21

0x428700 ORR	X15, XZR, X30

0x428704 DUP	Z16.D, X0

0x428708 STR	Z0, [X10, #511, MUL VL]

0x42870c LDR	X10, [SP, #216]

0x428710 DUP	Z17.D, X28

0x428714 DUP	Z22.D, X22

0x428718 DUP	Z24.D, X3

0x42871c ORR	X3, XZR, X19

0x428720 DUP	Z27.D, X14

0x428724 ORR	X14, XZR, X5

0x428728 ORR	X5, XZR, X23

0x42872c DUP	Z30.D, X16

0x428730 ORR	X16, XZR, X7

0x428734 DUP	Z31.D, X18

0x428738 DUP	Z8.D, X1

0x42873c DUP	Z9.D, X11

0x428740 DUP	Z11.D, X19

0x428744 DUP	Z12.D, X23

0x428748 DUP	Z13.D, X26

0x42874c DUP	Z1.D, X10

0x428750 LDR	X10, [SP, #208]

0x428754 DUP	Z0.D, X10

0x428758 SUB	X10, X29, #64

0x42875c STR	Z0, [X10, #510, MUL VL]

0x428760 DUP	Z0.D, X24

0x428764 ORR	X24, XZR, X26

0x428768 STR	Z0, [X10, #509, MUL VL]

0x42876c DUP	Z0.D, X17

0x428770 STR	Z0, [X10, #508, MUL VL]

0x428774 DUP	Z0.D, X27

0x428778 STR	Z0, [X10, #507, MUL VL]

0x42877c DUP	Z0.D, X6

0x428780 ORR	X6, XZR, X11

0x428784 STR	Z0, [X10, #506, MUL VL]

0x428788 DUP	Z0.D, X20

0x42878c STR	Z0, [X10, #505, MUL VL]

0x428790 DUP	Z0.D, X25

0x428794 STR	Z0, [X10, #504, MUL VL]

0x428798 LDR	X10, [SP, #192]

0x42879c DUP	Z23.D, X10

0x4287a0 LDR	X10, [SP, #176]

0x4287a4 DUP	Z25.D, X10

0x4287a8 ORR	X10, XZR, X14

(309) 0x4287ac MOVPRFX	Z0, Z14

(309) 0x4287b0 SDIV	Z0.D, P0/M, Z0.D, Z1.D

(309) 0x4287b4 SUB	X11, X29, #64

(309) 0x4287b8 DECD	X10, ALL

(309) 0x4287bc LDR	Z3, [X11, #510, MUL VL]

(309) 0x4287c0 LDR	Z4, [X11, #509, MUL VL]

(309) 0x4287c4 MOVPRFX	Z2, Z14

(309) 0x4287c8 MLS	Z2.D, P0/M, Z0.D, Z1.D

(309) 0x4287cc ADD	Z0.D, Z3.D, Z0.D

(309) 0x4287d0 MOVPRFX	Z15, Z0

(309) 0x4287d4 SXTW	Z15.D, P0/M, Z0.D

(309) 0x4287d8 ADD	Z0.D, Z0.D, #1

(309) 0x4287dc MUL	Z10.D, Z5.D, Z15.D

(309) 0x4287e0 MUL	Z3.D, Z6.D, Z15.D

(309) 0x4287e4 ADD	Z29.D, Z4.D, Z2.D

(309) 0x4287e8 ADR	Z2.D, [Z26, Z10.D,LSL #3]

(309) 0x4287ec ADR	Z3.D, [Z27, Z3.D,LSL #3]

(309) 0x4287f0 ADR	Z10.D, [Z2, Z29.D,SXTW #3]

(309) 0x4287f4 ADR	Z4.D, [Z3, Z29.D,SXTW #3]

(309) 0x4287f8 LD1D	{Z18.D}, P0/Z, [V10.D]

(309) 0x4287fc MOVPRFX	Z10, Z0

(309) 0x428800 SXTW	Z10.D, P0/M, Z0.D

(309) 0x428804 LD1D	{Z4.D}, P0/Z, [V4.D]

(309) 0x428808 MUL	Z0.D, Z5.D, Z10.D

(309) 0x42880c ADR	Z19.D, [Z26, Z0.D,LSL #3]

(309) 0x428810 ADR	Z0.D, [Z19, Z29.D,SXTW #3]

(309) 0x428814 LD1D	{Z20.D}, P0/Z, [V0.D]

(309) 0x428818 DUP	Z0.D, #8

(309) 0x42881c ADR	Z0.D, [Z0, Z29.D,SXTW #3]

(309) 0x428820 ADD	Z2.D, Z2.D, Z0.D

(309) 0x428824 ADD	Z19.D, Z19.D, Z0.D

(309) 0x428828 ADD	Z3.D, Z3.D, Z0.D

(309) 0x42882c LD1D	{Z21.D}, P0/Z, [V2.D]

(309) 0x428830 LD1D	{Z19.D}, P0/Z, [V19.D]

(309) 0x428834 LD1D	{Z3.D}, P0/Z, [V3.D]

(309) 0x428838 LDR	Z2, [X11, #508, MUL VL]

(309) 0x42883c FADD	Z18.D, Z18.D, Z20.D

(309) 0x428840 MUL	Z20.D, Z6.D, Z10.D

(309) 0x428844 FADD	Z4.D, Z18.D, Z4.D

(309) 0x428848 ADR	Z20.D, [Z27, Z20.D,LSL #3]

(309) 0x42884c MUL	Z2.D, Z2.D, Z15.D

(309) 0x428850 FADD	Z19.D, Z21.D, Z19.D

(309) 0x428854 ADR	Z21.D, [Z20, Z29.D,SXTW #3]

(309) 0x428858 FADD	Z3.D, Z19.D, Z3.D

(309) 0x42885c ADD	Z19.D, Z20.D, Z0.D

(309) 0x428860 MUL	Z20.D, Z16.D, Z15.D

(309) 0x428864 ADR	Z2.D, [Z25, Z2.D,LSL #3]

(309) 0x428868 LD1D	{Z21.D}, P0/Z, [V21.D]

(309) 0x42886c ADR	Z18.D, [Z2, Z29.D,SXTW #3]

(309) 0x428870 ADD	Z2.D, Z2.D, Z0.D

(309) 0x428874 LD1D	{Z19.D}, P0/Z, [V19.D]

(309) 0x428878 LD1D	{Z18.D}, P0/Z, [V18.D]

(309) 0x42887c LD1D	{Z2.D}, P0/Z, [V2.D]

(309) 0x428880 ADR	Z20.D, [Z31, Z20.D,LSL #3]

(309) 0x428884 FADD	Z4.D, Z4.D, Z21.D

(309) 0x428888 ADR	Z21.D, [Z20, Z29.D,SXTW #3]

(309) 0x42888c ADD	Z20.D, Z20.D, Z0.D

(309) 0x428890 FADD	Z3.D, Z3.D, Z19.D

(309) 0x428894 LD1D	{Z21.D}, P0/Z, [V21.D]

(309) 0x428898 LD1D	{Z20.D}, P0/Z, [V20.D]

(309) 0x42889c FMUL	Z4.D, Z18.D, Z4.D

(309) 0x4288a0 FMUL	Z2.D, Z2.D, Z3.D

(309) 0x4288a4 FMUL	Z3.D, Z4.D, Z28.D

(309) 0x4288a8 LD1RD	{Z4.D}, P0/Z, [X8]

(309) 0x4288ac FMUL	Z2.D, Z2.D, Z28.D

(309) 0x4288b0 FADD	Z20.D, Z21.D, Z20.D

(309) 0x4288b4 MUL	Z21.D, Z17.D, Z15.D

(309) 0x4288b8 FMUL	Z3.D, Z4.D, Z3.D

(309) 0x4288bc FMUL	Z2.D, Z4.D, Z2.D

(309) 0x4288c0 FSUB	Z2.D, Z2.D, Z3.D

(309) 0x4288c4 ADR	Z19.D, [Z8, Z21.D,LSL #3]

(309) 0x4288c8 ADR	Z21.D, [Z19, Z29.D,SXTW #3]

(309) 0x4288cc ADD	Z19.D, Z19.D, Z0.D

(309) 0x4288d0 LD1D	{Z21.D}, P0/Z, [V21.D]

(309) 0x4288d4 LD1D	{Z19.D}, P0/Z, [V19.D]

(309) 0x4288d8 FADD	Z20.D, Z20.D, Z21.D

(309) 0x4288dc MUL	Z21.D, Z7.D, Z15.D

(309) 0x4288e0 FADD	Z19.D, Z20.D, Z19.D

(309) 0x4288e4 MUL	Z20.D, Z16.D, Z10.D

(309) 0x4288e8 ADR	Z21.D, [Z30, Z21.D,LSL #3]

(309) 0x4288ec ADR	Z21.D, [Z21, Z29.D,SXTW #3]

(309) 0x4288f0 LD1D	{Z21.D}, P0/Z, [V21.D]

(309) 0x4288f4 FMUL	Z18.D, Z21.D, Z19.D

(309) 0x4288f8 ADR	Z19.D, [Z31, Z20.D,LSL #3]

(309) 0x4288fc MUL	Z21.D, Z17.D, Z10.D

(309) 0x428900 ADR	Z20.D, [Z19, Z29.D,SXTW #3]

(309) 0x428904 ADD	Z19.D, Z19.D, Z0.D

(309) 0x428908 FMUL	Z18.D, Z18.D, Z28.D

(309) 0x42890c FMUL	Z18.D, Z4.D, Z18.D

(309) 0x428910 LD1D	{Z20.D}, P0/Z, [V20.D]

(309) 0x428914 LD1D	{Z19.D}, P0/Z, [V19.D]

(309) 0x428918 FADD	Z19.D, Z20.D, Z19.D

(309) 0x42891c ADR	Z20.D, [Z8, Z21.D,LSL #3]

(309) 0x428920 ADR	Z21.D, [Z20, Z29.D,SXTW #3]

(309) 0x428924 ADD	Z0.D, Z20.D, Z0.D

(309) 0x428928 MUL	Z20.D, Z7.D, Z10.D

(309) 0x42892c LD1D	{Z21.D}, P0/Z, [V21.D]

(309) 0x428930 LD1D	{Z0.D}, P0/Z, [V0.D]

(309) 0x428934 ADR	Z20.D, [Z30, Z20.D,LSL #3]

(309) 0x428938 ADR	Z20.D, [Z20, Z29.D,SXTW #3]

(309) 0x42893c FADD	Z19.D, Z19.D, Z21.D

(309) 0x428940 FADD	Z0.D, Z19.D, Z0.D

(309) 0x428944 LDR	Z19, [X11, #506, MUL VL]

(309) 0x428948 LD1D	{Z20.D}, P0/Z, [V20.D]

(309) 0x42894c FMUL	Z0.D, Z20.D, Z0.D

(309) 0x428950 MUL	Z19.D, Z19.D, Z15.D

(309) 0x428954 FMUL	Z0.D, Z0.D, Z28.D

(309) 0x428958 FMUL	Z0.D, Z4.D, Z0.D

(309) 0x42895c LDR	Z4, [X11, #507, MUL VL]

(309) 0x428960 ADR	Z19.D, [Z11, Z19.D,LSL #3]

(309) 0x428964 ADR	Z3.D, [Z19, Z29.D,SXTW #3]

(309) 0x428968 LDR	Z19, [X11, #505, MUL VL]

(309) 0x42896c FADD	Z0.D, Z2.D, Z0.D

(309) 0x428970 FSUB	Z0.D, Z0.D, Z18.D

(309) 0x428974 LD1D	{Z3.D}, P0/Z, [V3.D]

(309) 0x428978 DUP	Z18.D, X15

(309) 0x42897c MUL	Z4.D, Z4.D, Z15.D

(309) 0x428980 MUL	Z19.D, Z19.D, Z15.D

(309) 0x428984 ADR	Z2.D, [Z9, Z4.D,LSL #3]

(309) 0x428988 LDR	Z4, [X11, #504, MUL VL]

(309) 0x42898c ADR	Z19.D, [Z12, Z19.D,LSL #3]

(309) 0x428990 ADR	Z2.D, [Z2, Z29.D,SXTW #3]

(309) 0x428994 ADR	Z19.D, [Z19, Z29.D,SXTW #3]

(309) 0x428998 LD1D	{Z2.D}, P0/Z, [V2.D]

(309) 0x42899c MUL	Z4.D, Z4.D, Z15.D

(309) 0x4289a0 LD1D	{Z20.D}, P0/Z, [V19.D]

(309) 0x4289a4 ADR	Z4.D, [Z13, Z4.D,LSL #3]

(309) 0x4289a8 ADR	Z4.D, [Z4, Z29.D,SXTW #3]

(309) 0x4289ac FDIV	Z3.D, P0/M, Z3.D, Z20.D

(309) 0x4289b0 LD1D	{Z4.D}, P0/Z, [V4.D]

(309) 0x4289b4 FDIV	Z4.D, P0/M, Z4.D, Z20.D

(309) 0x4289b8 FADD	Z3.D, Z3.D, Z4.D

(309) 0x4289bc MUL	Z4.D, Z22.D, Z15.D

(309) 0x4289c0 FMUL	Z3.D, Z0.D, Z3.D

(309) 0x4289c4 FADD	Z0.D, Z2.D, Z0.D

(309) 0x4289c8 FDIVR	Z0.D, P0/M, Z0.D, Z2.D

(309) 0x4289cc ADR	Z4.D, [Z18, Z4.D,LSL #3]

(309) 0x4289d0 FDUP	Z18.D, #112

(309) 0x4289d4 FDIV	Z18.D, P0/M, Z18.D, Z2.D

(309) 0x4289d8 ADR	Z4.D, [Z4, Z29.D,SXTW #3]

(309) 0x4289dc MUL	Z2.D, Z24.D, Z15.D

(309) 0x4289e0 LD1D	{Z4.D}, P0/Z, [V4.D]

(309) 0x4289e4 FMUL	Z3.D, Z18.D, Z3.D

(309) 0x4289e8 DUP	Z18.D, X12

(309) 0x4289ec FSUB	Z3.D, Z4.D, Z3.D

(309) 0x4289f0 MUL	Z4.D, Z23.D, Z15.D

(309) 0x4289f4 ADR	Z4.D, [Z18, Z4.D,LSL #3]

(309) 0x4289f8 ADR	Z4.D, [Z4, Z29.D,SXTW #3]

(309) 0x4289fc ST1D	{Z3.D}, P0, [V4.D]

(309) 0x428a00 LD1D	{Z3.D}, P0/Z, [V19.D]

(309) 0x428a04 FMUL	Z0.D, Z0.D, Z3.D

(309) 0x428a08 DUP	Z3.D, X16

(309) 0x428a0c ADR	Z2.D, [Z3, Z2.D,LSL #3]

(309) 0x428a10 ADR	Z2.D, [Z2, Z29.D,SXTW #3]

(309) 0x428a14 ST1D	{Z0.D}, P0, [V2.D]

(309) 0x428a18 LDR	Z0, [X11, #511, MUL VL]

(309) 0x428a1c ADD	Z14.D, Z14.D, Z0.D

(309) 0x428a20 CBNZ	X10, 4287ac

0x428a24 LDR	X8, [SP, #24]

0x428a28 LDP	X20, X17, [SP, #128]

0x428a2c ORR	X11, XZR, X6

0x428a30 ORR	X27, XZR, X13

0x428a34 ORR	X19, XZR, X3

0x428a38 ORR	X23, XZR, X5

0x428a3c ORR	X26, XZR, X24

0x428a40 LDP	X22, X25, [SP, #112]

0x428a44 ORR	X30, XZR, X15

0x428a48 ORR	X7, XZR, X16

0x428a4c LDP	X21, X16, [SP, #64]

0x428a50 LDP	X0, X18, [SP, #48]

0x428a54 LDP	X28, X1, [SP, #32]

0x428a58 LDR	X4, [SP, #152]

0x428a5c CMP	X8, X14

0x428a60 ORR	X8, XZR, X12

0x428a64 LDP	X13, X12, [SP, #96]

0x428a68 LDP	X15, X14, [SP, #80]

0x428a6c B.EQ	428ccc

0x428a70 LDR	X2, [SP, #216]

0x428a74 FMOV	D0, #0.2500000

0x428a78 FMOV	D1, #-1.0000000

0x428a7c ADD	X10, X4, #1

0x428a80 STR	X10, [SP, #152]

0x428a84 SUB	W24, WZR, W2

(308) 0x428a88 LDP	X3, X2, [SP, #208]

(308) 0x428a8c ORR	X10, XZR, X22

(308) 0x428a90 ORR	X22, XZR, X25

(308) 0x428a94 ORR	X25, XZR, X20

(308) 0x428a98 ORR	X20, XZR, X27

(308) 0x428a9c ORR	X27, XZR, X7

(308) 0x428aa0 ORR	X7, XZR, X17

(308) 0x428aa4 SDIV	X2, X9, X2

(308) 0x428aa8 ADD	W5, W3, W2

(308) 0x428aac LDR	X3, [SP, #200]

(308) 0x428ab0 ADD	W3, W3, W9

(308) 0x428ab4 ADD	X9, X9, #1

(308) 0x428ab8 MADD	W4, W24, W2, W3

(308) 0x428abc SBFM	X3, X5, #0, #31

(308) 0x428ac0 ADD	W5, W5, #1

(308) 0x428ac4 MADD	X6, X17, X3, XZR

(308) 0x428ac8 ORR	X17, XZR, X26

(308) 0x428acc ORR	X26, XZR, X30

(308) 0x428ad0 ORR	X30, XZR, X23

(308) 0x428ad4 ORR	X23, XZR, X19

(308) 0x428ad8 ORR	X19, XZR, X11

(308) 0x428adc ORR	X11, XZR, X8

(308) 0x428ae0 LDR	X8, [SP, #176]

(308) 0x428ae4 SBFM	X5, X5, #0, #31

(308) 0x428ae8 ADD	W2, W4, #1

(308) 0x428aec ADD	W4, W4, #2

(308) 0x428af0 ADD	X6, X8, X6,LSL #3

(308) 0x428af4 ORR	X8, XZR, X11

(308) 0x428af8 ORR	X11, XZR, X19

(308) 0x428afc ORR	X19, XZR, X23

(308) 0x428b00 ORR	X23, XZR, X30

(308) 0x428b04 ORR	X30, XZR, X26

(308) 0x428b08 ORR	X26, XZR, X17

(308) 0x428b0c ORR	X17, XZR, X7

(308) 0x428b10 ORR	X7, XZR, X27

(308) 0x428b14 ORR	X27, XZR, X20

(308) 0x428b18 ORR	X20, XZR, X25

(308) 0x428b1c ORR	X25, XZR, X22

(308) 0x428b20 ORR	X22, XZR, X10

(308) 0x428b24 LDR	D2, [X6, X2,SXTW #3]

(308) 0x428b28 LDR	D3, [X6, X4,SXTW #3]

(308) 0x428b2c MADD	X6, X13, X3, XZR

(308) 0x428b30 ADD	X6, X12, X6,LSL #3

(308) 0x428b34 LDR	D4, [X6, X2,SXTW #3]

(308) 0x428b38 LDR	D5, [X6, X4,SXTW #3]

(308) 0x428b3c MADD	X6, X13, X5, XZR

(308) 0x428b40 ADD	X6, X12, X6,LSL #3

(308) 0x428b44 LDR	D6, [X6, X2,SXTW #3]

(308) 0x428b48 LDR	D7, [X6, X4,SXTW #3]

(308) 0x428b4c MADD	X6, X15, X3, XZR

(308) 0x428b50 ADD	X6, X14, X6,LSL #3

(308) 0x428b54 LDR	D16, [X6, X2,SXTW #3]

(308) 0x428b58 LDR	D17, [X6, X4,SXTW #3]

(308) 0x428b5c MADD	X6, X15, X5, XZR

(308) 0x428b60 ADD	X6, X14, X6,LSL #3

(308) 0x428b64 LDR	D18, [X6, X2,SXTW #3]

(308) 0x428b68 LDR	D19, [X6, X4,SXTW #3]

(308) 0x428b6c MADD	X6, X21, X3, XZR

(308) 0x428b70 FADD	D4, D4, D6

(308) 0x428b74 ADD	X6, X16, X6,LSL #3

(308) 0x428b78 LDR	D20, [X6, X2,SXTW #3]

(308) 0x428b7c MADD	X6, X0, X3, XZR

(308) 0x428b80 FADD	D4, D4, D16

(308) 0x428b84 ADD	X6, X18, X6,LSL #3

(308) 0x428b88 LDR	D21, [X6, X2,SXTW #3]

(308) 0x428b8c LDR	D22, [X6, X4,SXTW #3]

(308) 0x428b90 MADD	X6, X28, X3, XZR

(308) 0x428b94 FADD	D4, D4, D18

(308) 0x428b98 ADD	X6, X1, X6,LSL #3

(308) 0x428b9c FMUL	D2, D2, D4

(308) 0x428ba0 FADD	D4, D5, D7

(308) 0x428ba4 LDR	D23, [X6, X2,SXTW #3]

(308) 0x428ba8 LDR	D24, [X6, X4,SXTW #3]

(308) 0x428bac MADD	X6, X21, X5, XZR

(308) 0x428bb0 FADD	D4, D4, D17

(308) 0x428bb4 ADD	X6, X16, X6,LSL #3

(308) 0x428bb8 FMUL	D2, D2, D0

(308) 0x428bbc LDR	D25, [X6, X2,SXTW #3]

(308) 0x428bc0 MADD	X6, X0, X5, XZR

(308) 0x428bc4 MADD	X5, X28, X5, XZR

(308) 0x428bc8 FADD	D4, D4, D19

(308) 0x428bcc ADD	X6, X18, X6,LSL #3

(308) 0x428bd0 ADD	X5, X1, X5,LSL #3

(308) 0x428bd4 FMUL	D3, D3, D4

(308) 0x428bd8 FADD	D4, D21, D22

(308) 0x428bdc LDR	D26, [X6, X2,SXTW #3]

(308) 0x428be0 LDR	D27, [X6, X4,SXTW #3]

(308) 0x428be4 LDR	D7, [X5, X2,SXTW #3]

(308) 0x428be8 LDR	X6, [SP, #184]

(308) 0x428bec FADD	D4, D4, D23

(308) 0x428bf0 FMUL	D3, D3, D0

(308) 0x428bf4 FADD	D4, D4, D24

(308) 0x428bf8 LDR	D5, [X6]

(308) 0x428bfc FMUL	D4, D20, D4

(308) 0x428c00 FADD	D6, D26, D27

(308) 0x428c04 FADD	D6, D6, D7

(308) 0x428c08 LDR	D7, [X5, X4,SXTW #3]

(308) 0x428c0c MADD	X4, X27, X3, XZR

(308) 0x428c10 FMUL	D4, D4, D0

(308) 0x428c14 MADD	X5, X25, X3, XZR

(308) 0x428c18 FMUL	D2, D5, D2

(308) 0x428c1c FMUL	D3, D5, D3

(308) 0x428c20 ADD	X4, X11, X4,LSL #3

(308) 0x428c24 ADD	X5, X26, X5,LSL #3

(308) 0x428c28 FMUL	D4, D5, D4

(308) 0x428c2c FSUB	D2, D3, S2

(308) 0x428c30 LDR	D3, [X4, X2,SXTW #3]

(308) 0x428c34 LDR	X4, [SP, #168]

(308) 0x428c38 FADD	D6, D6, D7

(308) 0x428c3c LDR	D7, [X5, X2,SXTW #3]

(308) 0x428c40 MADD	X5, X10, X3, XZR

(308) 0x428c44 LDR	X10, [SP, #192]

(308) 0x428c48 FMUL	D6, D25, D6

(308) 0x428c4c ADD	X5, X30, X5,LSL #3

(308) 0x428c50 MADD	X4, X4, X3, XZR

(308) 0x428c54 FMUL	D6, D6, D0

(308) 0x428c58 ADD	X4, X19, X4,LSL #3

(308) 0x428c5c FMUL	D5, D5, D6

(308) 0x428c60 FADD	D2, D2, D5

(308) 0x428c64 FDIV	D5, D1, D3

(308) 0x428c68 FSUB	D2, D2, S4

(308) 0x428c6c LDR	D4, [X4, X2,SXTW #3]

(308) 0x428c70 MADD	X4, X20, X3, XZR

(308) 0x428c74 ADD	X4, X23, X4,LSL #3

(308) 0x428c78 LDR	D6, [X4, X2,SXTW #3]

(308) 0x428c7c FDIV	D4, D4, D6

(308) 0x428c80 FDIV	D6, D7, D6

(308) 0x428c84 FADD	D4, D4, D6

(308) 0x428c88 FMUL	D4, D2, D4

(308) 0x428c8c FADD	D2, D3, D2

(308) 0x428c90 FDIV	D2, D3, D2

(308) 0x428c94 FMUL	D4, D5, D4

(308) 0x428c98 LDR	D5, [X5, X2,SXTW #3]

(308) 0x428c9c MADD	X5, X10, X3, XZR

(308) 0x428ca0 ADD	X5, X8, X5,LSL #3

(308) 0x428ca4 FADD	D4, D5, D4

(308) 0x428ca8 STR	D4, [X5, X2,SXTW #3]

(308) 0x428cac LDR	D4, [X4, X2,SXTW #3]

(308) 0x428cb0 LDP	X10, X4, [SP, #152]

(308) 0x428cb4 MADD	X3, X4, X3, XZR

(308) 0x428cb8 FMUL	D2, D2, D4

(308) 0x428cbc ADD	X3, X7, X3,LSL #3

(308) 0x428cc0 STR	D2, [X3, X2,SXTW #3]

(308) 0x428cc4 CMP	X10, X9

(308) 0x428cc8 B.NE	428a88

0x428ccc LDR	W1, [SP, #148]

0x428cd0 ADRP	X0,

0x428cd4 ADD	X0, X0, #2512

0x428cd8 BL	402cc0

0x428cdc ADDVL	SP, SP, #8

0x428ce0 ADD	SP, SP, #256

0x428ce4 LDP	D9, D8, [SP, #48]

0x428ce8 LDP	D11, D10, [SP, #32]

0x428cec LDP	D13, D12, [SP, #16]

0x428cf0 LDP	X20, X19, [SP, #144]

0x428cf4 LDP	X22, X21, [SP, #128]

0x428cf8 LDP	X24, X23, [SP, #112]

0x428cfc LDP	X26, X25, [SP, #96]

0x428d00 LDP	X28, X27, [SP, #80]

0x428d04 LDP	X29, X30, [SP, #64]

0x428d08 LDP	D15, D14, [SP], #160

0x428d0c RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.17 to 27.00 cycles (1.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 65% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 35.17 to 29.58 cycles (1.19x speedup).

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

12% of VPU loads are used in vector version.
30% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.17 to 1.00 cycles (35.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 688 bytes. The binary function is storing 528 bytes.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	13.08	12.92	13.00	13.00	28.00	13.00	6.00	6.00	2.00	2.00	35.17	34.83	35.00	13.50	13.50
cycles	3.50	3.50	13.08	12.92	13.00	13.00	28.00	13.00	6.00	6.00	2.00	2.00	35.17	34.83	35.00	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Overall L1	35.17

Vectorization ratios

INT

all	14%
load	12%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	12%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.17 cycles. At this rate:

20% of peak load performance is reached (19.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.01 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #56	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W24, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 428cdc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W10, W9, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d594>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2488	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #228	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X22, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UMADDL X19, W10, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X19, XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W1, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X2, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 428ccc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X11, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X3, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X5, X4, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X7, X6, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X0, X19, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X28, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X10, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X9, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X9, X4, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X3, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X5, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 428a70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X9, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X22, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X28, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FDUP Z28.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X20, X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
INDEX Z14.D, X2, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
AND X5, X5, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X14, X13, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X16, X15, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X21, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X1, X0, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
DUP Z26.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X12, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z5.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ADD X9, X2, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP Z6.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z7.D, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X15, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z16.D, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z17.D, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z22.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z24.D, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X3, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z27.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X14, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z30.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X16, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z31.D, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z8.D, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z9.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z11.D, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z12.D, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z13.D, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z1.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X10, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X10, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X24, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X10, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X6, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X10, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z23.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z25.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X10, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X11, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X27, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X22, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X30, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X7, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X16, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X0, X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR X8, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X13, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X14, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B.EQ 428ccc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W24, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W1, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46dcd0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2512	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD SP, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP D15, D14, [SP], #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

13% of VPU instructions are used in vector version (process two or more data elements in vector registers):

12% of VPU loads are used in vector version.
30% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.17 to 1.00 cycles (35.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 688 bytes. The binary function is storing 528 bytes.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	13.08	12.92	13.00	13.00	28.00	13.00	6.00	6.00	2.00	2.00	35.17	34.83	35.00	13.50	13.50
cycles	3.50	3.50	13.08	12.92	13.00	13.00	28.00	13.00	6.00	6.00	2.00	2.00	35.17	34.83	35.00	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Overall L1	35.17

Vectorization ratios

INT

all	14%
load	12%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	13%
load	12%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.17 cycles. At this rate:

20% of peak load performance is reached (19.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.01 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 428520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #56	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W24, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 428cdc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W10, W9, W24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46d594>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2488	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #228	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X22, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
UMADDL X19, W10, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X19, XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR W1, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X2, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X2, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 428ccc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X11, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X3, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X5, X4, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X7, X6, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X0, X19, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X28, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X19, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X10, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X9, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X9, X4, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X3, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X5, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 428a70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X9, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X22, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X28, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FDUP Z28.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X20, X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
INDEX Z14.D, X2, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
AND X5, X5, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X14, X13, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X16, X15, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X21, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X1, X0, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
DUP Z26.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X12, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z5.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ADD X9, X2, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP Z6.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z7.D, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X15, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z16.D, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z17.D, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z22.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z24.D, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X3, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z27.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X14, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z30.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X16, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z31.D, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z8.D, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z9.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z11.D, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z12.D, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z13.D, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z1.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X10, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X10, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X24	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X24, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X10, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X6, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X10, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X10, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z23.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z25.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X10, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X11, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X27, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X22, X25, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X30, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X7, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X16, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X0, X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR X8, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X13, X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X14, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B.EQ 428ccc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W24, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W1, [SP, #148]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <46dcd0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2512	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD SP, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP D15, D14, [SP], #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.90	5.75
○Loop 309 - PdV.cpp:70-83 - exec	6.90	5.71
○Loop 308 - PdV.cpp:70-83 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code