OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 5.42% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x427e70 STP	D15, D14, [SP, #864]!

0x427e74 STP	D13, D12, [SP, #16]

0x427e78 STP	D11, D10, [SP, #32]

0x427e7c STP	D9, D8, [SP, #48]

0x427e80 STP	X29, X30, [SP, #64]

0x427e84 STP	X28, X27, [SP, #80]

0x427e88 STP	X26, X25, [SP, #96]

0x427e8c STP	X24, X23, [SP, #112]

0x427e90 STP	X22, X21, [SP, #128]

0x427e94 STP	X20, X19, [SP, #144]

0x427e98 ADD	X29, SP, #64

0x427e9c SUB	SP, SP, #144

0x427ea0 ADDVL	SP, SP, #57

0x427ea4 LDR	W8, [X2]

0x427ea8 LDR	W21, [X4]

0x427eac LDR	W9, [X5]

0x427eb0 ADD	W10, W8, #1

0x427eb4 LDR	W8, [X3]

0x427eb8 ADD	W19, W21, #1

0x427ebc ADD	W9, W9, #2

0x427ec0 ADD	W8, W8, #2

0x427ec4 SUBS	W8, W8, W10

0x427ec8 CCMP	W9, W19, #4, #12

0x427ecc B.LE	4284e4

0x427ed0 LDR	W1, [X0]

0x427ed4 SUB	W25, W9, W19

0x427ed8 MOVN	X9, #0

0x427edc ORR	X20, XZR, X7

0x427ee0 ORR	X23, XZR, X6

0x427ee4 ADRP	X0,

0x427ee8 ADD	X0, X0, #2416

0x427eec ADD	X3, SP, #116

0x427ef0 ADD	X4, SP, #136

0x427ef4 STR	WZR, [SP, #116]

0x427ef8 STR	X10, [SP, #104]

0x427efc STR	W1, [SP, #76]

0x427f00 UMADDL	X24, W25, W8, X9

0x427f04 MOVZ	W8, #1

0x427f08 ADD	X5, SP, #128

0x427f0c ADD	X6, SP, #120

0x427f10 MOVZ	W2, #34

0x427f14 MOVZ	W7, #1

0x427f18 STP	X24, XZR, [SP, #128]

0x427f1c STR	X8, [SP, #120]

0x427f20 STR	X8, [SP]

0x427f24 BL	402e00

0x427f28 LDR	X8, [SP, #128]

0x427f2c CMP	X8, X24

0x427f30 CSEL	X8, X8, X24, #11

0x427f34 LDR	X24, [SP, #136]

0x427f38 CMP	X24, X8

0x427f3c B.GT	4284d4

0x427f40 LDP	X7, X30, [X29, #144]

0x427f44 LDP	X1, X27, [X29, #128]

0x427f48 LDP	X9, X22, [X29, #160]

0x427f4c ORR	X10, XZR, X25

0x427f50 STR	X8, [SP, #64]

0x427f54 LDP	X16, X18, [X29, #112]

0x427f58 LDP	X8, X14, [X29, #96]

0x427f5c LDR	X11, [X20, #16]

0x427f60 LDR	X12, [X20]

0x427f64 LDR	X0, [X23, #16]

0x427f68 LDR	X17, [X23]

0x427f6c LDR	X4, [X1, #16]

0x427f70 LDR	X5, [X1]

0x427f74 LDR	X20, [X7, #16]

0x427f78 LDR	X1, [X7]

0x427f7c LDR	X7, [X30, #16]

0x427f80 LDR	X26, [X30]

0x427f84 LDR	X30, [SP, #64]

0x427f88 STR	X8, [SP, #96]

0x427f8c ORR	X8, XZR, X22

0x427f90 LDR	X13, [X14, #16]

0x427f94 LDR	X14, [X14]

0x427f98 LDR	X15, [X16, #16]

0x427f9c LDR	X16, [X16]

0x427fa0 LDR	X2, [X18, #16]

0x427fa4 LDR	X3, [X18]

0x427fa8 LDR	X6, [X27, #16]

0x427fac LDR	X18, [X27]

0x427fb0 ORR	X27, XZR, X24

0x427fb4 LDR	X25, [X9, #16]

0x427fb8 LDR	X23, [X9]

0x427fbc SUB	X9, X30, X24

0x427fc0 ADD	X28, X9, #1

0x427fc4 LDR	X22, [X22, #16]

0x427fc8 LDR	X8, [X8]

0x427fcc CNTD	X9, ALL

0x427fd0 STP	X1, X18, [SP, #80]

0x427fd4 CMP	X28, X9

0x427fd8 B.CC	42830c

0x427fdc DUP	Z0.D, X9

0x427fe0 SUB	X27, XZR, X9

0x427fe4 SUB	X9, X29, #64

0x427fe8 STP	X21, X8, [SP, #16]

0x427fec ORR	X21, XZR, X28

0x427ff0 PTRUE	P0.D, ALL

0x427ff4 FDUP	Z25.D, #80

0x427ff8 STP	X5, X3, [SP, #48]

0x427ffc INDEX	Z13.D, X24, #1

0x428000 AND	X28, X28, X27

0x428004 STP	X26, X23, [SP, #32]

0x428008 ADD	X27, X24, X28

0x42800c STR	Z0, [X9, #511, MUL VL]

0x428010 DUP	Z22.D, X8

0x428014 LDP	X8, X9, [SP, #96]

0x428018 DUP	Z1.D, X10

0x42801c DUP	Z5.D, X12

0x428020 DUP	Z6.D, X14

0x428024 DUP	Z7.D, X16

0x428028 DUP	Z19.D, X1

0x42802c ORR	X1, XZR, X6

0x428030 DUP	Z20.D, X23

0x428034 ORR	X23, XZR, X4

0x428038 DUP	Z21.D, X26

0x42803c DUP	Z23.D, X0

0x428040 DUP	Z24.D, X11

0x428044 DUP	Z27.D, X13

0x428048 DUP	Z28.D, X15

0x42804c DUP	Z29.D, X2

0x428050 DUP	Z31.D, X4

0x428054 DUP	Z8.D, X6

0x428058 DUP	Z9.D, X20

0x42805c DUP	Z10.D, X25

0x428060 DUP	Z11.D, X7

0x428064 DUP	Z12.D, X22

0x428068 DUP	Z0.D, X9

0x42806c SUB	X9, X29, #64

0x428070 STR	Z0, [X9, #510, MUL VL]

0x428074 DUP	Z0.D, X19

0x428078 ORR	X19, XZR, X7

0x42807c STR	Z0, [X9, #509, MUL VL]

0x428080 DUP	Z0.D, X17

0x428084 STR	Z0, [X9, #508, MUL VL]

0x428088 DUP	Z0.D, X3

0x42808c ORR	X3, XZR, X0

0x428090 ORR	X0, XZR, X28

0x428094 ORR	X28, XZR, X22

0x428098 ORR	X30, XZR, X0

0x42809c STR	Z0, [X9, #507, MUL VL]

0x4280a0 DUP	Z0.D, X5

0x4280a4 ORR	X5, XZR, X2

0x4280a8 STR	Z0, [X9, #506, MUL VL]

0x4280ac DUP	Z0.D, X18

0x4280b0 ORR	X18, XZR, X25

0x4280b4 STR	Z0, [X9, #505, MUL VL]

0x4280b8 ORR	X9, XZR, X20

0x4280bc HINT	#0

(307) 0x4280c0 MOVPRFX	Z26, Z13

(307) 0x4280c4 SDIV	Z26.D, P0/M, Z26.D, Z1.D

(307) 0x4280c8 SUB	X20, X29, #64

(307) 0x4280cc DECD	X30, ALL

(307) 0x4280d0 LDR	Z0, [X20, #510, MUL VL]

(307) 0x4280d4 LDR	Z2, [X20, #509, MUL VL]

(307) 0x4280d8 ADD	Z30.D, Z0.D, Z26.D

(307) 0x4280dc LDR	Z0, [X20, #508, MUL VL]

(307) 0x4280e0 MSB	Z26.D, P0/M, Z1.D, Z13.D

(307) 0x4280e4 MOVPRFX	Z15, Z30

(307) 0x4280e8 SXTW	Z15.D, P0/M, Z30.D

(307) 0x4280ec ADD	Z30.D, Z30.D, #1

(307) 0x4280f0 MUL	Z18.D, Z6.D, Z15.D

(307) 0x4280f4 ADD	Z14.D, Z2.D, Z26.D

(307) 0x4280f8 MUL	Z0.D, Z0.D, Z15.D

(307) 0x4280fc ADR	Z18.D, [Z27, Z18.D,LSL #3]

(307) 0x428100 ADR	Z0.D, [Z23, Z0.D,LSL #3]

(307) 0x428104 ADR	Z18.D, [Z18, Z14.D,SXTW #3]

(307) 0x428108 ADR	Z26.D, [Z0, Z14.D,SXTW #3]

(307) 0x42810c LD1D	{Z18.D}, P0/Z, [V18.D]

(307) 0x428110 LD1D	{Z2.D}, P0/Z, [V26.D]

(307) 0x428114 MUL	Z26.D, Z5.D, Z15.D

(307) 0x428118 ADR	Z3.D, [Z24, Z26.D,LSL #3]

(307) 0x42811c ADR	Z26.D, [Z3, Z14.D,SXTW #3]

(307) 0x428120 LD1D	{Z4.D}, P0/Z, [V26.D]

(307) 0x428124 MOVPRFX	Z26, Z30

(307) 0x428128 SXTW	Z26.D, P0/M, Z30.D

(307) 0x42812c MUL	Z30.D, Z5.D, Z26.D

(307) 0x428130 ADR	Z30.D, [Z24, Z30.D,LSL #3]

(307) 0x428134 ADR	Z16.D, [Z30, Z14.D,SXTW #3]

(307) 0x428138 LD1D	{Z16.D}, P0/Z, [V16.D]

(307) 0x42813c FADD	Z17.D, Z4.D, Z16.D

(307) 0x428140 FADD	Z4.D, Z4.D, Z17.D

(307) 0x428144 DUP	Z17.D, #8

(307) 0x428148 ADR	Z17.D, [Z17, Z14.D,SXTW #3]

(307) 0x42814c FADD	Z4.D, Z16.D, Z4.D

(307) 0x428150 ADD	Z3.D, Z3.D, Z17.D

(307) 0x428154 ADD	Z30.D, Z30.D, Z17.D

(307) 0x428158 FMUL	Z2.D, Z2.D, Z4.D

(307) 0x42815c MUL	Z4.D, Z7.D, Z15.D

(307) 0x428160 ADD	Z0.D, Z0.D, Z17.D

(307) 0x428164 LD1D	{Z3.D}, P0/Z, [V3.D]

(307) 0x428168 LD1D	{Z16.D}, P0/Z, [V30.D]

(307) 0x42816c LD1D	{Z0.D}, P0/Z, [V0.D]

(307) 0x428170 FMUL	Z2.D, Z2.D, Z25.D

(307) 0x428174 ADR	Z4.D, [Z28, Z4.D,LSL #3]

(307) 0x428178 FADD	Z30.D, Z3.D, Z16.D

(307) 0x42817c FADD	Z3.D, Z3.D, Z30.D

(307) 0x428180 ADR	Z30.D, [Z4, Z14.D,SXTW #3]

(307) 0x428184 ADD	Z4.D, Z4.D, Z17.D

(307) 0x428188 LD1D	{Z30.D}, P0/Z, [V30.D]

(307) 0x42818c LD1D	{Z4.D}, P0/Z, [V4.D]

(307) 0x428190 FADD	Z3.D, Z16.D, Z3.D

(307) 0x428194 FMUL	Z0.D, Z0.D, Z3.D

(307) 0x428198 FMUL	Z0.D, Z0.D, Z25.D

(307) 0x42819c FADD	Z16.D, Z30.D, Z4.D

(307) 0x4281a0 FADD	Z16.D, Z30.D, Z16.D

(307) 0x4281a4 FADD	Z4.D, Z4.D, Z16.D

(307) 0x4281a8 MUL	Z16.D, Z7.D, Z26.D

(307) 0x4281ac FMUL	Z4.D, Z18.D, Z4.D

(307) 0x4281b0 ADR	Z16.D, [Z28, Z16.D,LSL #3]

(307) 0x4281b4 FMUL	Z4.D, Z4.D, Z25.D

(307) 0x4281b8 ADD	Z17.D, Z16.D, Z17.D

(307) 0x4281bc ADR	Z16.D, [Z16, Z14.D,SXTW #3]

(307) 0x4281c0 LD1D	{Z16.D}, P0/Z, [V16.D]

(307) 0x4281c4 LD1D	{Z3.D}, P0/Z, [V17.D]

(307) 0x4281c8 FADD	Z17.D, Z16.D, Z3.D

(307) 0x4281cc FADD	Z16.D, Z16.D, Z17.D

(307) 0x4281d0 MUL	Z17.D, Z6.D, Z26.D

(307) 0x4281d4 FADD	Z3.D, Z3.D, Z16.D

(307) 0x4281d8 LD1RD	{Z16.D}, P0/Z, [X8]

(307) 0x4281dc ADR	Z17.D, [Z27, Z17.D,LSL #3]

(307) 0x4281e0 ADR	Z17.D, [Z17, Z14.D,SXTW #3]

(307) 0x4281e4 FMUL	Z2.D, Z16.D, Z2.D

(307) 0x4281e8 FMUL	Z0.D, Z16.D, Z0.D

(307) 0x4281ec FMUL	Z4.D, Z16.D, Z4.D

(307) 0x4281f0 LD1D	{Z17.D}, P0/Z, [V17.D]

(307) 0x4281f4 FMUL	Z2.D, P0/M, Z2.D, #0

(307) 0x4281f8 FMUL	Z0.D, P0/M, Z0.D, #0

(307) 0x4281fc FMUL	Z4.D, P0/M, Z4.D, #0

(307) 0x428200 FSUB	Z0.D, Z0.D, Z2.D

(307) 0x428204 LDR	Z2, [X20, #507, MUL VL]

(307) 0x428208 FMUL	Z3.D, Z17.D, Z3.D

(307) 0x42820c MUL	Z17.D, Z19.D, Z15.D

(307) 0x428210 MUL	Z2.D, Z2.D, Z15.D

(307) 0x428214 FMUL	Z3.D, Z3.D, Z25.D

(307) 0x428218 ADR	Z17.D, [Z9, Z17.D,LSL #3]

(307) 0x42821c FMUL	Z3.D, Z16.D, Z3.D

(307) 0x428220 LDR	Z16, [X20, #505, MUL VL]

(307) 0x428224 ADR	Z17.D, [Z17, Z14.D,SXTW #3]

(307) 0x428228 ADR	Z2.D, [Z29, Z2.D,LSL #3]

(307) 0x42822c FMUL	Z3.D, P0/M, Z3.D, #0

(307) 0x428230 LD1D	{Z17.D}, P0/Z, [V17.D]

(307) 0x428234 ADR	Z2.D, [Z2, Z14.D,SXTW #3]

(307) 0x428238 FADD	Z0.D, Z0.D, Z3.D

(307) 0x42823c LDR	Z3, [X20, #506, MUL VL]

(307) 0x428240 MUL	Z16.D, Z16.D, Z15.D

(307) 0x428244 LD1D	{Z2.D}, P0/Z, [V2.D]

(307) 0x428248 FSUB	Z0.D, Z0.D, Z4.D

(307) 0x42824c ADR	Z16.D, [Z8, Z16.D,LSL #3]

(307) 0x428250 MUL	Z3.D, Z3.D, Z15.D

(307) 0x428254 ADR	Z4.D, [Z16, Z14.D,SXTW #3]

(307) 0x428258 LD1D	{Z16.D}, P0/Z, [V4.D]

(307) 0x42825c ADR	Z3.D, [Z31, Z3.D,LSL #3]

(307) 0x428260 ADR	Z3.D, [Z3, Z14.D,SXTW #3]

(307) 0x428264 LD1D	{Z3.D}, P0/Z, [V3.D]

(307) 0x428268 FDIV	Z3.D, P0/M, Z3.D, Z16.D

(307) 0x42826c FDIVR	Z16.D, P0/M, Z16.D, Z17.D

(307) 0x428270 FADD	Z3.D, Z3.D, Z16.D

(307) 0x428274 FDUP	Z16.D, #112

(307) 0x428278 FDIV	Z16.D, P0/M, Z16.D, Z2.D

(307) 0x42827c FMUL	Z3.D, Z0.D, Z3.D

(307) 0x428280 FADD	Z0.D, Z2.D, Z0.D

(307) 0x428284 FDIVR	Z0.D, P0/M, Z0.D, Z2.D

(307) 0x428288 FMUL	Z3.D, Z16.D, Z3.D

(307) 0x42828c MUL	Z16.D, Z20.D, Z15.D

(307) 0x428290 ADR	Z16.D, [Z10, Z16.D,LSL #3]

(307) 0x428294 ADR	Z16.D, [Z16, Z14.D,SXTW #3]

(307) 0x428298 LD1D	{Z16.D}, P0/Z, [V16.D]

(307) 0x42829c FSUB	Z3.D, Z16.D, Z3.D

(307) 0x4282a0 MUL	Z16.D, Z21.D, Z15.D

(307) 0x4282a4 ADR	Z16.D, [Z11, Z16.D,LSL #3]

(307) 0x4282a8 ADR	Z16.D, [Z16, Z14.D,SXTW #3]

(307) 0x4282ac ST1D	{Z3.D}, P0, [V16.D]

(307) 0x4282b0 LD1D	{Z2.D}, P0/Z, [V4.D]

(307) 0x4282b4 FMUL	Z0.D, Z0.D, Z2.D

(307) 0x4282b8 MUL	Z2.D, Z22.D, Z15.D

(307) 0x4282bc ADR	Z2.D, [Z12, Z2.D,LSL #3]

(307) 0x4282c0 ADR	Z2.D, [Z2, Z14.D,SXTW #3]

(307) 0x4282c4 ST1D	{Z0.D}, P0, [V2.D]

(307) 0x4282c8 LDR	Z0, [X20, #511, MUL VL]

(307) 0x4282cc ADD	Z13.D, Z13.D, Z0.D

(307) 0x4282d0 CBNZ	X30, 4280c0

0x4282d4 ORR	X2, XZR, X5

0x4282d8 ORR	X4, XZR, X23

0x4282dc ORR	X6, XZR, X1

0x4282e0 ORR	X20, XZR, X9

0x4282e4 ORR	X25, XZR, X18

0x4282e8 LDP	X26, X23, [SP, #32]

0x4282ec ORR	X7, XZR, X19

0x4282f0 ORR	X22, XZR, X28

0x4282f4 LDR	X30, [SP, #64]

0x4282f8 CMP	X21, X0

0x4282fc ORR	X0, XZR, X3

0x428300 LDP	X5, X3, [SP, #48]

0x428304 LDP	X21, X8, [SP, #16]

0x428308 B.EQ	4284d4

0x42830c FMOV	D0, #0.2500000

0x428310 FMOV	D1, #0.5000000

0x428314 FMOV	D2, #-1.0000000

0x428318 ADD	X28, X30, #1

0x42831c SUB	W30, WZR, W10

(306) 0x428320 SDIV	X9, X27, X10

(306) 0x428324 ORR	X18, XZR, X10

(306) 0x428328 LDR	X10, [SP, #104]

(306) 0x42832c ADD	W19, W21, W27

(306) 0x428330 ORR	X1, XZR, X17

(306) 0x428334 ADD	X27, X27, #1

(306) 0x428338 ADD	W10, W10, W9

(306) 0x42833c MADD	W9, W30, W9, W19

(306) 0x428340 SBFM	X24, X10, #0, #31

(306) 0x428344 ADD	W10, W10, #1

(306) 0x428348 MADD	X17, X17, X24, XZR

(306) 0x42834c ADD	W19, W9, #1

(306) 0x428350 ADD	W9, W9, #2

(306) 0x428354 SBFM	X10, X10, #0, #31

(306) 0x428358 ADD	X17, X0, X17,LSL #3

(306) 0x42835c LDR	D3, [X17, X19,SXTW #3]

(306) 0x428360 LDR	D4, [X17, X9,SXTW #3]

(306) 0x428364 MADD	X17, X12, X24, XZR

(306) 0x428368 ADD	X17, X11, X17,LSL #3

(306) 0x42836c LDR	D5, [X17, X19,SXTW #3]

(306) 0x428370 LDR	D6, [X17, X9,SXTW #3]

(306) 0x428374 MADD	X17, X12, X10, XZR

(306) 0x428378 ADD	X17, X11, X17,LSL #3

(306) 0x42837c LDR	D7, [X17, X19,SXTW #3]

(306) 0x428380 LDR	D16, [X17, X9,SXTW #3]

(306) 0x428384 MADD	X17, X14, X24, XZR

(306) 0x428388 ADD	X17, X13, X17,LSL #3

(306) 0x42838c LDR	D17, [X17, X19,SXTW #3]

(306) 0x428390 MADD	X17, X16, X24, XZR

(306) 0x428394 ADD	X17, X15, X17,LSL #3

(306) 0x428398 FADD	D21, D5, D7

(306) 0x42839c LDR	D18, [X17, X19,SXTW #3]

(306) 0x4283a0 LDR	D19, [X17, X9,SXTW #3]

(306) 0x4283a4 MADD	X17, X14, X10, XZR

(306) 0x4283a8 MADD	X10, X16, X10, XZR

(306) 0x4283ac FADD	D5, D5, D21

(306) 0x4283b0 ADD	X10, X15, X10,LSL #3

(306) 0x4283b4 ADD	X17, X13, X17,LSL #3

(306) 0x4283b8 LDR	D20, [X17, X19,SXTW #3]

(306) 0x4283bc ORR	X17, XZR, X1

(306) 0x4283c0 LDR	X1, [SP, #96]

(306) 0x4283c4 FADD	D5, D7, D5

(306) 0x4283c8 LDR	D7, [X10, X19,SXTW #3]

(306) 0x4283cc FMUL	D3, D3, D5

(306) 0x4283d0 FADD	D5, D6, D16

(306) 0x4283d4 FADD	D5, D6, D5

(306) 0x4283d8 LDR	D6, [X1]

(306) 0x4283dc FMUL	D3, D3, D0

(306) 0x4283e0 FADD	D5, D16, D5

(306) 0x4283e4 LDR	D16, [X10, X9,SXTW #3]

(306) 0x4283e8 MADD	X9, X3, X24, XZR

(306) 0x4283ec FMUL	D4, D4, D5

(306) 0x4283f0 FADD	D5, D18, D19

(306) 0x4283f4 ADD	X9, X2, X9,LSL #3

(306) 0x4283f8 FADD	D5, D18, D5

(306) 0x4283fc FMUL	D3, D6, D3

(306) 0x428400 FMUL	D4, D4, D0

(306) 0x428404 FADD	D5, D19, D5

(306) 0x428408 FMUL	D3, D3, D1

(306) 0x42840c FMUL	D5, D17, D5

(306) 0x428410 FADD	D17, D7, D16

(306) 0x428414 FMUL	D4, D6, D4

(306) 0x428418 FADD	D7, D7, D17

(306) 0x42841c FMUL	D5, D5, D0

(306) 0x428420 FMUL	D4, D4, D1

(306) 0x428424 FADD	D7, D16, D7

(306) 0x428428 FMUL	D7, D20, D7

(306) 0x42842c FMUL	D5, D6, D5

(306) 0x428430 FSUB	D3, D4, S3

(306) 0x428434 LDR	D4, [X9, X19,SXTW #3]

(306) 0x428438 MADD	X9, X5, X24, XZR

(306) 0x42843c ADD	X9, X4, X9,LSL #3

(306) 0x428440 FMUL	D7, D7, D0

(306) 0x428444 FMUL	D5, D5, D1

(306) 0x428448 FMUL	D6, D6, D7

(306) 0x42844c FMUL	D6, D6, D1

(306) 0x428450 FADD	D3, D3, D6

(306) 0x428454 FDIV	D6, D2, D4

(306) 0x428458 FSUB	D3, D3, S5

(306) 0x42845c LDR	D5, [X9, X19,SXTW #3]

(306) 0x428460 LDP	X10, X9, [SP, #80]

(306) 0x428464 MADD	X9, X9, X24, XZR

(306) 0x428468 MADD	X10, X10, X24, XZR

(306) 0x42846c ADD	X9, X6, X9,LSL #3

(306) 0x428470 ADD	X10, X20, X10,LSL #3

(306) 0x428474 LDR	D7, [X9, X19,SXTW #3]

(306) 0x428478 LDR	D16, [X10, X19,SXTW #3]

(306) 0x42847c MADD	X10, X23, X24, XZR

(306) 0x428480 ADD	X10, X25, X10,LSL #3

(306) 0x428484 FDIV	D5, D5, D7

(306) 0x428488 FDIV	D7, D16, D7

(306) 0x42848c FADD	D5, D5, D7

(306) 0x428490 FMUL	D5, D3, D5

(306) 0x428494 FADD	D3, D4, D3

(306) 0x428498 FDIV	D3, D4, D3

(306) 0x42849c FMUL	D5, D6, D5

(306) 0x4284a0 LDR	D6, [X10, X19,SXTW #3]

(306) 0x4284a4 MADD	X10, X26, X24, XZR

(306) 0x4284a8 ADD	X10, X7, X10,LSL #3

(306) 0x4284ac FADD	D5, D6, D5

(306) 0x4284b0 STR	D5, [X10, X19,SXTW #3]

(306) 0x4284b4 ORR	X10, XZR, X18

(306) 0x4284b8 LDR	D5, [X9, X19,SXTW #3]

(306) 0x4284bc MADD	X9, X8, X24, XZR

(306) 0x4284c0 ADD	X9, X22, X9,LSL #3

(306) 0x4284c4 FMUL	D3, D3, D5

(306) 0x4284c8 STR	D3, [X9, X19,SXTW #3]

(306) 0x4284cc CMP	X28, X27

(306) 0x4284d0 B.NE	428320

0x4284d4 LDR	W1, [SP, #76]

0x4284d8 ADRP	X0,

0x4284dc ADD	X0, X0, #2440

0x4284e0 BL	402cc0

0x4284e4 ADDVL	SP, SP, #7

0x4284e8 ADD	SP, SP, #144

0x4284ec LDP	D9, D8, [SP, #48]

0x4284f0 LDP	D11, D10, [SP, #32]

0x4284f4 LDP	D13, D12, [SP, #16]

0x4284f8 LDP	X20, X19, [SP, #144]

0x4284fc LDP	X22, X21, [SP, #128]

0x428500 LDP	X24, X23, [SP, #112]

0x428504 LDP	X26, X25, [SP, #96]

0x428508 LDP	X28, X27, [SP, #80]

0x42850c LDP	X29, X30, [SP, #64]

0x428510 LDP	D15, D14, [SP], #160

0x428514 RET

0x428518 HINT	#0

0x42851c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 62% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 27.00 to 23.67 cycles (1.14x speedup).

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

26% of VPU loads are used in vector version.
37% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 1.00 cycles (27.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 536 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	186
loop length	744
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	13.58	13.58	13.67	13.67	27.00	13.50	5.50	5.50	2.50	2.50	26.83	26.50	26.67	9.00	9.00
cycles	3.50	3.50	13.58	13.58	13.67	13.67	27.00	13.50	5.50	5.50	2.50	2.50	26.83	26.50	26.67	9.00	9.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.88
Overall L1	27.00

Vectorization ratios

INT

all	16%
load	26%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	26%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.00 cycles. At this rate:

20% of peak load performance is reached (19.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427e70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #57	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W19, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W19, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 4284e4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W9, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46dee4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2416	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #116	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X24, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #120	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X8, X24, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X24, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X24, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4284d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X30, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X1, X27, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X22, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X10, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X8, X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X30, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X8, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X30, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X22, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X1, X18, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X28, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42830c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X27, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FDUP Z25.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X5, X3, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
INDEX Z13.D, X24, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
AND X28, X28, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X26, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X27, X24, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z22.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDP X8, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
DUP Z1.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z5.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z6.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z7.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z19.D, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X1, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z20.D, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X23, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z21.D, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z23.D, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z24.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z27.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z28.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z29.D, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z31.D, X4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z8.D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z9.D, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z10.D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z11.D, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z12.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z0.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X9, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X9, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X9, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X30, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X5, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X18, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X9, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
ORR X2, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X4, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X6, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X26, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X7, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X3, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B.EQ 4284d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D1, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D2, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X28, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W30, WZR, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46d4d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP D15, D14, [SP], #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

26% of VPU loads are used in vector version.
37% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.00 to 1.00 cycles (27.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 536 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	186
loop length	744
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	13.58	13.58	13.67	13.67	27.00	13.50	5.50	5.50	2.50	2.50	26.83	26.50	26.67	9.00	9.00
cycles	3.50	3.50	13.58	13.58	13.67	13.67	27.00	13.50	5.50	5.50	2.50	2.50	26.83	26.50	26.67	9.00	9.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.88
Overall L1	27.00

Vectorization ratios

INT

all	16%
load	26%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	26%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.00 cycles. At this rate:

20% of peak load performance is reached (19.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427e70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL SP, SP, #57	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W19, W21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W9, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS W8, W8, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W19, #4, #12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LE 4284e4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W9, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <46dee4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2416	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #116	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR WZR, [SP, #116]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UMADDL X24, W25, W8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #120	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X8, X24, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X24, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X24, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 4284d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X30, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X1, X27, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X22, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X10, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X8, X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X30, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X8, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X30, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X28, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X22, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X1, X18, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X28, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 42830c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X27, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
FDUP Z25.D, #80	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
STP X5, X3, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
INDEX Z13.D, X24, #1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	5	1	N/A
AND X28, X28, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X26, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X27, X24, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z22.D, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
LDP X8, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
DUP Z1.D, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z5.D, X12	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z6.D, X14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z7.D, X16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z19.D, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X1, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z20.D, X23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X23, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DUP Z21.D, X26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z23.D, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z24.D, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z27.D, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z28.D, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z29.D, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z31.D, X4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z8.D, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z9.D, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z10.D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z11.D, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z12.D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP Z0.D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
SUB X9, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z0, [X9, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STR Z0, [X9, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X30, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X5, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
ORR X18, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z0, [X9, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X9, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
ORR X2, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X4, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X6, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X26, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X7, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X3, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B.EQ 4284d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D1, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D2, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X28, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB W30, WZR, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <46d4d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402cc0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP D15, D14, [SP], #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.42	4.52
○Loop 307 - PdV.cpp:49-63 - exec	5.42	4.48
○Loop 306 - PdV.cpp:49-63 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code