OV - exec - Function generate_chunk(int, global_variables&) [clone .omp

	Function: generate_chunk(int, global_variables&) [clone .omp_outlined.2]	Module: exec	Source: generate_chunk.cpp:85-123 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 85 - 123

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4231e0 LDR	W8, [X2]

0x4231e4 LDR	W9, [X3]

0x4231e8 CMP	W8, #1

0x4231ec CCMP	W9, #1, #8, #10

0x4231f0 B.LT	4232b0

0x4231f4 SUB	SP, SP, #160

0x4231f8 STP	X29, X30, [SP, #64]

0x4231fc STP	X28, X27, [SP, #80]

0x423200 STP	X26, X25, [SP, #96]

0x423204 STP	X24, X23, [SP, #112]

0x423208 STP	X22, X21, [SP, #128]

0x42320c STP	X20, X19, [SP, #144]

0x423210 ADD	X29, SP, #64

0x423214 LDR	W1, [X0]

0x423218 SBFM	X24, X9, #0, #31

0x42321c MOVN	X9, #0

0x423220 ORR	X20, XZR, X7

0x423224 ORR	X21, XZR, X6

0x423228 ORR	X23, XZR, X5

0x42322c ORR	X22, XZR, X4

0x423230 ADRP	X0,

0x423234 ADD	X0, X0, #1320

0x423238 SUB	X3, X29, #28

0x42323c SUB	X4, X29, #8

0x423240 STUR	WZR, [X29, #484]

0x423244 STR	W1, [SP, #12]

0x423248 MADD	X19, X24, X8, X9

0x42324c MOVZ	W8, #1

0x423250 SUB	X5, X29, #16

0x423254 SUB	X6, X29, #24

0x423258 MOVZ	W2, #34

0x42325c MOVZ	W7, #1

0x423260 STP	X19, XZR, [X29, #1008]

0x423264 STUR	X8, [X29, #488]

0x423268 STR	X8, [SP]

0x42326c BL	402e00

0x423270 LDP	X8, X7, [X29, #1008]

0x423274 CMP	X8, X19

0x423278 CSEL	X6, X8, X19, #11

0x42327c CMP	X7, X6

0x423280 B.LE	4232b4

  (246) 0x423284 LDR	W1, [SP, #12]

  (246) 0x423288 ADRP	X0,

  (246) 0x42328c ADD	X0, X0, #1344

  (246) 0x423290 BL	402cc0

  (246) 0x423294 LDP	X20, X19, [SP, #144]

  (246) 0x423298 LDP	X22, X21, [SP, #128]

  (246) 0x42329c LDP	X24, X23, [SP, #112]

  (246) 0x4232a0 LDP	X26, X25, [SP, #96]

  (246) 0x4232a4 LDP	X28, X27, [SP, #80]

  (246) 0x4232a8 LDP	X29, X30, [SP, #64]

  (246) 0x4232ac ADD	SP, SP, #160

  (246) 0x4232b0 RET

  (246) 0x4232b4 LDR	X25, [X29, #96]

  (246) 0x4232b8 LDRSW	X8, [X23]

  (246) 0x4232bc LDR	X13, [X20, #8]

  (246) 0x4232c0 LDP	X17, X12, [X29, #136]

  (246) 0x4232c4 LDP	X11, X14, [X29, #120]

  (246) 0x4232c8 LDR	X10, [X21, #8]

  (246) 0x4232cc ADD	X10, X10, X8,LSL #3

  (246) 0x4232d0 LDR	W20, [X13, X8,LSL #2]

  (246) 0x4232d4 LDR	X15, [X25, #64]

  (246) 0x4232d8 LDR	X13, [X25, #48]

  (246) 0x4232dc LDR	X11, [X11, #8]

  (246) 0x4232e0 LDR	X14, [X14, #8]

  (246) 0x4232e4 LDR	X17, [X17, #8]

  (246) 0x4232e8 LDR	X12, [X12, #8]

  (246) 0x4232ec LDR	X9, [X22, #8]

  (246) 0x4232f0 LDR	X4, [X25, #600]

  (246) 0x4232f4 ADD	X11, X11, X8,LSL #3

  (246) 0x4232f8 LDR	X5, [X25, #632]

  (246) 0x4232fc STP	X13, X15, [SP, #16]

  (246) 0x423300 LDR	X15, [X25, #16]

  (246) 0x423304 LDR	X16, [X25]

  (246) 0x423308 LDR	X18, [X25, #184]

  (246) 0x42330c LDR	X0, [X25, #168]

  (246) 0x423310 LDR	X2, [X25, #232]

  (246) 0x423314 LDR	X3, [X25, #216]

  (246) 0x423318 ADD	X14, X14, X8,LSL #3

  (246) 0x42331c ADD	X17, X17, X8,LSL #3

  (246) 0x423320 ADD	X1, X12, X8,LSL #3

  (246) 0x423324 CMP	W20, #1

  (246) 0x423328 B.EQ	42387c

  (246) 0x42332c CMP	W20, #2

  (246) 0x423330 B.EQ	4235b8

  (246) 0x423334 CMP	W20, #3

  (246) 0x423338 B.NE	423284

  (246) 0x42333c SUB	X12, X6, X7

  (246) 0x423340 ADD	X20, X12, #1

  (246) 0x423344 CNTD	X12, ALL

  (246) 0x423348 CMP	X20, X12

  (246) 0x42334c B.CC	4234b4

  (246) 0x423350 INDEX	Z0.D, X7, #1

  (246) 0x423354 SUB	X19, XZR, X12

  (246) 0x423358 PTRUE	P0.D, ALL

  (246) 0x42335c DUP	Z7.D, #8

  (246) 0x423360 DUP	Z16.D, #0

  (246) 0x423364 AND	X21, X20, X19

  (246) 0x423368 ADD	X7, X7, X21

  (246) 0x42336c DUP	Z1.D, X12

  (246) 0x423370 LDP	X13, X12, [SP, #16]

  (246) 0x423374 ORR	X22, XZR, X21

  (246) 0x423378 ORR	Z20.D, Z0.D, Z0.D

  (246) 0x42337c DUP	Z2.D, X24

  (246) 0x423380 DUP	Z3.D, X13

  (246) 0x423384 DUP	Z4.D, X16

  (246) 0x423388 DUP	Z5.D, X0

  (246) 0x42338c DUP	Z6.D, X3

  (246) 0x423390 DUP	Z17.D, X12

  (246) 0x423394 DUP	Z18.D, X15

  (246) 0x423398 DUP	Z19.D, X18

  (246) 0x42339c DUP	Z21.D, X2

    (252) 0x4233a0 MOVPRFX	Z22, Z0

    (252) 0x4233a4 SDIV	Z22.D, P0/M, Z22.D, Z2.D

    (252) 0x4233a8 ADD	X12, X9, X8,LSL #3

    (252) 0x4233ac DECD	X22, ALL

    (252) 0x4233b0 LD1RD	{Z24.D}, P0/Z, [X12]

    (252) 0x4233b4 MUL	Z23.D, Z22.D, Z2.D

    (252) 0x4233b8 MOVPRFX	Z26, Z22

    (252) 0x4233bc SXTW	Z26.D, P0/M, Z22.D

    (252) 0x4233c0 MUL	Z27.D, Z6.D, Z26.D

    (252) 0x4233c4 SUB	Z23.D, Z0.D, Z23.D

    (252) 0x4233c8 ADD	Z0.D, Z0.D, Z1.D

    (252) 0x4233cc LD1D	{Z25.D}, P0/Z, [X4, Z23.D,SXTW #3]

    (252) 0x4233d0 ADR	Z27.D, [Z21, Z27.D,LSL #3]

    (252) 0x4233d4 FCMEQ	P1.D, P0/Z, Z25.D, Z24.D

    (252) 0x4233d8 LD1D	{Z24.D}, P1/Z, [X10, Z16.D,LSL #3]

    (252) 0x4233dc LD1D	{Z25.D}, P1/Z, [X5, Z22.D,SXTW #3]

    (252) 0x4233e0 MUL	Z22.D, Z2.D, Z22.D

    (252) 0x4233e4 SUB	Z22.D, Z20.D, Z22.D

    (252) 0x4233e8 ADD	Z20.D, Z20.D, Z1.D

    (252) 0x4233ec FCMEQ	P1.D, P1/Z, Z25.D, Z24.D

    (252) 0x4233f0 MUL	Z25.D, Z3.D, Z26.D

    (252) 0x4233f4 LD1D	{Z24.D}, P1/Z, [X11, Z16.D,LSL #3]

    (252) 0x4233f8 ADR	Z25.D, [Z17, Z25.D,LSL #3]

    (252) 0x4233fc ADR	Z25.D, [Z25, Z23.D,SXTW #3]

    (252) 0x423400 ST1D	{Z24.D}, P1, [V25.D]

    (252) 0x423404 MUL	Z25.D, Z4.D, Z26.D

    (252) 0x423408 LD1D	{Z24.D}, P1/Z, [X14, Z16.D,LSL #3]

    (252) 0x42340c ADR	Z25.D, [Z18, Z25.D,LSL #3]

    (252) 0x423410 ADR	Z25.D, [Z25, Z23.D,SXTW #3]

    (252) 0x423414 SXTW	Z23.D, P0/M, Z23.D

    (252) 0x423418 ST1D	{Z24.D}, P1, [V25.D]

    (252) 0x42341c MUL	Z24.D, Z5.D, Z26.D

    (252) 0x423420 ADD	Z26.D, Z26.D, #1

    (252) 0x423424 ADR	Z24.D, [Z19, Z24.D,LSL #3]

    (252) 0x423428 LD1D	{Z25.D}, P1/Z, [X17, Z16.D,LSL #3]

    (252) 0x42342c ADR	Z28.D, [Z24, Z22.D,SXTW #3]

    (252) 0x423430 ST1D	{Z25.D}, P1, [V28.D]

    (252) 0x423434 ADR	Z28.D, [Z27, Z22.D,SXTW #3]

    (252) 0x423438 LD1D	{Z25.D}, P1/Z, [X1, Z16.D,LSL #3]

    (252) 0x42343c ST1D	{Z25.D}, P1, [V28.D]

    (252) 0x423440 MOVPRFX	Z25, Z22

    (252) 0x423444 SXTW	Z25.D, P0/M, Z22.D

    (252) 0x423448 CMPGE	P2.D, P1/Z, Z23.D, Z25.D

    (252) 0x42344c ADR	Z25.D, [Z7, Z22.D,SXTW #3]

    (252) 0x423450 ADD	Z24.D, Z24.D, Z25.D

    (252) 0x423454 LD1D	{Z23.D}, P2/Z, [X17, Z16.D,LSL #3]

    (252) 0x423458 ST1D	{Z23.D}, P2, [V24.D]

    (252) 0x42345c ADD	Z24.D, Z27.D, Z25.D

    (252) 0x423460 LD1D	{Z23.D}, P2/Z, [X1, Z16.D,LSL #3]

    (252) 0x423464 ST1D	{Z23.D}, P2, [V24.D]

    (252) 0x423468 MUL	Z24.D, Z5.D, Z26.D

    (252) 0x42346c MUL	Z26.D, Z6.D, Z26.D

    (252) 0x423470 LD1D	{Z23.D}, P1/Z, [X17, Z16.D,LSL #3]

    (252) 0x423474 ADR	Z24.D, [Z19, Z24.D,LSL #3]

    (252) 0x423478 ADR	Z26.D, [Z21, Z26.D,LSL #3]

    (252) 0x42347c ADR	Z27.D, [Z24, Z22.D,SXTW #3]

    (252) 0x423480 ADR	Z22.D, [Z26, Z22.D,SXTW #3]

    (252) 0x423484 ST1D	{Z23.D}, P1, [V27.D]

    (252) 0x423488 LD1D	{Z23.D}, P1/Z, [X1, Z16.D,LSL #3]

    (252) 0x42348c ST1D	{Z23.D}, P1, [V22.D]

    (252) 0x423490 ADD	Z23.D, Z24.D, Z25.D

    (252) 0x423494 LD1D	{Z22.D}, P2/Z, [X17, Z16.D,LSL #3]

    (252) 0x423498 ST1D	{Z22.D}, P2, [V23.D]

    (252) 0x42349c ADD	Z23.D, Z26.D, Z25.D

    (252) 0x4234a0 LD1D	{Z22.D}, P2/Z, [X1, Z16.D,LSL #3]

    (252) 0x4234a4 ST1D	{Z22.D}, P2, [V23.D]

    (252) 0x4234a8 CBNZ	X22, 4233a0

  (246) 0x4234ac CMP	X20, X21

  (246) 0x4234b0 B.EQ	423284

  (246) 0x4234b4 SUB	X21, XZR, X24,LSL #32

  (246) 0x4234b8 ADD	X6, X6, #1

  (246) 0x4234bc SUB	W20, WZR, W24

  (246) 0x4234c0 UBFM	X22, X7, #32, #31

  (246) 0x4234c4 MOVZ	X23, #1

  (246) 0x4234c8 B	4234dc

    (251) 0x4234cc ADD	X7, X7, #1

    (251) 0x4234d0 ADD	X22, X22, X23

    (251) 0x4234d4 CMP	X6, X7

    (251) 0x4234d8 B.EQ	423284

    (251) 0x4234dc SDIV	X27, X7, X24

    (251) 0x4234e0 LDR	D0, [X9, X8,LSL #3]

    (251) 0x4234e4 MADD	X12, X21, X27, X22

    (251) 0x4234e8 SBFM	X13, X12, #29, #63

    (251) 0x4234ec LDR	D1, [X4, X13]

    (251) 0x4234f0 FCMP	D1, D0

    (251) 0x4234f4 B.NE	4234cc

    (251) 0x4234f8 LDR	D0, [X10]

    (251) 0x4234fc LDR	D1, [X5, X27,SXTW #3]

    (251) 0x423500 FCMP	D1, D0

    (251) 0x423504 B.NE	4234cc

    (251) 0x423508 SBFM	X25, X12, #32, #63

    (251) 0x42350c LDP	X12, X13, [SP, #16]

    (251) 0x423510 LDR	D0, [X11]

    (251) 0x423514 SBFM	X26, X27, #0, #31

    (251) 0x423518 MADD	X19, X3, X26, XZR

    (251) 0x42351c ADD	X19, X2, X19,LSL #3

    (251) 0x423520 MADD	X12, X12, X26, XZR

    (251) 0x423524 ADD	X12, X13, X12,LSL #3

    (251) 0x423528 MADD	W13, W20, W27, W7

    (251) 0x42352c STR	D0, [X12, X25,LSL #3]

    (251) 0x423530 MADD	X12, X16, X26, XZR

    (251) 0x423534 LDR	D0, [X14]

    (251) 0x423538 SBFM	X27, X13, #0, #31

    (251) 0x42353c ADD	X12, X15, X12,LSL #3

    (251) 0x423540 ADD	X28, X27, #1

    (251) 0x423544 STR	D0, [X12, X25,LSL #3]

    (251) 0x423548 MADD	X12, X0, X26, XZR

    (251) 0x42354c LDR	D0, [X17]

    (251) 0x423550 ADD	X12, X18, X12,LSL #3

    (251) 0x423554 STR	D0, [X12, X13,SXTW #3]

    (251) 0x423558 LDR	D0, [X1]

    (251) 0x42355c STR	D0, [X19, X13,SXTW #3]

    (251) 0x423560 CMP	X25, X27

    (251) 0x423564 B.LT	423578

    (251) 0x423568 LDR	D0, [X17]

    (251) 0x42356c STR	D0, [X12, X28,LSL #3]

    (251) 0x423570 LDR	D0, [X1]

    (251) 0x423574 STR	D0, [X19, X28,LSL #3]

    (251) 0x423578 LDR	D0, [X17]

    (251) 0x42357c ADD	X13, X26, #1

    (251) 0x423580 MADD	X12, X0, X13, XZR

    (251) 0x423584 MADD	X13, X3, X13, XZR

    (251) 0x423588 ADD	X12, X18, X12,LSL #3

    (251) 0x42358c ADD	X19, X2, X13,LSL #3

    (251) 0x423590 STR	D0, [X12, X27,LSL #3]

    (251) 0x423594 LDR	D0, [X1]

    (251) 0x423598 STR	D0, [X19, X27,LSL #3]

    (251) 0x42359c CMP	X25, X27

    (251) 0x4235a0 B.LT	4234cc

    (251) 0x4235a4 LDR	D0, [X17]

    (251) 0x4235a8 STR	D0, [X12, X28,LSL #3]

    (251) 0x4235ac LDR	D0, [X1]

    (251) 0x4235b0 STR	D0, [X19, X28,LSL #3]

    (251) 0x4235b4 B	4234cc

  (246) 0x4235b8 LDR	X12, [X29, #152]

  (246) 0x4235bc LDR	X4, [X25, #536]

  (246) 0x4235c0 LDR	X5, [X25, #568]

  (246) 0x4235c4 LDR	X20, [X12, #8]

  (246) 0x4235c8 SUB	X12, X6, X7

  (246) 0x4235cc ADD	X21, X12, #1

  (246) 0x4235d0 CNTD	X12, ALL

  (246) 0x4235d4 CMP	X21, X12

  (246) 0x4235d8 B.CC	423758

  (246) 0x4235dc INDEX	Z0.D, X7, #1

  (246) 0x4235e0 SUB	X19, XZR, X12

  (246) 0x4235e4 PTRUE	P0.D, ALL

  (246) 0x4235e8 DUP	Z7.D, #8

  (246) 0x4235ec DUP	Z16.D, #0

  (246) 0x4235f0 AND	X22, X21, X19

  (246) 0x4235f4 ADD	X7, X7, X22

  (246) 0x4235f8 DUP	Z1.D, X12

  (246) 0x4235fc LDP	X13, X12, [SP, #16]

  (246) 0x423600 ORR	X23, XZR, X22

  (246) 0x423604 ORR	Z20.D, Z0.D, Z0.D

  (246) 0x423608 DUP	Z2.D, X24

  (246) 0x42360c DUP	Z3.D, X13

  (246) 0x423610 DUP	Z4.D, X16

  (246) 0x423614 DUP	Z5.D, X0

  (246) 0x423618 DUP	Z6.D, X3

  (246) 0x42361c DUP	Z17.D, X12

  (246) 0x423620 DUP	Z18.D, X15

  (246) 0x423624 DUP	Z19.D, X18

  (246) 0x423628 DUP	Z21.D, X2

    (250) 0x42362c MOVPRFX	Z22, Z0

    (250) 0x423630 SDIV	Z22.D, P0/M, Z22.D, Z2.D

    (250) 0x423634 ADD	X12, X9, X8,LSL #3

    (250) 0x423638 LD1RD	{Z25.D}, P0/Z, [X10]

    (250) 0x42363c DECD	X23, ALL

    (250) 0x423640 LD1RD	{Z24.D}, P0/Z, [X12]

    (250) 0x423644 ADD	X12, X20, X8,LSL #3

    (250) 0x423648 MUL	Z23.D, Z22.D, Z2.D

    (250) 0x42364c SUB	Z23.D, Z0.D, Z23.D

    (250) 0x423650 ADD	Z0.D, Z0.D, Z1.D

    (250) 0x423654 LD1D	{Z26.D}, P0/Z, [X4, Z23.D,SXTW #3]

    (250) 0x423658 FSUB	Z24.D, Z26.D, Z24.D

    (250) 0x42365c LD1D	{Z26.D}, P0/Z, [X5, Z22.D,SXTW #3]

    (250) 0x423660 FSUB	Z25.D, Z26.D, Z25.D

    (250) 0x423664 LD1RD	{Z26.D}, P0/Z, [X12]

    (250) 0x423668 FMUL	Z25.D, Z25.D, Z25.D

    (250) 0x42366c FMAD	Z24.D, P0/M, Z24.D, Z25.D

    (250) 0x423670 MOVPRFX	Z25, Z22

    (250) 0x423674 SXTW	Z25.D, P0/M, Z22.D

    (250) 0x423678 MUL	Z22.D, Z2.D, Z22.D

    (250) 0x42367c MUL	Z27.D, Z6.D, Z25.D

    (250) 0x423680 FSQRT	Z24.D, P0/M, Z24.D

    (250) 0x423684 SUB	Z22.D, Z20.D, Z22.D

    (250) 0x423688 ADD	Z20.D, Z20.D, Z1.D

    (250) 0x42368c ADR	Z27.D, [Z21, Z27.D,LSL #3]

    (250) 0x423690 FCMGE	P1.D, P0/Z, Z26.D, Z24.D

    (250) 0x423694 MUL	Z26.D, Z3.D, Z25.D

    (250) 0x423698 LD1D	{Z24.D}, P1/Z, [X11, Z16.D,LSL #3]

    (250) 0x42369c ADR	Z26.D, [Z17, Z26.D,LSL #3]

    (250) 0x4236a0 ADR	Z26.D, [Z26, Z23.D,SXTW #3]

    (250) 0x4236a4 ST1D	{Z24.D}, P1, [V26.D]

    (250) 0x4236a8 MUL	Z26.D, Z4.D, Z25.D

    (250) 0x4236ac LD1D	{Z24.D}, P1/Z, [X14, Z16.D,LSL #3]

    (250) 0x4236b0 ADR	Z26.D, [Z18, Z26.D,LSL #3]

    (250) 0x4236b4 ADR	Z26.D, [Z26, Z23.D,SXTW #3]

    (250) 0x4236b8 SXTW	Z23.D, P0/M, Z23.D

    (250) 0x4236bc ST1D	{Z24.D}, P1, [V26.D]

    (250) 0x4236c0 MUL	Z24.D, Z5.D, Z25.D

    (250) 0x4236c4 ADD	Z25.D, Z25.D, #1

    (250) 0x4236c8 LD1D	{Z26.D}, P1/Z, [X17, Z16.D,LSL #3]

    (250) 0x4236cc ADR	Z24.D, [Z19, Z24.D,LSL #3]

    (250) 0x4236d0 ADR	Z28.D, [Z24, Z22.D,SXTW #3]

    (250) 0x4236d4 ST1D	{Z26.D}, P1, [V28.D]

    (250) 0x4236d8 ADR	Z28.D, [Z27, Z22.D,SXTW #3]

    (250) 0x4236dc LD1D	{Z26.D}, P1/Z, [X1, Z16.D,LSL #3]

    (250) 0x4236e0 ST1D	{Z26.D}, P1, [V28.D]

    (250) 0x4236e4 MOVPRFX	Z26, Z22

    (250) 0x4236e8 SXTW	Z26.D, P0/M, Z22.D

    (250) 0x4236ec CMPGE	P2.D, P1/Z, Z23.D, Z26.D

    (250) 0x4236f0 ADR	Z26.D, [Z7, Z22.D,SXTW #3]

    (250) 0x4236f4 ADD	Z24.D, Z24.D, Z26.D

    (250) 0x4236f8 LD1D	{Z23.D}, P2/Z, [X17, Z16.D,LSL #3]

    (250) 0x4236fc ST1D	{Z23.D}, P2, [V24.D]

    (250) 0x423700 ADD	Z24.D, Z27.D, Z26.D

    (250) 0x423704 LD1D	{Z23.D}, P2/Z, [X1, Z16.D,LSL #3]

    (250) 0x423708 ST1D	{Z23.D}, P2, [V24.D]

    (250) 0x42370c MUL	Z24.D, Z5.D, Z25.D

    (250) 0x423710 MUL	Z25.D, Z6.D, Z25.D

    (250) 0x423714 LD1D	{Z23.D}, P1/Z, [X17, Z16.D,LSL #3]

    (250) 0x423718 ADR	Z24.D, [Z19, Z24.D,LSL #3]

    (250) 0x42371c ADR	Z25.D, [Z21, Z25.D,LSL #3]

    (250) 0x423720 ADR	Z27.D, [Z24, Z22.D,SXTW #3]

    (250) 0x423724 ADR	Z22.D, [Z25, Z22.D,SXTW #3]

    (250) 0x423728 ST1D	{Z23.D}, P1, [V27.D]

    (250) 0x42372c LD1D	{Z23.D}, P1/Z, [X1, Z16.D,LSL #3]

    (250) 0x423730 ST1D	{Z23.D}, P1, [V22.D]

    (250) 0x423734 ADD	Z23.D, Z24.D, Z26.D

    (250) 0x423738 LD1D	{Z22.D}, P2/Z, [X17, Z16.D,LSL #3]

    (250) 0x42373c ST1D	{Z22.D}, P2, [V23.D]

    (250) 0x423740 ADD	Z23.D, Z25.D, Z26.D

    (250) 0x423744 LD1D	{Z22.D}, P2/Z, [X1, Z16.D,LSL #3]

    (250) 0x423748 ST1D	{Z22.D}, P2, [V23.D]

    (250) 0x42374c CBNZ	X23, 42362c

  (246) 0x423750 CMP	X21, X22

  (246) 0x423754 B.EQ	423284

(249) 0x423758 SUB	X22, XZR, X24,LSL #32

(249) 0x42375c ADD	X6, X6, #1

(249) 0x423760 SUB	W21, WZR, W24

(249) 0x423764 UBFM	X23, X7, #32, #31

(249) 0x423768 MOVZ	X25, #1

(249) 0x42376c B	423790

0x423770 HINT	#0

0x423774 HINT	#0

0x423778 HINT	#0

0x42377c HINT	#0

(249) 0x423780 ADD	X7, X7, #1

(249) 0x423784 ADD	X23, X23, X25

(249) 0x423788 CMP	X6, X7

(249) 0x42378c B.EQ	423284

(249) 0x423790 SDIV	X28, X7, X24

(249) 0x423794 LDR	D0, [X9, X8,LSL #3]

(249) 0x423798 LDR	D1, [X10]

(249) 0x42379c MADD	X12, X22, X28, X23

(249) 0x4237a0 SBFM	X13, X12, #29, #63

(249) 0x4237a4 LDR	D2, [X4, X13]

(249) 0x4237a8 FSUB	D0, D2, S0

(249) 0x4237ac LDR	D2, [X5, X28,SXTW #3]

(249) 0x4237b0 FSUB	D1, D2, S1

(249) 0x4237b4 FMUL	D1, D1, D1

(249) 0x4237b8 FMADD	D0, D0, D0, D1

(249) 0x4237bc LDR	D1, [X20, X8,LSL #3]

(249) 0x4237c0 FSQRT	D0, D0

(249) 0x4237c4 FCMP	D0, D1

(249) 0x4237c8 B.HI	423780

(249) 0x4237cc SBFM	X26, X12, #32, #63

(249) 0x4237d0 LDP	X12, X13, [SP, #16]

(249) 0x4237d4 LDR	D0, [X11]

(249) 0x4237d8 SBFM	X27, X28, #0, #31

(249) 0x4237dc MADD	X19, X3, X27, XZR

(249) 0x4237e0 ADD	X19, X2, X19,LSL #3

(249) 0x4237e4 MADD	X12, X12, X27, XZR

(249) 0x4237e8 ADD	X12, X13, X12,LSL #3

(249) 0x4237ec MADD	W13, W21, W28, W7

(249) 0x4237f0 STR	D0, [X12, X26,LSL #3]

(249) 0x4237f4 MADD	X12, X16, X27, XZR

(249) 0x4237f8 LDR	D0, [X14]

(249) 0x4237fc SBFM	X28, X13, #0, #31

(249) 0x423800 ADD	X12, X15, X12,LSL #3

(249) 0x423804 ADD	X30, X28, #1

(249) 0x423808 STR	D0, [X12, X26,LSL #3]

(249) 0x42380c MADD	X12, X0, X27, XZR

(249) 0x423810 LDR	D0, [X17]

(249) 0x423814 ADD	X12, X18, X12,LSL #3

(249) 0x423818 STR	D0, [X12, X13,SXTW #3]

(249) 0x42381c LDR	D0, [X1]

(249) 0x423820 STR	D0, [X19, X13,SXTW #3]

(249) 0x423824 CMP	X26, X28

(249) 0x423828 B.LT	42383c

(249) 0x42382c LDR	D0, [X17]

(249) 0x423830 STR	D0, [X12, X30,LSL #3]

(249) 0x423834 LDR	D0, [X1]

(249) 0x423838 STR	D0, [X19, X30,LSL #3]

(249) 0x42383c LDR	D0, [X17]

(249) 0x423840 ADD	X13, X27, #1

(249) 0x423844 MADD	X12, X0, X13, XZR

(249) 0x423848 MADD	X13, X3, X13, XZR

(249) 0x42384c ADD	X12, X18, X12,LSL #3

(249) 0x423850 ADD	X19, X2, X13,LSL #3

(249) 0x423854 STR	D0, [X12, X28,LSL #3]

(249) 0x423858 LDR	D0, [X1]

(249) 0x42385c STR	D0, [X19, X28,LSL #3]

(249) 0x423860 CMP	X26, X28

(249) 0x423864 B.LT	423780

(249) 0x423868 LDR	D0, [X17]

(249) 0x42386c STR	D0, [X12, X30,LSL #3]

(249) 0x423870 LDR	D0, [X1]

(249) 0x423874 STR	D0, [X19, X30,LSL #3]

(249) 0x423878 B	423780

  (246) 0x42387c LDP	X19, X12, [X29, #104]

  (246) 0x423880 LDR	X12, [X12, #8]

  (246) 0x423884 LDR	X19, [X19, #8]

  (246) 0x423888 ADD	X21, X12, X8,LSL #3

  (246) 0x42388c SUB	X12, X6, X7

  (246) 0x423890 ADD	X20, X19, X8,LSL #3

  (246) 0x423894 ADD	X22, X12, #1

  (246) 0x423898 CNTD	X12, ALL

  (246) 0x42389c CMP	X22, X12

  (246) 0x4238a0 B.CC	423a4c

  (246) 0x4238a4 INDEX	Z0.D, X7, #1

  (246) 0x4238a8 SUB	X19, XZR, X12

  (246) 0x4238ac PTRUE	P0.D, ALL

  (246) 0x4238b0 DUPM	Z7.D, #4294967296

  (246) 0x4238b4 DUP	Z16.D, #8

  (246) 0x4238b8 DUP	Z17.D, #0

  (246) 0x4238bc AND	X23, X22, X19

  (246) 0x4238c0 ADD	X25, X7, X23

  (246) 0x4238c4 DUP	Z1.D, X12

  (246) 0x4238c8 LDP	X13, X12, [SP, #16]

  (246) 0x4238cc ORR	X7, XZR, X23

  (246) 0x4238d0 ORR	Z21.D, Z0.D, Z0.D

  (246) 0x4238d4 DUP	Z2.D, X24

  (246) 0x4238d8 DUP	Z3.D, X13

  (246) 0x4238dc DUP	Z4.D, X16

  (246) 0x4238e0 DUP	Z5.D, X0

  (246) 0x4238e4 DUP	Z6.D, X3

  (246) 0x4238e8 DUP	Z18.D, X12

  (246) 0x4238ec DUP	Z19.D, X15

  (246) 0x4238f0 DUP	Z20.D, X18

  (246) 0x4238f4 DUP	Z22.D, X2

  (246) 0x4238f8 HINT	#0

  (246) 0x4238fc HINT	#0

    (248) 0x423900 MOVPRFX	Z23, Z0

    (248) 0x423904 SDIV	Z23.D, P0/M, Z23.D, Z2.D

    (248) 0x423908 ADD	X12, X9, X8,LSL #3

    (248) 0x42390c LDR	D26, [X10]

    (248) 0x423910 DECD	X7, ALL

    (248) 0x423914 LD1RD	{Z25.D}, P0/Z, [X12]

    (248) 0x423918 DUP	Z26.D, Z26.D[0]

    (248) 0x42391c MUL	Z24.D, Z23.D, Z2.D

    (248) 0x423920 LSL	Z28.D, Z23.D, #32

    (248) 0x423924 SUB	Z24.D, Z0.D, Z24.D

    (248) 0x423928 ADD	Z0.D, Z0.D, Z1.D

    (248) 0x42392c LSL	Z27.D, Z24.D, #32

    (248) 0x423930 ADD	Z27.D, Z27.D, Z7.D

    (248) 0x423934 ASR	Z27.D, Z27.D, #-31

    (248) 0x423938 LD1D	{Z27.D}, P0/Z, [X4, Z27.D]

    (248) 0x42393c FCMGE	P1.D, P0/Z, Z27.D, Z25.D

    (248) 0x423940 LD1D	{Z25.D}, P1/Z, [X4, Z24.D,SXTW #3]

    (248) 0x423944 LD1D	{Z27.D}, P1/Z, [X20, Z17.D,LSL #3]

    (248) 0x423948 FCMGT	P1.D, P1/Z, Z27.D, Z25.D

    (248) 0x42394c ADD	Z25.D, Z28.D, Z7.D

    (248) 0x423950 MOVPRFX	Z27, Z23

    (248) 0x423954 SXTW	Z27.D, P0/M, Z23.D

    (248) 0x423958 ASR	Z25.D, Z25.D, #-31

    (248) 0x42395c MUL	Z28.D, Z6.D, Z27.D

    (248) 0x423960 LD1D	{Z25.D}, P1/Z, [X5, Z25.D]

    (248) 0x423964 ADR	Z28.D, [Z22, Z28.D,LSL #3]

    (248) 0x423968 FCMGE	P1.D, P1/Z, Z25.D, Z26.D

    (248) 0x42396c LD1D	{Z25.D}, P1/Z, [X5, Z23.D,SXTW #3]

    (248) 0x423970 MUL	Z23.D, Z2.D, Z23.D

    (248) 0x423974 LD1D	{Z26.D}, P1/Z, [X21, Z17.D,LSL #3]

    (248) 0x423978 SUB	Z23.D, Z21.D, Z23.D

    (248) 0x42397c ADD	Z21.D, Z21.D, Z1.D

    (248) 0x423980 FCMGT	P1.D, P1/Z, Z26.D, Z25.D

    (248) 0x423984 MUL	Z26.D, Z3.D, Z27.D

    (248) 0x423988 LD1D	{Z25.D}, P1/Z, [X11, Z17.D,LSL #3]

    (248) 0x42398c ADR	Z26.D, [Z18, Z26.D,LSL #3]

    (248) 0x423990 ADR	Z26.D, [Z26, Z24.D,SXTW #3]

    (248) 0x423994 ST1D	{Z25.D}, P1, [V26.D]

    (248) 0x423998 MUL	Z26.D, Z4.D, Z27.D

    (248) 0x42399c LD1D	{Z25.D}, P1/Z, [X14, Z17.D,LSL #3]

    (248) 0x4239a0 ADR	Z26.D, [Z19, Z26.D,LSL #3]

    (248) 0x4239a4 ADR	Z26.D, [Z26, Z24.D,SXTW #3]

    (248) 0x4239a8 SXTW	Z24.D, P0/M, Z24.D

    (248) 0x4239ac ST1D	{Z25.D}, P1, [V26.D]

    (248) 0x4239b0 MUL	Z25.D, Z5.D, Z27.D

    (248) 0x4239b4 ADD	Z27.D, Z27.D, #1

    (248) 0x4239b8 LD1D	{Z26.D}, P1/Z, [X17, Z17.D,LSL #3]

    (248) 0x4239bc ADR	Z25.D, [Z20, Z25.D,LSL #3]

    (248) 0x4239c0 ADR	Z29.D, [Z25, Z23.D,SXTW #3]

    (248) 0x4239c4 ST1D	{Z26.D}, P1, [V29.D]

    (248) 0x4239c8 ADR	Z29.D, [Z28, Z23.D,SXTW #3]

    (248) 0x4239cc LD1D	{Z26.D}, P1/Z, [X1, Z17.D,LSL #3]

    (248) 0x4239d0 ST1D	{Z26.D}, P1, [V29.D]

    (248) 0x4239d4 MOVPRFX	Z26, Z23

    (248) 0x4239d8 SXTW	Z26.D, P0/M, Z23.D

    (248) 0x4239dc CMPGE	P2.D, P1/Z, Z24.D, Z26.D

    (248) 0x4239e0 ADR	Z26.D, [Z16, Z23.D,SXTW #3]

    (248) 0x4239e4 ADD	Z25.D, Z25.D, Z26.D

    (248) 0x4239e8 LD1D	{Z24.D}, P2/Z, [X17, Z17.D,LSL #3]

    (248) 0x4239ec ST1D	{Z24.D}, P2, [V25.D]

    (248) 0x4239f0 ADD	Z25.D, Z28.D, Z26.D

    (248) 0x4239f4 LD1D	{Z24.D}, P2/Z, [X1, Z17.D,LSL #3]

    (248) 0x4239f8 ST1D	{Z24.D}, P2, [V25.D]

    (248) 0x4239fc MUL	Z25.D, Z5.D, Z27.D

    (248) 0x423a00 MUL	Z27.D, Z6.D, Z27.D

    (248) 0x423a04 ADR	Z25.D, [Z20, Z25.D,LSL #3]

    (248) 0x423a08 ADR	Z27.D, [Z22, Z27.D,LSL #3]

    (248) 0x423a0c ADR	Z28.D, [Z25, Z23.D,SXTW #3]

    (248) 0x423a10 LD1D	{Z24.D}, P1/Z, [X17, Z17.D,LSL #3]

    (248) 0x423a14 ADR	Z23.D, [Z27, Z23.D,SXTW #3]

    (248) 0x423a18 ST1D	{Z24.D}, P1, [V28.D]

    (248) 0x423a1c LD1D	{Z24.D}, P1/Z, [X1, Z17.D,LSL #3]

    (248) 0x423a20 ST1D	{Z24.D}, P1, [V23.D]

    (248) 0x423a24 ADD	Z24.D, Z25.D, Z26.D

    (248) 0x423a28 LD1D	{Z23.D}, P2/Z, [X17, Z17.D,LSL #3]

    (248) 0x423a2c ST1D	{Z23.D}, P2, [V24.D]

    (248) 0x423a30 ADD	Z24.D, Z27.D, Z26.D

    (248) 0x423a34 LD1D	{Z23.D}, P2/Z, [X1, Z17.D,LSL #3]

    (248) 0x423a38 ST1D	{Z23.D}, P2, [V24.D]

    (248) 0x423a3c CBNZ	X7, 423900

  (246) 0x423a40 ORR	X7, XZR, X25

  (246) 0x423a44 CMP	X22, X23

  (246) 0x423a48 B.EQ	423284

  (246) 0x423a4c SUB	X23, XZR, X24,LSL #32

  (246) 0x423a50 ADD	X6, X6, #1

  (246) 0x423a54 SUB	W12, WZR, W24

  (246) 0x423a58 UBFM	X25, X7, #32, #31

  (246) 0x423a5c MOVZ	X26, #1

  (246) 0x423a60 STR	W12, [SP, #8]

  (246) 0x423a64 B	423a78

    (247) 0x423a68 ADD	X7, X7, #1

    (247) 0x423a6c ADD	X25, X25, X26

    (247) 0x423a70 CMP	X6, X7

    (247) 0x423a74 B.EQ	423284

    (247) 0x423a78 SDIV	X27, X7, X24

    (247) 0x423a7c LDR	D0, [X9, X8,LSL #3]

    (247) 0x423a80 MADD	X28, X23, X27, X25

    (247) 0x423a84 ADD	X12, X28, X26

    (247) 0x423a88 SBFM	X12, X12, #29, #63

    (247) 0x423a8c LDR	D1, [X4, X12]

    (247) 0x423a90 FCMP	D1, D0

    (247) 0x423a94 B.LT	423a68

    (247) 0x423a98 SBFM	X12, X28, #29, #63

    (247) 0x423a9c LDR	D1, [X20]

    (247) 0x423aa0 LDR	D0, [X4, X12]

    (247) 0x423aa4 FCMP	D0, D1

    (247) 0x423aa8 B.PL	423a68

    (247) 0x423aac UBFM	X22, X27, #32, #31

    (247) 0x423ab0 LDR	D0, [X10]

    (247) 0x423ab4 ADD	X12, X22, X26

    (247) 0x423ab8 SBFM	X12, X12, #29, #63

    (247) 0x423abc LDR	D1, [X5, X12]

    (247) 0x423ac0 FCMP	D1, D0

    (247) 0x423ac4 B.LT	423a68

    (247) 0x423ac8 SBFM	X12, X22, #29, #63

    (247) 0x423acc LDR	D1, [X21]

    (247) 0x423ad0 LDR	D0, [X5, X12]

    (247) 0x423ad4 FCMP	D0, D1

    (247) 0x423ad8 B.PL	423a68

    (247) 0x423adc LDR	X13, [SP, #16]

    (247) 0x423ae0 SBFM	X12, X22, #32, #63

    (247) 0x423ae4 LDR	D0, [X11]

    (247) 0x423ae8 SBFM	X28, X28, #32, #63

    (247) 0x423aec SBFM	X22, X27, #0, #31

    (247) 0x423af0 MADD	X19, X13, X12, XZR

    (247) 0x423af4 LDR	X13, [SP, #24]

    (247) 0x423af8 MADD	X12, X16, X12, XZR

    (247) 0x423afc ADD	X12, X15, X12,LSL #3

    (247) 0x423b00 ADD	X19, X13, X19,LSL #3

    (247) 0x423b04 STR	D0, [X19, X28,LSL #3]

    (247) 0x423b08 LDR	D0, [X14]

    (247) 0x423b0c STR	D0, [X12, X28,LSL #3]

    (247) 0x423b10 LDR	W12, [SP, #8]

    (247) 0x423b14 LDR	D0, [X17]

    (247) 0x423b18 MADD	W13, W12, W27, W7

    (247) 0x423b1c MADD	X12, X0, X22, XZR

    (247) 0x423b20 ADD	X19, X18, X12,LSL #3

    (247) 0x423b24 MADD	X12, X3, X22, XZR

    (247) 0x423b28 SBFM	X30, X13, #0, #31

    (247) 0x423b2c STR	D0, [X19, X13,SXTW #3]

    (247) 0x423b30 ADD	X27, X30, #1

    (247) 0x423b34 LDR	D0, [X1]

    (247) 0x423b38 ADD	X12, X2, X12,LSL #3

    (247) 0x423b3c STR	D0, [X12, X13,SXTW #3]

    (247) 0x423b40 CMP	X28, X30

    (247) 0x423b44 B.LT	423b58

    (247) 0x423b48 LDR	D0, [X17]

    (247) 0x423b4c STR	D0, [X19, X27,LSL #3]

    (247) 0x423b50 LDR	D0, [X1]

    (247) 0x423b54 STR	D0, [X12, X27,LSL #3]

    (247) 0x423b58 LDR	D0, [X17]

    (247) 0x423b5c ADD	X13, X22, #1

    (247) 0x423b60 MADD	X12, X0, X13, XZR

    (247) 0x423b64 MADD	X13, X3, X13, XZR

    (247) 0x423b68 ADD	X12, X18, X12,LSL #3

    (247) 0x423b6c ADD	X19, X2, X13,LSL #3

    (247) 0x423b70 STR	D0, [X12, X30,LSL #3]

    (247) 0x423b74 LDR	D0, [X1]

    (247) 0x423b78 STR	D0, [X19, X30,LSL #3]

    (247) 0x423b7c CMP	X28, X30

    (247) 0x423b80 B.LT	423a68

    (247) 0x423b84 LDR	D0, [X17]

    (247) 0x423b88 STR	D0, [X12, X27,LSL #3]

    (247) 0x423b8c LDR	D0, [X1]

    (247) 0x423b90 STR	D0, [X19, X27,LSL #3]

    (247) 0x423b94 B	423a68

0x423b98 HINT	#0

0x423b9c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.50 to 4.25 cycles (1.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.08	4.08	4.00	4.00	3.92	3.92	0.00	0.00	0.00	0.00	5.50	5.50	4.00	5.50	5.50
cycles	1.50	1.50	4.08	4.08	4.00	4.00	3.92	3.92	0.00	0.00	0.00	0.00	5.50	5.50	4.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

5% of peak load performance is reached (5.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
51% of peak store performance is reached (24.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4231e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LT 4232b0 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X24, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46d230>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X19, X24, X8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X7, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X6, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4232b4 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.08	4.08	4.00	4.00	3.92	3.92	0.00	0.00	0.00	0.00	5.50	5.50	4.00	5.50	5.50
cycles	1.50	1.50	4.08	4.08	4.00	4.00	3.92	3.92	0.00	0.00	0.00	0.00	5.50	5.50	4.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

5% of peak load performance is reached (5.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
51% of peak store performance is reached (24.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4231e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (25.0%)
B.LT 4232b0 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X24, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <46d230>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X19, X24, X8, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402e00 <@plt_start@+0x170>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X7, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X8, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X6, X8, X19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X7, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4232b4 <_Z14generate_chunkiR16global_variables.omp_outlined.2+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone .omp_outlined.2]–	0.04	0.03
▼Loop 249 - generate_chunk.cpp:85-123 - exec–	0.00	0.00
▼Loop 246 - generate_chunk.cpp:85-123 - exec–	0.00	0.00
○Loop 248 - generate_chunk.cpp:85-98 - exec	0.04	0.03
○Loop 252 - generate_chunk.cpp:85-123 - exec	0.00	0.00
○Loop 247 - generate_chunk.cpp:86-98 - exec	0.00	0.00
○Loop 251 - generate_chunk.cpp:86-123 - exec	0.00	0.00
○Loop 250 - generate_chunk.cpp:85-112 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code