OV - exec - Loop 626

	Loop Id: 626	Module: exec	Source: update_halo.cpp:527-530	Coverage: 0.01%

0x430ca4 LDR	W1, [SP, #20]

0x430ca8 ADRP	X0,

0x430cac ADD	X0, X0, #1904

0x430cb0 BL	402d80

0x430cb4 LDP	X20, X19, [SP, #128]

0x430cb8 LDP	X22, X21, [SP, #112]

0x430cbc LDP	X24, X23, [SP, #96]

0x430cc0 LDP	X26, X25, [SP, #80]

0x430cc4 LDP	X28, X27, [SP, #64]

0x430cc8 LDP	X29, X30, [SP, #48]

0x430ccc ADD	SP, SP, #144

0x430cd0 RET

0x430cd4 SUB	X11, X22, #2

0x430cd8 ADD	W10, W22, #2

0x430cdc SUB	X12, X22, #1

0x430ce0 UBFM	X15, X23, #59, #58

0x430ce4 UBFM	X4, X23, #61, #60

0x430ce8 AND	X14, X20, #6014

0x430cec MADD	X11, X23, X11, XZR

0x430cf0 SBFM	X10, X10, #0, #31

0x430cf4 MADD	X13, X23, X12, XZR

0x430cf8 SUB	X16, XZR, X15

0x430cfc SUB	X5, XZR, X4

0x430d00 AND	X12, X20, #4160

0x430d04 ADD	X11, X21, X11,LSL #3

0x430d08 ADD	X17, X21, X13,LSL #3

0x430d0c STR	X11, [SP, #24]

0x430d10 ADD	X11, X10, #2

0x430d14 MADD	X11, X23, X11, XZR

0x430d18 ADD	X19, X21, X11,LSL #3

0x430d1c ADD	W11, W9, W24

0x430d20 SUB	W11, W11, W20

0x430d24 ADD	W7, W11, #1

0x430d28 MADD	X11, X23, X10, XZR

0x430d2c ADD	X13, X23, X11

0x430d30 ADD	X2, X21, X11,LSL #3

0x430d34 MADD	X11, X23, X22, XZR

0x430d38 ADD	X18, X21, X13,LSL #3

0x430d3c SUB	X13, X22, #3

0x430d40 ADD	X3, X21, X11,LSL #3

0x430d44 MADD	X13, X23, X13, XZR

0x430d48 ADD	X0, X21, X13,LSL #3

0x430d4c ADD	X13, X10, #3

0x430d50 MADD	X13, X23, X13, XZR

0x430d54 ADD	X1, X21, X13,LSL #3

0x430d58 B	430d70

0x430d60 CMP	W9, W8

0x430d64 ADD	W9, W9, #1

0x430d68 ADD	W7, W6, #1

0x430d6c B.EQ	430ca4

0x430d70 SBFM	X6, X7, #0, #31

0x430d74 CMP	W20, #4

0x430d78 B.CS	430d84

0x430d7c ORR	X23, XZR, XZR

0x430d80 B	430df4

0x430d84 LDR	X11, [SP, #24]

0x430d88 ORR	X23, XZR, XZR

0x430d8c ORR	X24, XZR, X3

0x430d90 ORR	X25, XZR, X2

0x430d94 ORR	X26, XZR, X1

0x430d98 ORR	X27, XZR, X0

0x430d9c ORR	X28, XZR, X18

0x430da0 ORR	X30, XZR, X17

0x430da4 ORR	X13, XZR, X19

  (625) 0x430da8 LDR	D0, [X24, X6,LSL #3]

  (625) 0x430dac ADD	X23, X23, #4

  (625) 0x430db0 ADD	X24, X24, X16

  (625) 0x430db4 CMP	X14, X23

  (625) 0x430db8 STR	D0, [X25, X6,LSL #3]

  (625) 0x430dbc ADD	X25, X25, X15

  (625) 0x430dc0 LDR	D0, [X30, X6,LSL #3]

  (625) 0x430dc4 ADD	X30, X30, X16

  (625) 0x430dc8 STR	D0, [X28, X6,LSL #3]

  (625) 0x430dcc ADD	X28, X28, X15

  (625) 0x430dd0 LDR	D0, [X11, X6,LSL #3]

  (625) 0x430dd4 ADD	X11, X11, X16

  (625) 0x430dd8 STR	D0, [X13, X6,LSL #3]

  (625) 0x430ddc ADD	X13, X13, X15

  (625) 0x430de0 LDR	D0, [X27, X6,LSL #3]

  (625) 0x430de4 ADD	X27, X27, X16

  (625) 0x430de8 STR	D0, [X26, X6,LSL #3]

  (625) 0x430dec ADD	X26, X26, X15

  (625) 0x430df0 B.NE	430da8

0x430df4 CBZ	X12, 430d60

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 527 - 530

--------------------------------------------------------------------------------

527: #pragma omp parallel for simd

528:       for (int j = (x_min - depth + 1); j < (x_max + 1 + depth + 2); j++) {

529:         for (int k = 0; k < depth; ++k) {

530:           field.vol_flux_x(j, y_max + 2 + k) = field.vol_flux_x(j, y_max - k);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..90
Source	update_halo.cpp:527-529
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	2.69
Front-end cycles	8.13
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	12.50
P2 cycles	12.50
P3 cycles	12.50
P4 cycles	12.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.17
P10 cycles	2.83
P11 cycles	3.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.28
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.97
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.96

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..90
Source	update_halo.cpp:527-529
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	2.69
Front-end cycles	8.13
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	12.50
P2 cycles	12.50
P3 cycles	12.50
P4 cycles	12.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.17
P10 cycles	2.83
P11 cycles	3.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.28
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.97
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.96

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..90
Source file and lines	update_halo.cpp:527-530
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:527-530.

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:527-529.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.50 to 2.69 cycles (4.65x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 0.50 cycles (25.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	3.50	3.50	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.13
Overall L1	12.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

9% of peak load performance is reached (8.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <464ca8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #1904	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 402d80 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X11, X22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W10, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X15, X23, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X4, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND X14, X20, #6014	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SBFM X10, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X13, X23, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SUB X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X5, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND X12, X20, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [SP, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X19, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W11, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W11, W11, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W7, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X13, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X22, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X18, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X13, X22, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X13, X23, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X0, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X13, X23, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X1, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 430d70 <.omp_outlined..90+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W7, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 430ca4 <.omp_outlined..90+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X6, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CS 430d84 <.omp_outlined..90+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 430df4 <.omp_outlined..90+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X26, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X28, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X30, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBZ X12, 430d60 <.omp_outlined..90+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..90
Source file and lines	update_halo.cpp:527-530
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 0.50 cycles (25.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	3.50	3.50	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.13
Overall L1	12.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

9% of peak load performance is reached (8.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <464ca8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #1904	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 402d80 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X11, X22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W10, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X15, X23, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X4, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND X14, X20, #6014	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SBFM X10, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X13, X23, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SUB X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X5, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND X12, X20, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [SP, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X19, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W11, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W11, W11, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W7, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X13, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X11, X23, X22, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X18, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X13, X22, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X21, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X13, X23, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X0, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X13, X23, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X1, X21, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 430d70 <.omp_outlined..90+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W7, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 430ca4 <.omp_outlined..90+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X6, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CS 430d84 <.omp_outlined..90+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 430df4 <.omp_outlined..90+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X26, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X28, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X30, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBZ X12, 430d60 <.omp_outlined..90+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code