OV - exec - Loop 356

	Loop Id: 356	Module: exec	Source: advec_mom.cpp:181-211 [...]	Coverage: 3.99%

0x41e300 MOVPRFX	Z23, Z0

0x41e304 SDIV	Z23.D, P0/M, Z23.D, Z2.D

0x41e308 MOVPRFX	Z25, Z0

0x41e30c MLS	Z25.D, P0/M, Z23.D, Z2.D

0x41e310 ADD	Z25.D, Z4.D, Z25.D

0x41e314 ADD	Z24.D, Z3.D, Z23.D

0x41e318 MOVPRFX	Z26, Z24

0x41e31c SXTW	Z26.D, P0/M, Z24.D

0x41e320 SUBS	X12, X12, X10

0x41e324 ADD	Z28.D, Z17.D, Z23.D

0x41e328 MOVPRFX	Z29, Z28

0x41e32c SXTW	Z29.D, P0/M, Z28.D

0x41e330 ADD	Z30.D, Z18.D, Z23.D

0x41e334 ADD	Z23.D, Z22.D, Z23.D

0x41e338 ADD	Z0.D, Z0.D, Z1.D

0x41e33c SXTW	Z25.D, P0/M, Z25.D

0x41e340 MOVPRFX	Z27, Z25

0x41e344 MLA	Z27.D, P0/M, Z5.D, Z26.D

0x41e348 LD1D	{Z27.D}, P0/Z, [X23, Z27.D,LSL #3]    [5]

0x41e34c MOVPRFX	Z8, Z27

0x41e350 FABS	Z8.D, P0/M, Z27.D

0x41e354 FCMLT	P1.D, P0/Z, Z27.D, #0

0x41e358 SEL	Z31.D, P1, Z26.D, Z29.D

0x41e35c SEL	Z29.D, P1, Z29.D, Z26.D

0x41e360 SEL	Z23.D, P1, Z23.D, Z30.D

0x41e364 MOVPRFX	Z9, Z25

0x41e368 MLA	Z9.D, P0/M, Z29.D, Z6.D

0x41e36c LD1D	{Z9.D}, P0/Z, [X25, Z9.D,LSL #3]    [1]

0x41e370 SEL	Z28.D, P1, Z28.D, Z30.D

0x41e374 SXTW	Z23.D, P0/M, Z23.D

0x41e378 MAD	Z29.D, P0/M, Z7.D, Z25.D

0x41e37c MAD	Z31.D, P0/M, Z7.D, Z25.D

0x41e380 MAD	Z23.D, P0/M, Z7.D, Z25.D

0x41e384 FDIV	Z8.D, P0/M, Z8.D, Z9.D

0x41e388 MOVPRFX	Z9, Z8

0x41e38c FADD	Z9.D, P0/M, Z9.D, #1

0x41e390 LD1D	{Z29.D}, P0/Z, [X28, Z29.D,LSL #3]    [2]

0x41e394 LD1D	{Z23.D}, P0/Z, [X28, Z23.D,LSL #3]    [8]

0x41e398 LD1D	{Z31.D}, P0/Z, [X28, Z31.D,LSL #3]    [6]

0x41e39c FSUB	Z30.D, Z29.D, Z23.D

0x41e3a0 FSUB	Z10.D, Z31.D, Z29.D

0x41e3a4 FABD	Z23.D, P0/M, Z23.D, Z29.D

0x41e3a8 FMUL	Z30.D, Z30.D, Z10.D

0x41e3ac FMUL	Z9.D, Z9.D, Z23.D

0x41e3b0 FCMLE	P2.D, P0/Z, Z10.D, #0

0x41e3b4 EOR	P2.B, P0/Z, P2.B, P0.B

0x41e3b8 FCMGT	P1.D, P0/Z, Z30.D, #0

0x41e3bc MOVPRFX	Z30, Z31

0x41e3c0 FABD	Z30.D, P0/M, Z30.D, Z29.D

0x41e3c4 FSUB	Z31.D, Z19.D, Z8.D

0x41e3c8 LD1D	{Z24.D}, P1/Z, [X26, Z24.D,SXTW #3]    [3]

0x41e3cc LD1D	{Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]    [4]

0x41e3d0 FMUL	Z31.D, Z31.D, Z30.D

0x41e3d4 FDIV	Z31.D, P0/M, Z31.D, Z24.D

0x41e3d8 FDIVR	Z28.D, P0/M, Z28.D, Z9.D

0x41e3dc FADD	Z28.D, Z31.D, Z28.D

0x41e3e0 FMUL	Z24.D, Z24.D, Z28.D

0x41e3e4 FDIV	Z24.D, P0/M, Z24.D, Z20.D

0x41e3e8 FMINNM	Z23.D, P0/M, Z23.D, Z24.D

0x41e3ec FMINNM	Z23.D, P0/M, Z23.D, Z30.D

0x41e3f0 MOVPRFX	Z24, Z23

0x41e3f4 FNEG	Z24.D, P0/M, Z23.D

0x41e3f8 SEL	Z23.D, P2, Z23.D, Z24.D

0x41e3fc MOVPRFX	Z24, Z8

0x41e400 FSUBR	Z24.D, P0/M, Z24.D, #1

0x41e404 SEL	Z23.D, P1, Z23.D, Z21.D

0x41e408 FMAD	Z23.D, P0/M, Z24.D, Z29.D

0x41e40c MOVPRFX	Z24, Z25

0x41e410 MLA	Z24.D, P0/M, Z16.D, Z26.D

0x41e414 FMUL	Z23.D, Z27.D, Z23.D

0x41e418 ST1D	{Z23.D}, P0, [X22, Z24.D,LSL #3]    [7]

0x41e41c B.NE	41e300

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 181 - 211

--------------------------------------------------------------------------------

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.39
Bottlenecks	P6, P7,
Function	.omp_outlined..20
Source	advec_mom.cpp:181-211,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.50
CQA cycles if no scalar integer	30.50
CQA cycles if FP arith vectorized	30.50
CQA cycles if fully vectorized	30.50
Front-end cycles	9.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	30.50
P6 cycles	30.50
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00 - 2.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.23
Nb FLOP add-sub	24.00
Nb FLOP mul	20.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.39
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	81.69
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.12
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	62.50
Vector-efficiency ratio all	97.71
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.59
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	97.27

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.39
Bottlenecks	P6, P7,
Function	.omp_outlined..20
Source	advec_mom.cpp:181-211,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.50
CQA cycles if no scalar integer	30.50
CQA cycles if FP arith vectorized	30.50
CQA cycles if fully vectorized	30.50
Front-end cycles	9.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	30.50
P6 cycles	30.50
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00 - 2.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.23
Nb FLOP add-sub	24.00
Nb FLOP mul	20.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.39
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	81.69
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.12
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	62.50
Vector-efficiency ratio all	97.71
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.59
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	97.27

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..20
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:181-211
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU addition or subtraction instructions are used in vector version.
62% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
24: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	72
loop length	288
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	30.50	30.50	0.50	0.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	30.50	30.50	6.00	6.00	4.00	4.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	5.00-2.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Data deps.	2.00
Overall L1	30.50

Vectorization ratios

INT

all	71%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

7% of peak load performance is reached (7.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z25, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z25.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z25.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z24.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z28.D, Z17.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z30.D, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z5.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z8, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z8.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z31.D, P1, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P1, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z29.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z9.D}, P0/Z, [X25, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z29.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z31.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z23.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FDIV Z8.D, P0/M, Z8.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z9, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z9.D, P0/M, Z9.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z30.D, Z29.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z10.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z9.D, Z9.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLE P2.D, P0/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
FCMGT P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z30, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z30.D, P0/M, Z30.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z31.D, Z19.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P1/Z, [X26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z31.D, P0/M, Z31.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z28.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z24.D, P0/M, Z24.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMINNM Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z23.D, P0/M, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z24.D, P0/M, Z24.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z24, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z16.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z23.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41e300 <.omp_outlined..20+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..20
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:181-211
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU addition or subtraction instructions are used in vector version.
62% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
24: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 224 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	72
loop length	288
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	30.50	30.50	0.50	0.50	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	30.50	30.50	6.00	6.00	4.00	4.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	5.00-2.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Data deps.	2.00
Overall L1	30.50

Vectorization ratios

INT

all	71%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	90%
fma	100%
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.50 cycles. At this rate:

7% of peak load performance is reached (7.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z23.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z25, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z25.D, P0/M, Z23.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z25.D, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z24.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z26.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z28.D, Z17.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z30.D, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z23.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z27, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z27.D, P0/M, Z5.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z8, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z8.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z27.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z31.D, P1, Z26.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z29.D, P1, Z29.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z29.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z9.D}, P0/Z, [X25, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SEL Z28.D, P1, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z23.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z29.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z31.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z23.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FDIV Z8.D, P0/M, Z8.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z9, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z9.D, P0/M, Z9.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z30.D, Z29.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z10.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z23.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z9.D, Z9.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLE P2.D, P0/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
EOR P2.B, P0/Z, P2.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
FCMGT P1.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z30, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z30.D, P0/M, Z30.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z31.D, Z19.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P1/Z, [X26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z31.D, P0/M, Z31.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z28.D, P0/M, Z28.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z28.D, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z24.D, P0/M, Z24.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMINNM Z23.D, P0/M, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z23.D, P0/M, Z23.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P2, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z24.D, P0/M, Z24.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z23.D, P1, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z24, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z16.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z23.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41e300 <.omp_outlined..20+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code