OV - exec - Loop 275

0x41d060 MOVPRFX	Z18, Z0

0x41d064 SDIV	Z18.D, P0/M, Z18.D, Z2.D

0x41d068 ADD	Z19.D, Z3.D, Z18.D

0x41d06c MOVPRFX	Z20, Z0

0x41d070 MLS	Z20.D, P0/M, Z18.D, Z2.D

0x41d074 ADD	Z18.D, Z5.D, Z18.D

0x41d078 SUBS	X12, X12, X10

0x41d07c ADD	Z21.D, Z4.D, Z20.D

0x41d080 ADD	Z20.D, Z7.D, Z20.D

0x41d084 ADD	Z0.D, Z0.D, Z1.D

0x41d088 SXTW	Z18.D, P0/M, Z18.D

0x41d08c SXTW	Z19.D, P0/M, Z19.D

0x41d090 MOVPRFX	Z23, Z6

0x41d094 MUL	Z23.D, P0/M, Z23.D, Z19.D

0x41d098 ADR	Z24.D, [Z23, Z21.D,SXTW]    [4]

0x41d09c MUL	Z18.D, P0/M, Z18.D, Z6.D

0x41d0a0 ADR	Z22.D, [Z18, Z21.D,SXTW]    [5]

0x41d0a4 ADR	Z18.D, [Z18, Z20.D,SXTW]    [6]

0x41d0a8 ADR	Z20.D, [Z23, Z20.D,SXTW]    [1]

0x41d0ac SXTW	Z21.D, P0/M, Z21.D

0x41d0b0 LD1D	{Z22.D}, P0/Z, [X25, Z22.D,LSL #3]    [9]

0x41d0b4 LD1D	{Z24.D}, P0/Z, [X25, Z24.D,LSL #3]    [3]

0x41d0b8 LD1D	{Z18.D}, P0/Z, [X25, Z18.D,LSL #3]    [8]

0x41d0bc LD1D	{Z20.D}, P0/Z, [X25, Z20.D,LSL #3]    [2]

0x41d0c0 MAD	Z19.D, P0/M, Z17.D, Z21.D

0x41d0c4 FADD	Z22.D, Z22.D, Z24.D

0x41d0c8 FADD	Z18.D, Z22.D, Z18.D

0x41d0cc FADD	Z18.D, Z18.D, Z20.D

0x41d0d0 FMUL	Z18.D, Z18.D, Z16.D

0x41d0d4 ST1D	{Z18.D}, P0, [X23, Z19.D,LSL #3]    [7]

0x41d0d8 B.NE	41d060

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 86 - 88

--------------------------------------------------------------------------------

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.10
Bottlenecks	P6, P7,
Function	.omp_outlined..8#0x41cf50
Source	advec_mom.cpp:86-88,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	10.50
Front-end cycles	3.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.33
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	73.33
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	64.29
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	87.50
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	73.21
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.10
Bottlenecks	P6, P7,
Function	.omp_outlined..8#0x41cf50
Source	advec_mom.cpp:86-88,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	10.50
Front-end cycles	3.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	12.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.33
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	73.33
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	64.29
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	87.50
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	73.21
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..8#0x41cf50
Source file and lines	advec_mom.cpp:86-88
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:86-88
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
64% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: addition or subtraction
4: multiply

The binary loop is loading 128 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	12.00	12.00	0.50	0.50	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	12.00	12.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.88
Data deps.	2.00
Overall L1	12.00

Vectorization ratios

INT

all	69%
load	50%
store	100%
mul	100%
add-sub	54%
fma	100%
other	57%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	50%
store	100%
mul	100%
add-sub	64%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z20.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z18.D, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z21.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z20.D, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z23, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z23.D, P0/M, Z23.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z24.D, [Z23, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z18.D, P0/M, Z18.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z22.D, [Z18, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z18.D, [Z18, Z20.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z20.D, [Z23, Z20.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z22.D}, P0/Z, [X25, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X25, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X25, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X25, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z22.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z18.D}, P0, [X23, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41d060 <.omp_outlined..8+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..8#0x41cf50
Source file and lines	advec_mom.cpp:86-88
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:86-88
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
64% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

12: addition or subtraction
4: multiply

The binary loop is loading 128 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	12.00	12.00	0.50	0.50	2.50	2.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	12.00	12.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.88
Data deps.	2.00
Overall L1	12.00

Vectorization ratios

INT

all	69%
load	50%
store	100%
mul	100%
add-sub	54%
fma	100%
other	57%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	50%
store	100%
mul	100%
add-sub	64%
fma	100%
div/sqrt	100%
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d060

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z18, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z18.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z19.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z20.D, P0/M, Z18.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z18.D, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z21.D, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z20.D, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z18.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z19.D, P0/M, Z19.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z23, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z23.D, P0/M, Z23.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z24.D, [Z23, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z18.D, P0/M, Z18.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z22.D, [Z18, Z21.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z18.D, [Z18, Z20.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z20.D, [Z23, Z20.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
LD1D {Z22.D}, P0/Z, [X25, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X25, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X25, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X25, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z19.D, P0/M, Z17.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z22.D, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z22.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, Z18.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z18.D}, P0, [X23, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41d060 <.omp_outlined..8+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code